JPH04133540A - Cyclic communication system - Google Patents

Abstract

PURPOSE:To reduce the burden of a communication controller by storing cyclic data which are more frequently accessed by CPUs in a shared memory and cyclic data which are less frequently accessed by CPUs in a cyclic memory. CONSTITUTION:A communication controller 4 stores cyclic data which are more frequently accessed by CPUs 1 and 1 or 2 and 2 of the cyclic data received by the controller 4 through a transmission line 11 at regular periods at a previously indicated address of a shared memory 3 through a system bus 10. The controller 4, on the other hand, stores cyclic data which are less frequently accessed by the CPUs 1 and 1 or 2 and 2 at a previously indicated address of a cyclic memory 5. When the memories are properly used in such way, the data transferring burden on the system bus 10 is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a cyclic communication system capable of processing cyclic data received via a transmission path at high speed and efficiently by a plurality of CPUs. .

[Conventional technology]

FIG. 2 is a block diagram of a conventional cyclic communication system shown in, for example, Japanese Unexamined Patent Publication No. 63-97037. (4) A rigorous cyclic memory for storing the cyclic data received by the CPU 1
fi+ and CPTJ2 (!l and communication controller (
41 is connected to the friend system bus (IIIH), which is a transmission line through which cyclic data is transmitted.

Next, the operation will be explained.

The communication controller (4) stores cyclic data received periodically via the transmission path (111) at a pre-specified t address in the cyclic memory (5).

Next, CPUI il+ or CPt221! 1 issues a read request to the communication controller (4) via the system bus (to) in order to access necessary cyclic data t in the cyclic memory (6). If the communication controller (4) is not executing cyclic data reception processing from the transmission line (111) when the read request is received, it will accept the read request and write cyclic memo 1 based on the request content. 5), take out the necessary boot controller and read the data via the system bus to the requesting CPUll1l or CPU2i! Send to I. On the other hand, if the communication controller (4) is executing the process of receiving cyclic data from the transmission path (11) at the time of the above IJ-do request, the CPU filt will continue to receive data from the CPtJ2f21 until the process is completed. Requests will be awaited. Conversely, while the communication controller (4) is executing a read request from CPU2 tel, the communication controller (41C transmission line + 11
) cannot perform cyclic data reception processing.

In response to a read request for the cyclic memory (6) from CPUx (11 and CPU2i!I), the communication controller (4
) is performed at regular intervals at any arbitrary time, regardless of whether cyclic data reception processing is being executed or not.

[Problem to be solved by the invention]

Since the conventional cyclic communication system is configured as described above, the communication controller is required to perform both cyclic data reception processing and cyclic data read processing from the CPU, which increases the load on the communication controller. At the same time, there are problems such as slow cyclic data access from the CPU. Particularly in multiprocessor configurations where multiple CPUs are connected to the system bus, the processing speed decreases significantly.

This invention was made to solve the above problems, and provides high-performance cyclic communication that enables high-speed cyclic reception processing and cyclic data access by reducing the load on the communication controller. [Detailed means for solving the problem] A cyclic communication system according to the present invention has a plurality of C
A shared memory that can be accessed by the PUs is provided on the system bus, and cyclic data that is accessed frequently by each CPU is stored in the shared memory, while cyclic data that is accessed less frequently is stored in the cyclic memory. It's a great thing.

[Effect]

In the cyclic communication system of the present invention, among the cyclic data received from the transmission path to the communication controller, data that is frequently accessed from the CPU is stored in the shared memory on the system bus, and data that is accessed infrequently is transferred to the shared memory on the system bus. Store in memory. This ninth CPU
The nine cyclic data stored in the shared memory can be accessed at high speed via the system bus without starting the communication controller.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, fll is CPU1.12+, CPU2,
(31 is a shared memory that can be commonly accessed by CI'U1 tl11? and CPU21!+, (4) is a communication controller, and til&! is a memory for storing part of the next cyclic data received by the communication controller (4). Cyclic memory, αω the above CPtJI Ill and CPU
2 (!l) and the system bus to which the shared memory (3) and the communication controller (41 are connected; (!l) is the transmission line through which the signal data is transmitted.) Next, the operation will be explained.

Communication controller (4) c) Of the cyclic data received at regular intervals via the transmission line (11), the CPUI 11
117'C, the cyclic data frequently accessed by CPU2 fil is stored at a pre-specified address on the shared memory (3) via the system bus (101t". On the other hand, CPLJ1 (1) or CPLJ211 is frequently accessed. stores cyclic data that will not be accessed at a pre-specified address on the cyclic memory (5). By using memory differently in this way, the data transfer load on the system bus (IOI) can be reduced. , which cyclic data is stored in shared memory (
Allocation information regarding which memory to store data in, 3) and cyclic memory (5), is set to an initial value when the system is started up. The settings of this information can be changed after system startup.

Next, the operation when the CPU 11it accesses cyclic data will be described. The operation of CPt1212) is also similar. First, when accessing cyclic data on the shared memory (3) that requires frequent access, the shared memory (3) is directly accessed via the system bus [0)' without starting the CPUI (11a trauma controller (4)). ) can be read at high speed. Communication controller 14) Since it is not necessary to start up all the communication controllers, the effect is particularly great in a multiprocessor configuration.

Next, when accessing data on the cyclic memory (6) that does not need to be accessed frequently, use the CPU
A read request is sent to the communication controller (4) via the IT system bus 00). Communication controller +
41i At the time when the above read request is received, the read request will be accepted if the cyclic data reception process from the transmission line (Ill) is not executed, and the cyclic memo will be sent from the cyclic memo January 6 according to the request content. The data is retrieved and sent via the system bus (1otr) to the data requester Crux Ill. When the read request is received, the communication controller (4) connects the transmission line (Ill
If the cyclic data reception process from
The request from the CPU ill will wait until the process is completed. Also, conversely, the communication controller (41
While executing a read request from the CPUI, the communication controller (41) cannot perform cyclic data reception processing from the transmission line (11).
Since access to the cyclic memory (5) from Ill is not performed frequently, the load on the communication controller (4) does not become heavy.

Note that in the above embodiment, the case where cyclic data is received and processed from the transmission path is explained, but the shared memory (3
) and the cyclic memory (5) are transmitted to the transmission path, the same effects as in the above embodiments are achieved.

However, in the above embodiment, the information on whether to store the received cyclic data in the shared memo January 3) or the cyclic memo January 6) is set in the communication controller (4). It is also possible to store the information in the received cyclic data itself so that there is no need to specially set the information to the communication controller (41).

9. Cyclic memory (6) Communication controller]
4) Alternatively, the communication controller (4) may be equipped with a complete cyclic memo (5).

〔Effect of the invention〕

As described above, according to the present invention, the cyclic communication system is configured such that multiple CPUs can directly access cyclic data on the shared memory without activating the communication controller, thereby enabling high-speed data processing. There is an effect that can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a cyclic communication system according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional cyclic communication system. In the figure, (11 and (21 are CPU, +31
is shared memory, f41i communication controller, (5) is cyclic memo! J, (]0)l'! The system bus is a 1lllld transmission line. In addition, in the figures, the same or equivalent parts are indicated by the same reference numerals.

Claims (1)

[Claims] A system bus to which a plurality of CPUs are connected, a communication controller installed between the system bus and the transmission line to control communication, and a cyclic controller connected to the communication controller to store cyclic data periodically received from the transmission line. In a cyclic communication system comprising a memory, in which each of the CPUs performs predetermined data processing using the cyclic data, a shared memory shared by the CPUs is provided on the system bus,
A cyclic communication system characterized in that cyclic data that is frequently accessed from each of the CPUs is selected and stored in the shared memory.