JPH04278659A - Inter-multiprocessor communication system - Google Patents

Abstract

PURPOSE:To minimize the influence of the data transfer speed to the processing ability of a high rank processor by using a processor bus with high efficiency without deteriorating the data transfer speed of the processor bus. CONSTITUTION:Lower rank processors 2 and 3 register the data transmission requests to the transmission request flags 8 and 9 of a high rank processor 1 when these transmission requests are produced. A transmission permission circuit 11 of the processor 1 checks the free state of a data memory 6 for the processor 2, for example, to which a transmission request is previously registered. Then the circuit 11 gives a transmission permission to a data transmission circuit 14 of the processor 2 when the free state of the memory 6 is confirmed. The circuit 14 transfers the data stored in a primary store memory 13 to a less significant processor data memory 6 of the processor 1. A high rank CPU 10 confirms the data transmission request with an interruption when the transmission request is registered to the flag 8 or 9 or scans periodically both flags 8 and 9 in order to discriminate the presence or absence of data in the data memories 6 and 7 for the processors 2 and 3 and to fetch the data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system between processors, and more particularly to a communication system between hierarchical multiprocessors.

0002

2. Description of the Related Art There are the following two types of conventional multiprocessor communication systems. In the first system shown in FIG. 2, an upper processor 1, a lower processor 2, and a lower processor 3 are connected to a processor bus 4. processor bus 4
is composed of a memory bus, an I/O bus, or a time-divided data bus of a higher-level processor. Data communication from the lower processor 2 to the upper processor 1 can be performed in two cases: the upper processor 1 requests specific data from the lower processor 2, and the lower processor 2 requests data communication. In this method, data is communicated from the lower processor 2 to the upper processor 1 according to instructions from the upper processor 1, and the lower processor 3 is not given the right to communicate data, and the upper processor 1 has only one window for data communication. The data communication request from the lower processor 3 is placed in a waiting state until a transmission instruction from the upper processor 1 is received after the data communication regarding the lower processor 2 is completed.

In the second system shown in FIG. 3, an upper processor 1, a lower processor 2, and a lower processor 3 are connected by a processor bus 4. The processor bus 4 is configured as a time-division transmission path, and channels for data communication are allocated to a plurality of lower processors such as lower processor 2 and lower processor 3 within one frame.
By simultaneously transmitting data using time-division multiplexed transmission paths in response to data transmission requests that occur simultaneously to a plurality of lower-level processors, data is stored in the memory 5 allocated to each lower-level processor of the higher-level processor. The configuration was such that the upper processors read sequentially.

0004

[Problems to be Solved by the Invention] In this first conventional method, even if data transmission requests are issued to multiple lower processors at the same time, only the lower processor designated by the higher processor is given exclusive rights to the bus. The data communication speed depends on the communication speed of the lower processor, which may place a burden on the upper processor, or the higher processor processes data communication from multiple lower processors sequentially, resulting in latency for the lower processor. This problem can occur and affect the processing capacity of the system.

In the second method, data from the lower processor is sent to the upper processor if the reception memory in the upper processor is free, regardless of the processing state of the upper processor; There is a problem in that the data transmission capacity per unit time decreases depending on the number of channels allocated to each lower-level processor and the number of lower-level processors, which affects the data acquisition speed of the higher-level processor and affects the processing capacity of the system.

An object of the present invention is to provide a multiprocessor communication system that allows efficient use of a processor bus without reducing the data transfer speed of the processor bus, and that minimizes the influence of the data transfer speed on the processing ability of a host processor. Our goal is to provide the following.

[0007]

Means for Solving the Problems The multiprocessor communication system of the present invention provides a processor system in which an upper processor and a plurality of lower processors are connected by a processor bus to execute distributed processing, in which each of the lower processors is connected to the upper processor. a data memory capable of storing data from a processor; means for transmitting a data transmission request from the lower processor to the upper processor; means for granting data transmission permission to a lower processor; means for the lower processor to send a data transmission request to the upper processor; a primary storage memory for temporarily storing data to be transmitted to the upper processor; and means for transmitting the transmission data accumulated in the primary storage memory to the host processor via the processor bus based on the data transmission permission.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention when there are two lower processors. Connected to the upper CPU 10 of the upper processor 1 are a data transmission flag 8 for the lower processor 2 and a data transmission flag 9 for the lower processor 3, which store the presence or absence of a data transmission request from the lower processor 2 and the lower processor 3. The contents are also sent to the transmission permission circuit 11. Furthermore, within the upper processor 1 there is a data memory 6 for the lower processor 2.
and a data memory 7 for the lower processor 3. The lower processor 2 includes a primary storage memory 13, a data sending circuit 14, a transmission request circuit 15, and a lower CPU 12, and the lower processor 3 has a similar configuration. The data memory 6 for the lower processor 2 and the data memory 7 for the lower processor 3 of the upper processor 1 are connected to the primary storage memories 13 of the lower processors 2 and 3 via a processor bus 4. One side of the data transmission request flag bus 16 is the transmission request circuit 15 of the lower processor 2 and the lower processor 3, the data transmission request flag 8 for the lower processor 2, and the transmission request flag 9 for the lower processor 3.
The other side of the data transmission request flag bus 16 is connected to the transmission permission circuit 11 of the upper processor 1 and the data sending circuits 14 of the lower processors 2 and 3.

When a data transmission request to the upper processor 1 occurs simultaneously in the lower processor 2 and the lower processor 3, the data desired to be transmitted is stored in each primary storage memory 13, and the lower CP of each lower processor
Using the transmission request circuit 15 of U12, the upper processor 1
The lower processor 2 data transmission request flag 8 and the lower processor 3 data transmission request flag 9 are set.

For example, when a data transmission request from the lower processor 2 is inputted first, the transmission permission circuit 11 of the upper processor 1 determines whether the data memory 6 for the lower processor 2 is free, and if it is empty, the upper processor Transmission permission is given to the data sending circuit 14 of the lower processor 2 without instructions from the CPU 10. The data transmission circuit 14 of the lower processor 2 controls the primary storage memory 13 of the lower processor 2 and transfers the stored data to the data memory 6 for the lower processor 2 via the processor bus 4. When the data transfer from the lower processor 2 is completed, the transmission permission circuit 11 of the upper processor 1 is activated as soon as the processor bus 4 becomes empty, regardless of whether the upper CPU 10 takes in the data from the data memory 6 for the lower processor 2. The free space in the data memory 7 for the lower processor 3 and the set state of the data transmission request flag 9 for the lower processor 3 are checked. As a result, if a data transmission request is identified from the lower processor 3, the transmission permission circuit 11 uses the data transmission request flag bus 16 to send the data transmission request to the data transmission circuit 14 of the lower processor 3.
It gives transmission permission to the lower processor 3 and causes the data to be transferred from the primary storage memory 13 of the lower processor 3 to the data memory 7 for the lower processor 3 in the higher processor 1.

When the transmission request flag is set in the data transmission request flag 8 for the lower processor 2 or the data transmission request flag 9 for the lower processor 3, the upper CPU 10 confirms the transmission request by an interrupt, or cancels the data transmission. By periodically scanning the request flag, it is determined whether the data is present in the data memory and the data is fetched.

[0013]

As explained above, the present invention provides a data memory for each lower processor in the upper processor, and provides a transmission permission circuit in the upper processor to permit data transmission from the lower processor. Even if multiple processors issue data transmission requests at the same time, regardless of the operation of the upper processor, if the processor bus is free and the data memory corresponding to the lower processor in the upper processor is free, the data will be sent sequentially from the lower processor. can be transferred to the data memory in the upper processor, which has the effect of efficiently using the processor bus without reducing the data transfer speed of the processor bus.As a result, the upper processor does not need to be aware of the state of the processor bus. Since it is only necessary to read the data memory in the upper processor, the effect of data transfer speed on the processing capacity of the upper processor can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example of a multiprocessor communication system.

FIG. 3 is a block diagram showing a conventional example of a multiprocessor communication system.

[Explanation of symbols]

1 Upper processor 2 Lower processor 2 3 Lower processor 3 4 Processor bus 5 Data memory 6 Data memory 7 for lower processor 2
Data memory for lower processor 3 8 Data transmission request flag for lower processor 2 9 Data transmission request flag for lower processor 3 10 Upper CPU 11 Transmission permission circuit 12 Lower CPU 13 Primary storage memory 14 Data transmission circuit 15 Transmission request circuit

Claims (1)

[Claims] 1. A processor system in which an upper processor and a plurality of lower processors are connected by a processor bus and execute distributed processing, wherein the upper processor includes a data memory capable of storing data from each of the lower processors; means for transmitting a data transmission request from a processor to the upper processor; means for granting data transmission permission to the lower processor based on the data transmission request from the lower processor and data memory free information in the upper processor; means for a processor to send a data transmission request to the higher-level processor; a primary storage memory for temporarily storing data to be transmitted to the higher-level processor; and transmission data accumulated in the primary storage memory based on the data transmission permission from the higher-level processor. a multiprocessor communication system, comprising means for sending the above-mentioned host processor to the higher-level processor via a processor bus.