JPH04130760A - Semiconductor chip carrier - Google Patents

Semiconductor chip carrier

Info

Publication number
JPH04130760A
JPH04130760A JP25329890A JP25329890A JPH04130760A JP H04130760 A JPH04130760 A JP H04130760A JP 25329890 A JP25329890 A JP 25329890A JP 25329890 A JP25329890 A JP 25329890A JP H04130760 A JPH04130760 A JP H04130760A
Authority
JP
Japan
Prior art keywords
external connection
connection terminal
semiconductor chip
solder
chip carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25329890A
Other languages
Japanese (ja)
Inventor
Masami Otada
小多田 正美
Shinobu Watabe
忍 渡部
Eitaro Matsui
栄太郎 松居
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP25329890A priority Critical patent/JPH04130760A/en
Publication of JPH04130760A publication Critical patent/JPH04130760A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405Edge mounted components, e.g. terminals

Abstract

PURPOSE:To increase the junction strength of the conductive pattern of a printed-wiring board and an external connecting terminal while lessening the dispersion thereof by a method wherein a recession for a solder well is formed on the junction surface of the external connecting terminal. CONSTITUTION:Within an external connecting terminal 21, a trench 25 for a solder well is formed on the part near the printed wiring board 1 periphery of a junction surface 21a while the trench 25 is in the width W 1-5 times of the thickness (t) of the external connecting terminal 21 and in the depth D1/3-1/2 times of the thickness (t). At this time, the trench 25 is formed extending over the whole width of the external connecting terminal 21. In such a constitution, within the junction part of the conductive pattern 3 of the printed wiring board 1, the junction part in sufficient solder thickness and even length can be stably secured so that the junction strength may sufficiently be increased while lessening the dispersion thereof.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体チップキャリアに関する。[Detailed description of the invention] [Industrial application field] This invention relates to semiconductor chip carriers.

〔従来の技術〕[Conventional technology]

半導体チップキャリアは、第4図にみるように、チップ
搭載面1aの周囲に導電パターン3が形成されたプリン
ト配線板1と外部接続端子2・・・とを備え、各外部接
続端子2・・・は一端が各導電ツクターン3・・・にハ
ンダ接合されている。各外部接続端子2・・・の他端は
一つの金属リング5で繋がっている。
As shown in FIG. 4, the semiconductor chip carrier includes a printed wiring board 1 on which a conductive pattern 3 is formed around a chip mounting surface 1a, and external connection terminals 2.・One end is soldered to each conductive turn 3 . The other end of each external connection terminal 2 is connected by one metal ring 5.

この半導体チップキャリアは、以下のようにして使われ
る。
This semiconductor chip carrier is used as follows.

第5図にみるように、チップ搭載面1aに半導体チップ
10を搭載し、同半導体チ・ノブ10と導電パターン3
をワイヤー11で接続した後、半導体チップ保護用の樹
脂封止膜12を形成しておし)く。ついで、半導体チッ
プキャリアAをマザーボードBに載せ、外部接続端子2
・・・の他側とマザーボードBの導電パターン(図示省
略)をノ1ンダ接合する(2次実装)。
As shown in FIG. 5, a semiconductor chip 10 is mounted on the chip mounting surface 1a, and the semiconductor chip 10 and the conductive pattern 3 are
After connecting them with wires 11, a resin sealing film 12 for protecting the semiconductor chip is formed. Next, place the semiconductor chip carrier A on the motherboard B, and connect the external connection terminal 2.
. . . The other side and the conductive pattern (not shown) of the motherboard B are connected by soldering (secondary mounting).

外部接続端子2には、第6図にみるように、厚みが一定
の外部接続端子25のものの他、第7図にみるように、
出願人の先の出願(特願平1−278031号)により
提案された接合部分が肉厚の外部接続端子26がある。
The external connection terminals 2 include external connection terminals 25 with a constant thickness as shown in FIG. 6, as well as external connection terminals 25 with a constant thickness as shown in FIG.
There is an external connection terminal 26 with a thick joint portion proposed in the applicant's previous application (Japanese Patent Application No. 1-278031).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第6.7図に示した半導体チップキャリアの場合、導電
パターン3と外部接続端子25.26のハンダ接合が十
分なものと言えないという問題がある。
In the case of the semiconductor chip carrier shown in FIG. 6.7, there is a problem that the solder joint between the conductive pattern 3 and the external connection terminals 25 and 26 is not sufficient.

導電パターンと外部接続端子の接合強度を第8図に示す
ピーリング方式で調べてみると、接合強度は十分でなく
バラツキも大きいのである。30はクランプ用爪である
。外部接続端子26の場合、凸部後端面のハンダ部分が
あるため、多少はましであるが、このハンダ部分は安定
して形成されるわけでないから本質的な解決にはならな
い。
When the bonding strength between the conductive pattern and the external connection terminal was investigated using the peeling method shown in FIG. 8, it was found that the bonding strength was not sufficient and had large variations. 30 is a clamping claw. In the case of the external connection terminal 26, there is a solder portion on the rear end surface of the convex portion, so this is somewhat better, but since this solder portion is not formed stably, it is not an essential solution.

半導体チップキャリアを信頼性試験(例えば、温度サイ
クル試験)にかけてから、導電パターンと外部接続端子
の接合強度を同様に調べてみると、接合強度が極端に低
下するものが出る。
If a semiconductor chip carrier is subjected to a reliability test (for example, a temperature cycle test) and then the bonding strength between the conductive pattern and the external connection terminal is examined in the same manner, the bonding strength may be extremely reduced in some carriers.

このように、ハンダ接合が十分でないのは、端子接合面
と導電パターン面の間のハンダ厚みに2〜50ハと大き
なバラ・ンキがあるからである。特に接合個所のプリン
ト配線板周縁側でのハンダ厚みが薄いと接合強度の低下
が激しいようである。
The reason why the solder joint is not sufficient is that there is a large variation in the thickness of the solder between the terminal joint surface and the conductive pattern surface, ranging from 2 to 50 mm. Particularly, if the solder thickness is thin on the peripheral edge side of the printed wiring board at the joint location, the joint strength seems to drop significantly.

この発明は、上記事情に鑑み、プリント配線板の導電パ
ターンと外部接続端子の接合強度が十分に高(バラツキ
も少ない半導体チップキャリアを提供することを課題と
する。
In view of the above circumstances, it is an object of the present invention to provide a semiconductor chip carrier in which the bonding strength between a conductive pattern of a printed wiring board and an external connection terminal is sufficiently high (with little variation).

〔課題を解決するための手段〕[Means to solve the problem]

前記課題を解決するため、請求項1記載の発明は、チッ
プ搭載面の周囲に導電パターンが形成されたプリント配
線板と外部接続端子とを備え、同外部接続端子が前記導
電パターンにハンダ接合されている半導体チップキャリ
アにおいて、前記外部接続端子の接合面にハンダ溜まり
用の凹部を形成した構成をとるようにしている。
In order to solve the above problem, the invention according to claim 1 includes a printed wiring board on which a conductive pattern is formed around a chip mounting surface and an external connection terminal, and the external connection terminal is soldered to the conductive pattern. In this semiconductor chip carrier, a concave portion for a solder pool is formed on the bonding surface of the external connection terminal.

凹部の形成位置や形状に関しては様々な態様がある。形
成位置に関しては、プリント配線板周縁に近い位置にあ
ることが好ましく、形状に関しては、例えば、第1図に
みるように、外部接続端子21の幅全長に渡って形成さ
れた溝21であることが好ましい。具体的には、例えば
、請求項2のように、ハンダ溜まり用の凹部は、接合面
のプリント配線板周縁側の位置に幅方向に形成された溝
であって、同溝は、外部接続端子厚みtの1〜5倍の幅
と外部接続端子厚みtの1/3〜1/2の深さがあるも
のが挙げられる。
There are various aspects regarding the formation position and shape of the recess. Regarding the formation position, it is preferable that it be close to the periphery of the printed wiring board, and regarding the shape, for example, as shown in FIG. 1, it is a groove 21 formed over the entire width of the external connection terminal 21. is preferred. Specifically, for example, as in claim 2, the recess for the solder pool is a groove formed in the width direction at a position on the peripheral edge side of the printed wiring board of the bonding surface, and the groove is a groove for forming an external connection terminal. Examples include those having a width of 1 to 5 times the thickness t and a depth of 1/3 to 1/2 of the external connection terminal thickness t.

以下、この発明の半導体チップキャリアを、より具体的
に説明する。
Hereinafter, the semiconductor chip carrier of the present invention will be explained in more detail.

この発明にかかる半導体チップキャリアは、第4図にみ
るように、プリント配線板1と多数の外部接続端子2・
・・を備えている。プリント配線板1は中央にチップ搭
載面(キャビティ部)laを有するとともにチップ搭載
面の周囲にCu導電パターン3・・・が多数形成されて
いる。各外部接続端子2・・・は一端が各導電パターン
3・・・それぞれにハンダ接合されている。各外部接続
端子2・・・の他端が一つの金属リング5で繋がった状
態にある。勿論、各外部接続端子2・・・の他端が金属
リングで繋がっておらず、個々に分断されていてもよい
As shown in FIG. 4, the semiconductor chip carrier according to the present invention includes a printed wiring board 1 and a large number of external connection terminals 2.
It is equipped with... The printed wiring board 1 has a chip mounting surface (cavity portion) la in the center, and a large number of Cu conductive patterns 3 are formed around the chip mounting surface. One end of each external connection terminal 2 is soldered to each conductive pattern 3. The other ends of each external connection terminal 2 are connected by one metal ring 5. Of course, the other ends of each external connection terminal 2 may not be connected by the metal ring, but may be separated individually.

チップ搭載面1aは、通常、凹面やフラツト面である。The chip mounting surface 1a is usually a concave surface or a flat surface.

プリント配線板10基材は、全体が絶縁材からなるもの
に限らず、金属材表面に絶縁層を設けたものであっても
よい。
The base material of the printed wiring board 10 is not limited to being entirely made of an insulating material, and may be a material having an insulating layer provided on the surface of a metal material.

外部接続端子2は、通常、厚み0.15〜0.35鶴程
度の板体であり、材質としては4270イ(Ni42%
、Fe残部)やCu合金などが例示される。
The external connection terminal 2 is usually a plate with a thickness of about 0.15 to 0.35mm, and is made of 4270I (42% Ni).
, Fe balance), Cu alloy, etc.

ハンダ接合は、2次実装段階で熱が加わった際に溶融・
破損しないように、固相線280℃以上の高温ハンダに
よりなされていることが望ましい。例えば、S n 3
.5%、A g 1.5%、Pb95%の高温ハンダや
S n 5.0%、A g 2.5%、Pb92.5%
の高温ハンダ等が例示される。この他、固相線温度が1
83℃の共晶ハンダや固相線温度が220〜260℃レ
ベルのハンダを用いることもできる。使われるハンダは
、普通、クリームハンダである。
Solder joints may melt or melt when heated during the secondary mounting stage.
To avoid damage, it is desirable to use high temperature solder with a solidus temperature of 280° C. or higher. For example, S n 3
.. 5%, Ag 1.5%, Pb 95% high temperature solder or Sn 5.0%, Ag 2.5%, Pb 92.5%
Examples include high-temperature solder. In addition, the solidus temperature is 1
It is also possible to use eutectic solder at 83°C or solder whose solidus temperature is at the level of 220 to 260°C. The solder used is usually cream solder.

ハンダ接合を行う場合、クリームハンダをメタルマスク
を使うスクリーン印刷法等により導電パターン3・・・
上に塗布し、外部接続端子2・・・の接合面を合せて配
置し、加熱し接合固定するようにする。なお、外部接続
端子2はハンダ等による表面処理を予め施しておく。加
熱は、光ビーム(キセノンランプ) 、YAGレーザ、
近赤外線ランプなどで行う。
When performing solder joints, conductive patterns 3 are printed using cream solder using a screen printing method using a metal mask, etc.
The bonding surfaces of the external connection terminals 2 are placed together and heated to be bonded and fixed. Note that the external connection terminal 2 is subjected to surface treatment using solder or the like in advance. Heating is done using a light beam (xenon lamp), YAG laser,
This is done using a near-infrared lamp, etc.

続いて、この発明における外部接続端子と導電パターン
の接合個所まわりの具体的な構成を、第1〜3図を参照
しながら説明する。
Next, the specific structure around the joint portion of the external connection terminal and the conductive pattern in the present invention will be explained with reference to FIGS. 1 to 3.

第1図(a)の場合、外部接続端子21は接合面21a
のプリント配線板周縁に近い所にハンダ溜まり用の溝2
5が形成されており、同溝25は、外部接続端子厚みt
の1〜5倍の幅Wと外部接続端子厚みtの1/3〜1/
2の深さDがある。溝25は、第1図(b)にみるよう
に、外部接続端子21の全幅に渡って形成されているも
のである。
In the case of FIG. 1(a), the external connection terminal 21 is connected to the joint surface 21a.
Groove 2 for solder pool near the periphery of the printed wiring board.
5 is formed, and the groove 25 has an external connection terminal thickness t.
1 to 5 times the width W and 1/3 to 1/ of the external connection terminal thickness t.
There is a depth D of 2. The groove 25 is formed over the entire width of the external connection terminal 21, as shown in FIG. 1(b).

第2図の場合、外部接続端子22は接合面22aのプリ
ント配線板周縁に近い所にハンダ溜まり用の溝26が形
成されている。この溝26も、外部接続端子厚みtの1
〜5倍の幅Wと接続端子厚みtの1/3〜1/2の深さ
Dをもち、さらに、外側寄り側面26bには角度θ=3
0〜60°の傾斜が付いており、外部接続端子21の全
幅に渡って形成されている。
In the case of FIG. 2, the external connection terminal 22 has a solder pool groove 26 formed on the joint surface 22a near the periphery of the printed wiring board. This groove 26 also has a thickness t of the external connection terminal.
It has a width W of ~5 times and a depth D of 1/3 to 1/2 of the connection terminal thickness t, and an angle θ=3 on the outer side surface 26b.
It has an inclination of 0 to 60 degrees and is formed over the entire width of the external connection terminal 21.

なお、前記の両溝25.26の場合、溝底前方側の角2
5a、26aには丸み(アール)が付いている。角25
a、26aの丸みは外部接続端子厚みtの115〜1/
2のアール(R)である。
In addition, in the case of the above-mentioned both grooves 25 and 26, the corner 2 on the front side of the groove bottom
5a and 26a are rounded. corner 25
The roundness of a and 26a is 115 to 1/ of the external connection terminal thickness t.
It is R (R) of 2.

第3図の場合、外部接続端子23の接合面23aには、
第1.2図に示すと同様の溝25(26)に加えて前方
にハンダ溜まり用の小溝27・・・が3個形成されてい
る。各小満27は、外部接続端子厚みtの1/5〜1/
2程度の幅を持ち、略四角や半円の断面形状を持つ。小
満26も外部接続端子23の全幅に渡って形成されてい
る。なお、小満27は1個であってもよい。
In the case of FIG. 3, on the joint surface 23a of the external connection terminal 23,
As shown in FIG. 1.2, in addition to similar grooves 25 (26), three small grooves 27 for collecting solder are formed at the front. Each small portion 27 is 1/5 to 1/1/2 of the external connection terminal thickness t.
It has a width of about 2 mm and a roughly square or semicircular cross-sectional shape. The small part 26 is also formed over the entire width of the external connection terminal 23. Note that the number of small mantles 27 may be one.

この発明のハンダ溜まり用の凹部は、上記のような溝に
限らず、外部接続端子の全幅より短めに穿たれ側面には
開いていない窪み状のものであってもよい。外部接続端
子も、全長にわたり厚みが一定である必要はなく、第7
図に示すような接合部分が肉厚の端子であってもよい。
The concave portion for the solder pool of the present invention is not limited to the above-mentioned groove, but may be a concave portion that is formed to be shorter than the entire width of the external connection terminal and not open to the side surface. The external connection terminal also does not need to have a constant thickness over its entire length;
The joint portion may be a thick terminal as shown in the figure.

これらの接合固定の場合、第1〜3図にみるように、プ
リント配線板周縁の接合個所に溝による十分なハンダ溜
まり空間があり、ここで十分なハンダ厚みが確保される
In the case of these bonding and fixing, as shown in FIGS. 1 to 3, there is a sufficient solder pool space formed by the groove at the bonding location on the periphery of the printed wiring board, and a sufficient solder thickness is ensured here.

続いて、この発明の半導体チップキャリアの使い方を説
明する。
Next, how to use the semiconductor chip carrier of the present invention will be explained.

第5図にみるように、半導体チップ搭載面1aに半導体
チップ10を搭載し、同半導体チップ10と導電パター
ン3・・・先端をワイヤー11で接続した後、半導体チ
ップ10保護のために樹脂封止膜12を形成しておいて
、半導体チップキャリアAをマザーボードBに載せ、外
部接続端子2の他端側(外部接続端子は適当な段階で切
断・折り曲げ等の必要な処理がなされる)とマザーボー
ドBの導電パターン(図示省略)をハンダ接合し、2次
搭載処理を行う。樹脂封止膜12の形態には、半導体チ
ップ部とワイヤ接続部を封止したポンティングの形態と
半導体チップキャリア全体を封止した形態がある。
As shown in FIG. 5, after mounting the semiconductor chip 10 on the semiconductor chip mounting surface 1a and connecting the ends of the semiconductor chip 10 and the conductive pattern 3 with wires 11, the semiconductor chip 10 is sealed with resin to protect it. After forming the protective film 12, the semiconductor chip carrier A is placed on the motherboard B, and the other end side of the external connection terminal 2 (the external connection terminal is subjected to necessary processing such as cutting and bending at an appropriate stage). A conductive pattern (not shown) on the motherboard B is soldered and a secondary mounting process is performed. The resin sealing film 12 has two types: a ponting type in which the semiconductor chip portion and the wire connection portion are sealed, and a type in which the entire semiconductor chip carrier is sealed.

〔作   用〕[For production]

この発明の半導体チップキャリアの場合、プリント配線
板の導電パターンと外部接続端子の接合個所では、十分
なハンダ厚みのある接合部分が均一な長さで安定して確
保されるようになる。これは、外部接続端子の接合面に
ある凹部によるノ\ンダ溜まり空間が設けられており、
ここではAンダ厚みが十分に厚いからである。そのため
、接合強度が十分に高くバラツキも少なくなる。
In the case of the semiconductor chip carrier of the present invention, at the joint portion between the conductive pattern of the printed wiring board and the external connection terminal, a joint portion having a sufficient solder thickness and a uniform length can be stably secured. This is because there is a space for the solder to accumulate due to the recess in the joint surface of the external connection terminal.
This is because the Anda thickness is sufficiently thick here. Therefore, the bonding strength is sufficiently high and variations are reduced.

〔実 施 例〕〔Example〕

続いて、この発明の詳細な説明する。この発明は下記の
実施例に限らない。
Next, the present invention will be explained in detail. This invention is not limited to the following embodiments.

プリント配線板として、導電パターンが幅0.2〜0.
−5鶴、長さ1〜1.51富、パターンピッチ0.4〜
0.65mのCuJiの導電パターンを有するものを準
備した。
As a printed wiring board, the conductive pattern has a width of 0.2 to 0.
-5 cranes, length 1~1.51 wealth, pattern pitch 0.4~
A sample having a 0.65 m CuJi conductive pattern was prepared.

外部接続端子には、材質に関しては42アロイ(N i
 42%、Fe残り)材のもの、Cu合金材のものを準
備し、形状に関しては、第1〜3図のものをそれぞれ準
備した。外部接続端子は導電Xターンよりやや小さく、
板厚みは0.15〜0.351程度である。ハンダ溜ま
り用の溝の加工はエツチングで行った。ハンダによる表
面処理も予め施した。
The external connection terminal is made of 42 alloy (Ni
42% Fe remaining) material and a Cu alloy material were prepared, and as for the shapes, those shown in Figs. 1 to 3 were prepared, respectively. The external connection terminal is slightly smaller than the conductive X turn,
The plate thickness is about 0.15 to 0.351. The groove for the solder pool was created by etching. Surface treatment with solder was also applied in advance.

S n 3.5%、A g 1.5%、pb95%の高
温ハンダ、S n 5.0%、A g 2.5%、P 
b 92.5%の高温ハンダのクリームハンダを、メタ
ルマスクを使うシルクスクリーン法で導電パターンに塗
布し、前述したようにして接合固定を行った。
High temperature solder with S n 3.5%, A g 1.5%, PB 95%, S n 5.0%, A g 2.5%, P
b A cream solder of 92.5% high temperature solder was applied to the conductive pattern by a silk screen method using a metal mask, and bonding and fixing was performed as described above.

このようにして得た半導体チップキャリアの外部接続端
子と導電パターンの間の接合強度を調べたところ、従来
よりも優れていた。第8図に示すピーリング方式で強度
試験を実施すると、30〜60°傾斜した時点で剥離が
始まり、この時の負荷荷重に耐え得る接合強度が確保さ
れたことが確認できた。
When the bonding strength between the external connection terminal and the conductive pattern of the semiconductor chip carrier thus obtained was examined, it was found to be superior to that of the conventional method. When a strength test was conducted using the peeling method shown in FIG. 8, it was confirmed that peeling started at a tilt angle of 30 to 60 degrees, and that a bonding strength capable of withstanding the applied load at this time was secured.

信頼性試験を行った後の比較においても、実施例の半導
体チップキャリアの接合の方が従来のものより優れてい
ることが確認された。
A comparison after conducting a reliability test also confirmed that the bonding of the semiconductor chip carrier of the example was superior to that of the conventional one.

〔発明の効果〕〔Effect of the invention〕

以上に述べたように、請求項1.2記載の半導体チップ
キャリアは、プリント配線板の導電パターンと外部接続
端子の接合個所では十分なハンダ厚みのある接合部分が
均一な長さで安定して確保されるため、接合強度が十分
に高くバラツキも少ない。
As described above, in the semiconductor chip carrier according to claim 1.2, the joint portion with sufficient solder thickness is uniform and stable at the joint portion between the conductive pattern of the printed wiring board and the external connection terminal. Therefore, the bonding strength is sufficiently high and there is little variation.

請求項2記載の半導体チップキャリアは、十分なハンダ
厚みのある接合部分がプリント配線板周縁側にあるため
、接合強度がより高くバラツキもより少なくなる。
In the semiconductor chip carrier according to the second aspect of the present invention, since the bonded portion with sufficient solder thickness is located on the peripheral edge side of the printed wiring board, the bonding strength is higher and variation is reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は、この発明にかかる半導体チップキャリ
アの要部構成例をあられす部分断面図、第1図(b)は
、同半導体チップキャリアの外部接続端子の接合面まわ
りをあられす部分平面図、第2図および第3図は、この
発明にかかる半導体チップキャリアの他の要部構成例を
あられす部分断面図、第4図は、この発明の半導体チッ
プキャリアの一例外観をあられす斜視図、第5図は、同
半導体チップキャリアの使用状態をあられす断面図、第
6図および第7図は、それぞれ、従来の半導体チップキ
ャリアの要部構成をあられす部分断面図、第8図は、接
合強度を測定する際の様子をあられす要部断面図である
。 A・・・半導体チップキャリア  1・・・プリント配
線板  2.21.22.23・・・外部接続端子3・
・・導電パターン  21a、22a、23a・・・接
合面   25.26・・・ハンダ溜まり用の溝代理人
 弁理士  松 本 武 彦 第 図 第3図 第4 図 第 5図 第 図 介
FIG. 1(a) is a partial cross-sectional view showing an example of the main structure of a semiconductor chip carrier according to the present invention, and FIG. 2 and 3 are partial plan views, and FIG. 3 is a partial cross-sectional view showing another example of the structure of the main parts of the semiconductor chip carrier according to the present invention, and FIG. FIG. 5 is a perspective view showing the semiconductor chip carrier in use, and FIGS. 6 and 7 are partial sectional views showing the main structure of the conventional semiconductor chip carrier. FIG. 8 is a sectional view of the main part showing the state when measuring the bonding strength. A... Semiconductor chip carrier 1... Printed wiring board 2.21.22.23... External connection terminal 3.
...Conductive patterns 21a, 22a, 23a...Joint surfaces 25.26...Grooves for solder pool Agent Patent attorney Takehiko MatsumotoFigure 3Figure 4Figure 5Figure 5

Claims (1)

【特許請求の範囲】 1 チップ搭載面の周囲に導電パターンが形成されたプ
リント配線板と外部接続端子とを備え、同外部接続端子
が前記導電パターンにハンダ接合されている半導体チッ
プキャリアにおいて、前記外部接続端子の接合面にハン
ダ溜まり用の凹部が形成されていることを特徴とする半
導体チップキャリア。 2 ハンダ溜まり用の凹部が接合面のプリント配線板周
縁側の位置に幅方向に形成された溝であって、同溝は、
外部接続端子厚みtの1〜5倍の幅と外部接続端子厚み
tの1/3〜1/2の深さがある請求項1記載の半導体
チップキャリア。
[Scope of Claims] 1. A semiconductor chip carrier comprising a printed wiring board on which a conductive pattern is formed around a chip mounting surface and an external connection terminal, the external connection terminal being soldered to the conductive pattern. A semiconductor chip carrier characterized in that a recess for a solder pool is formed on a bonding surface of an external connection terminal. 2. A recessed portion for collecting solder is a groove formed in the width direction at a position on the peripheral edge side of the printed wiring board on the bonding surface, and the groove is
2. The semiconductor chip carrier according to claim 1, wherein the semiconductor chip carrier has a width of 1 to 5 times the thickness t of the external connection terminal and a depth of 1/3 to 1/2 the thickness t of the external connection terminal.
JP25329890A 1990-09-21 1990-09-21 Semiconductor chip carrier Pending JPH04130760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25329890A JPH04130760A (en) 1990-09-21 1990-09-21 Semiconductor chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25329890A JPH04130760A (en) 1990-09-21 1990-09-21 Semiconductor chip carrier

Publications (1)

Publication Number Publication Date
JPH04130760A true JPH04130760A (en) 1992-05-01

Family

ID=17249344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25329890A Pending JPH04130760A (en) 1990-09-21 1990-09-21 Semiconductor chip carrier

Country Status (1)

Country Link
JP (1) JPH04130760A (en)

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JP2007287828A (en) * 2006-04-14 2007-11-01 Matsushita Electric Ind Co Ltd Solid-state electrolytic capacitor, and its manufacturing method
JP2009177201A (en) * 2003-03-31 2009-08-06 Sanyo Electric Co Ltd Method of producing circuit board connector
JP2010033790A (en) * 2008-07-28 2010-02-12 Panasonic Corp Electronic component and method of manufacturing same
JP2013214423A (en) * 2012-04-02 2013-10-17 Showa Tekkusu:Kk Rail-bond
TWI497614B (en) * 2012-06-29 2015-08-21 Universal Scient Ind Shanghai Assembly structure
WO2017221601A1 (en) * 2016-06-23 2017-12-28 株式会社東海理化電機製作所 Module and method for manufacturing same
JP2021034324A (en) * 2019-08-29 2021-03-01 矢崎総業株式会社 Shield connector
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009177201A (en) * 2003-03-31 2009-08-06 Sanyo Electric Co Ltd Method of producing circuit board connector
JP2007287828A (en) * 2006-04-14 2007-11-01 Matsushita Electric Ind Co Ltd Solid-state electrolytic capacitor, and its manufacturing method
JP2010033790A (en) * 2008-07-28 2010-02-12 Panasonic Corp Electronic component and method of manufacturing same
JP2013214423A (en) * 2012-04-02 2013-10-17 Showa Tekkusu:Kk Rail-bond
TWI497614B (en) * 2012-06-29 2015-08-21 Universal Scient Ind Shanghai Assembly structure
WO2017221601A1 (en) * 2016-06-23 2017-12-28 株式会社東海理化電機製作所 Module and method for manufacturing same
CN113748505A (en) * 2019-04-25 2021-12-03 京瓷株式会社 Wiring substrate, package for electronic component, and electronic device
EP3961692A4 (en) * 2019-04-25 2023-05-24 Kyocera Corporation Wiring board, electronic member package, and electronic device
US11889618B2 (en) 2019-04-25 2024-01-30 Kyocera Corporation Wiring board, electronic component package, and electronic apparatus
JP2021034324A (en) * 2019-08-29 2021-03-01 矢崎総業株式会社 Shield connector
CN112448209A (en) * 2019-08-29 2021-03-05 矢崎总业株式会社 Shielded connector
US11289855B2 (en) 2019-08-29 2022-03-29 Yazaki Corporation Shield connector having improved bonding strength to a substrate

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