JPH04125958A - Thin film capacitor - Google Patents
Thin film capacitorInfo
- Publication number
- JPH04125958A JPH04125958A JP24687890A JP24687890A JPH04125958A JP H04125958 A JPH04125958 A JP H04125958A JP 24687890 A JP24687890 A JP 24687890A JP 24687890 A JP24687890 A JP 24687890A JP H04125958 A JPH04125958 A JP H04125958A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- conductive layer
- electrode
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 title claims description 17
- 239000010409 thin film Substances 0.000 title claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 12
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 5
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 4
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910021332 silicide Inorganic materials 0.000 abstract description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 229910002370 SrTiO3 Inorganic materials 0.000 abstract 1
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はシリコン電極上に形成された薄膜キャパシタの
構造に関し、特にシリコン電極上に第１及び第２の材料
からなる導電層が形成され、その上に誘電体薄膜及び上
部電極が順に積層形成された構造を有する薄膜キャパシ
タに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the structure of a thin film capacitor formed on a silicon electrode, and in particular, a conductive layer made of first and second materials is formed on the silicon electrode, The present invention relates to a thin film capacitor having a structure in which a dielectric thin film and an upper electrode are sequentially laminated thereon.
〔従来の技術］
従来、この種の薄膜キャパシタとしては、シリコン電極
上に直接にスパッタ法により誘電体膜。[Prior Art] Conventionally, this type of thin film capacitor has been manufactured by forming a dielectric film directly on a silicon electrode by sputtering.
上部電極を順に積層形成した構造（特願平１−２１７９
１８号）、又はシリコン電極上にＴａ、 Ｔｉなとの少
なくとも１種類の高融点金属からなる第１層及びＰｔ。Structure in which upper electrodes are laminated in order (Japanese Patent Application No. 1-2179)
No. 18) or a first layer consisting of at least one kind of high melting point metal such as Ta or Ti on a silicon electrode and Pt.
Ｐｄの少なくとも１種の材料からなる第２層とから構成
される導電層上に誘電体膜、上部電極を順に積層形成し
た構造（特願平１−２３８４８４号）のものがある。There is a structure (Japanese Patent Application No. 1-238484) in which a dielectric film and an upper electrode are laminated in this order on a conductive layer consisting of a second layer made of at least one type of Pd.
［発明が解決しようとする課題］
上述した従来の構造の薄膜キャパシタにおいて、シリコ
ン電極上に直接にスパッタ法により誘電体を形成した場
合には、シリコン電極表面が誘電体を形成するときに酸
化され誘電率の高い誘電体を形成してもシリコン電極と
誘電体との界面に存在する低誘電率の二酸化シリコンの
ために薄膜キャパシタ全体の容量を大きくすることが制
限されるという欠点がある。また、シリコン電極に第１
及び第２の材料からなる導電層を形成し、その上に誘電
体、上部電極を順に積層形成した構造の場合には、誘電
体膜の堆積時及び熱処理時にシリコン電極からシリコン
が第１の導電層を拡散して第２の導電層に達し、第２の
導電層の材料とシリサイドを形成し、さらに誘電体との
界面に低誘電率の酸化物を形成することとなり、薄膜キ
ャパシタ全体の容量を大きくするためには、シリコン電
極からのシリコンが第２の導電層へ拡散するのを制御す
る必要があり、第２の導電層の厚みを十分に厚くし、ま
た誘電体膜の堆積及び熱処理温度の上限を制限しなけれ
ばならないが、導電層を厚くすると薄膜キャパシタ素子
製作プロセスにおいて導電層の加工性が悪くなり、また
誘電体膜の堆積及び熱処理温度の上限を制限すると誘電
体膜自身の誘電率を大きくすることが困難になるという
欠点がある。[Problems to be Solved by the Invention] In the thin film capacitor having the conventional structure described above, when a dielectric is formed directly on the silicon electrode by sputtering, the surface of the silicon electrode is oxidized when forming the dielectric. Even if a dielectric material with a high dielectric constant is formed, there is a drawback that increasing the capacitance of the entire thin film capacitor is limited due to the low dielectric constant silicon dioxide present at the interface between the silicon electrode and the dielectric material. In addition, the first
In the case of a structure in which a conductive layer made of a second material is formed, and a dielectric material and an upper electrode are laminated in this order on top of the conductive layer, silicon from the silicon electrode becomes the first conductive layer during deposition of the dielectric film and during heat treatment. It diffuses through the layer to reach the second conductive layer, forms a silicide with the material of the second conductive layer, and further forms a low dielectric constant oxide at the interface with the dielectric, reducing the capacitance of the entire thin film capacitor. In order to increase It is necessary to limit the upper limit of the temperature, but if the conductive layer is made thicker, the processability of the conductive layer will deteriorate in the thin film capacitor element fabrication process, and if the upper limit of the deposition and heat treatment temperature of the dielectric film is restricted, the dielectric film itself will deteriorate. A drawback is that it is difficult to increase the dielectric constant.
本発明の目的はシリコン電極からのシリコンの導電層と
誘電体膜の界面への拡散を防止した薄膜キャパシタを提
供することにある。An object of the present invention is to provide a thin film capacitor in which diffusion of silicon from a silicon electrode to an interface between a conductive layer and a dielectric film is prevented.
［課題を解決するための手段］
前記目的を達成するため、本発明に係る薄膜キャパシタ
においては、導電層と、誘電体と、上部電極とを有する
薄膜キャパシタであって、導電層と上部電極とは、誘電
体を間に介装して積層形成されたものであり、
導電層は、シリコン電極上に形成された第１層と、該第
１層上に形成された第２層とから構成されたものであり
、
第１層は、Ｂ、Ｐ、Ａｓ、Ｎ、Ａｒの少なくとも１種の
元素をイオン注入したＴａ、 Ｔｉの少なくとも１種の
材料からなるものであり、
第２層は、Ｐｔ、 Ｐｄの少なくとも１種の材料からな
るものである。[Means for Solving the Problems] In order to achieve the above object, a thin film capacitor according to the present invention includes a conductive layer, a dielectric, and an upper electrode, wherein the conductive layer and the upper electrode is formed by laminating layers with a dielectric interposed therebetween, and the conductive layer is composed of a first layer formed on a silicon electrode and a second layer formed on the first layer. The first layer is made of at least one material of Ta and Ti into which at least one element of B, P, As, N, and Ar is ion-implanted, and the second layer is It is made of at least one material of Pt and Pd.
シリコン電極上に形成される第１の導電層がＢ。 The first conductive layer formed on the silicon electrode is B.
Ｐ、 Ａｓ、 Ｎ、 Ａｒの少なくとも１種の元素をイ
オン注入したＴａ、 Ｔｉなどの少なくとも１種類の高
融点金属からなり、第１の導電層上に形成される第２の
導電層がＰｔ、 Ｐｄの少なくとも１種類の材料からな
り、この第１及び第２の導電層の組からなる導電層上に
誘電体膜、上部電極が順に積層形成されている。したが
って、シリコン電極からのシリコンが第２の導電層に拡
散されることが制限され、シリサイドの形成が防止され
ることとなる。The second conductive layer formed on the first conductive layer is made of at least one kind of high melting point metal such as Ta or Ti into which at least one element of P, As, N, or Ar is ion-implanted. A dielectric film and an upper electrode are laminated in this order on a conductive layer made of at least one type of material, Pd, and made up of a set of first and second conductive layers. Therefore, diffusion of silicon from the silicon electrode into the second conductive layer is restricted, and silicide formation is prevented.
〔実施例］ 次に、本発明について図面を参照して説明する。〔Example] Next, the present invention will be explained with reference to the drawings.
（実施例１）
第１図は、本発明の実施例１を示す縦断面図であって、
誘電体として５ｒＴｉＯ，を使用した薄膜キャパシタを
示すものである。(Example 1) FIG. 1 is a longitudinal cross-sectional view showing Example 1 of the present invention,
This figure shows a thin film capacitor using 5rTiO as a dielectric.
図において、１はＰ型シリコン基板、２はＮ型拡散層、
３はＰをイオン注入したＴｉ層、４はＰｔ層、５は５ｒ
ＴｉＯ，層、６はＡＱ電極である。作製プロセスは公知
の半導体集積回路作製プロセスを使用した。In the figure, 1 is a P-type silicon substrate, 2 is an N-type diffusion layer,
3 is a Ti layer into which P is ion-implanted, 4 is a Pt layer, and 5 is a 5r layer.
TiO,layer 6 is an AQ electrode. A known semiconductor integrated circuit manufacturing process was used for the manufacturing process.
Ｐ型シリコン基板１上に薄膜キャパシタの下部電極とな
るＮ型拡散層２を作製し、Ｎ型拡散層２上にＴｉ層３を
スパッタ法により１０〜１１００ｎ堆積し、Ｔｉ層３に
、Ｐをエネルギー４０〜１ｏｏｋｅＶ、ドーズ量１０１
〜１０”ｃｍ−”でイオン注入する。その後、スパッタ
法によりＴｉ層層上上Ｐｔ層４を１０〜ｌｏｏｎｍ堆積
し、さらにｐｔ層層上上５ｒＴｉＯ，層５を基板温度４
００℃で１００〜３００ｎｍ堆積し、その後酸素中で４
５０℃、２時間の熱処理を行い、光リソグラフィー及び
プラズマエツチング技術により５ｒＴｉＯ，層５・ｐｔ
層４・Ｔｉ層３を第１図の形状に加工する。最後に、上
部電極としてｋＱ電極６を１．ｏＩＩｍ堆積し、光リソ
グラフィー及びプラズマエツチングによりＡ［電極６を
加工して第１図に示す構造の薄膜キャパシタを作製した
。An N-type diffusion layer 2 that will become the lower electrode of a thin film capacitor is fabricated on a P-type silicon substrate 1. A Ti layer 3 of 10 to 1100 nm is deposited on the N-type diffusion layer 2 by sputtering, and P is applied to the Ti layer 3. Energy 40-1ookeV, dose 101
Ion implantation at ~10"cm-". Thereafter, a Pt layer 4 is deposited on the Ti layer by sputtering to a thickness of 10 to 100 m thick, and a layer 5 of 5rTiO is further deposited on the PT layer at a substrate temperature of 4.
Deposit 100-300 nm at 00 °C, then 4
After heat treatment at 50°C for 2 hours, 5rTiO layer 5.pt was formed using photolithography and plasma etching techniques.
Layer 4/Ti layer 3 is processed into the shape shown in FIG. Finally, 1.kQ electrode 6 is installed as the upper electrode. A thin film capacitor having the structure shown in FIG. 1 was fabricated by depositing oIIm and processing the electrode 6 by photolithography and plasma etching.
本発明の薄膜キャパシタでは、Ｔｉ層３にイオン注入し
ていないものに比べて耐熱性が５０℃以上改善され、よ
り高温の熱処理にも耐えることができるため、誘電体の
誘電率を大きくすることができる。また、実施例では、
Ｐをイオン注入しているが、注入エネルギーを選ぶこと
により、Ｂ、Ａｓ。In the thin film capacitor of the present invention, the heat resistance is improved by 50°C or more compared to a capacitor in which ions are not implanted into the Ti layer 3, and it can withstand higher temperature heat treatment, so the dielectric constant of the dielectric material can be increased. I can do it. In addition, in the example,
Although P is ion-implanted, B and As can be implanted by selecting the implantation energy.
Ｎ、Ａｒイオンを注入しても同様の効果がある。Similar effects can be obtained by implanting N and Ar ions.
（実施例２） 第２図は本発明の実施例２を示す縦断面図である。(Example 2) FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention.
図において、１１はＰ型シリコン基板、１２はＮ型拡散
層、１３はＰ型拡散層、１４及び１５はＢをイオン注入
したＴａ及びＴ１層、１６はＰｔ層、１７は誘電体とな
る５ｒＴｉＯ，層、１８は上部電極となるＡＱ電極であ
る。In the figure, 11 is a P-type silicon substrate, 12 is an N-type diffusion layer, 13 is a P-type diffusion layer, 14 and 15 are Ta and T1 layers into which B ions are implanted, 16 is a Pt layer, and 17 is a 5rTiO dielectric. , layer 18 is an AQ electrode serving as an upper electrode.
作製プロセスは実施例１と同様であるが、イオン注入は
Ｔａ層１４及び１１層１５を堆積した後、Ｂをエネルギ
ー２０〜４０ｋｅＶ、 ドーズ量１０” 〜１０’
” ａｍ−”でイオン注入した。また、Ｔａ層１４の厚
さは１０〜１００ｎｒｎ、 Ｔｉ層１５の厚さは１０〜
１１００ｎ、 ５ｒＴｉＯ，層１７の厚さは１０（１−
３００ｎｍ、 ＡＱｌｉ極１８は１．０１１ｍである。The manufacturing process is the same as in Example 1, but after depositing the Ta layers 14 and 11 layers 15, ion implantation is performed using B at an energy of 20 to 40 keV and a dose of 10'' to 10'.
Ion implantation was performed using "am-". Further, the thickness of the Ta layer 14 is 10 to 100 nrn, and the thickness of the Ti layer 15 is 10 to 100 nrn.
1100n, 5rTiO, thickness of layer 17 is 10(1-
300 nm, AQli pole 18 is 1.011 m.
［発明の効果］
以上説明したように本発明は、シリコン電極上に形成さ
れる導電層が第１層と第１層上に形成される第２層とか
ら構成され、第１層がＢ、Ｐ、ＡＳＮ、Ａｒの少なくと
も１種の元素をイオン注入されたＴａ、 Ｔｉの少なく
とも１種の材料からなり、第２層がＰｔ、 Ｐｄの少な
くとも１種の材料からなる構造であるため、シリコン電
極からのシリコンの第２層への拡散を制限し、第２層の
材料とシリサイドを形成することを防ぐことにより、導
電層の第１層の膜厚をあまり厚くすることなく、耐熱性
の改善をすることができ、誘電体の誘電率を大きくする
ことができる効果がある。[Effects of the Invention] As explained above, in the present invention, the conductive layer formed on the silicon electrode is composed of a first layer and a second layer formed on the first layer, and the first layer is made of B, The silicon electrode is made of at least one material of Ta or Ti into which at least one element of P, ASN, or Ar is ion-implanted, and the second layer is made of at least one material of Pt or Pd. By restricting the diffusion of silicon into the second layer and preventing the formation of silicide with the material of the second layer, the heat resistance can be improved without increasing the thickness of the first layer of the conductive layer. This has the effect of increasing the dielectric constant of the dielectric.
第１図は、本発明の実施例１を示す縦断面図、第２図は
本発明の実施例２を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention, and FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention.
Claims (1)
ャパシタであって、 導電層と上部電極とは、誘電体を間に介装して積層形成
されたものであり、 導電層は、シリコン電極上に形成された第１層と、該第
１層上に形成された第２層とから構成されたものであり
、 第１層は、Ｂ、Ｐ、Ａｓ、Ｎ、Ａｒの少なくとも１種の
元素をイオン注入したＴａ、Ｔｉの少なくとも１種の材
料からなるものであり、 第２層は、Ｐｔ、Ｐｄの少なくとも１種の材料からなる
ものであることを特徴とする薄膜キャパシタ。(1) A thin film capacitor having a conductive layer, a dielectric, and an upper electrode, where the conductive layer and the upper electrode are laminated with a dielectric interposed between them, and the conductive layer is , a first layer formed on a silicon electrode, and a second layer formed on the first layer, and the first layer is made of at least B, P, As, N, and Ar. 1. A thin film capacitor comprising at least one material of Ta and Ti into which one kind of element is ion-implanted, and a second layer comprising at least one material of Pt and Pd.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24687890A JPH0652774B2 (en) | 1990-09-17 | 1990-09-17 | Thin film capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24687890A JPH0652774B2 (en) | 1990-09-17 | 1990-09-17 | Thin film capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04125958A true JPH04125958A (en) | 1992-04-27 |
| JPH0652774B2 JPH0652774B2 (en) | 1994-07-06 |
Family
ID=17155085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24687890A Expired - Lifetime JPH0652774B2 (en) | 1990-09-17 | 1990-09-17 | Thin film capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0652774B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5693595A (en) * | 1995-06-06 | 1997-12-02 | Northrop Grumman Corporation | Integrated thin-film terminations for high temperature superconducting microwave components |
| KR100393197B1 (en) * | 1996-10-31 | 2003-11-01 | 삼성전자주식회사 | Ferroelectric capacitor and manufacturing method thereof |
| CN105070786A (en) * | 2015-07-28 | 2015-11-18 | 昆明物理研究所 | High temperature oxidation resistant lead-out electrode of reading circuit and preparation method of electrode |
-
1990
- 1990-09-17 JP JP24687890A patent/JPH0652774B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5693595A (en) * | 1995-06-06 | 1997-12-02 | Northrop Grumman Corporation | Integrated thin-film terminations for high temperature superconducting microwave components |
| KR100393197B1 (en) * | 1996-10-31 | 2003-11-01 | 삼성전자주식회사 | Ferroelectric capacitor and manufacturing method thereof |
| CN105070786A (en) * | 2015-07-28 | 2015-11-18 | 昆明物理研究所 | High temperature oxidation resistant lead-out electrode of reading circuit and preparation method of electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0652774B2 (en) | 1994-07-06 |
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