JPH04116964A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH04116964A JPH04116964A JP2237424A JP23742490A JPH04116964A JP H04116964 A JPH04116964 A JP H04116964A JP 2237424 A JP2237424 A JP 2237424A JP 23742490 A JP23742490 A JP 23742490A JP H04116964 A JPH04116964 A JP H04116964A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- ceramic substrate
- opening
- resistor
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 239000000919 ceramic Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims description 42
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 235000008314 Echinocereus dasyacanthus Nutrition 0.000 description 1
- 240000005595 Echinocereus dasyacanthus Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置用パッケージに関し、特に内部に終
端抵抗を有する高周波用の半導体装置用パッケージに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor device, and more particularly to a package for a high frequency semiconductor device having a termination resistor therein.
従来、内部に終端抵抗を有する高周波用の半導体装置用
パッケージは、特開昭６３−１８７６５０などに示され
ている。Conventionally, a package for a high frequency semiconductor device having an internal termination resistor is disclosed in Japanese Patent Application Laid-Open No. 187650/1983.
次に、この例について図面を用いて説明する。Next, this example will be explained using the drawings.
第４図は従来の半導体装置用パッケージの一例を示す要
部斜視図である。FIG. 4 is a perspective view of essential parts of an example of a conventional semiconductor device package.
セラミック基板２ Ｅ 、 ２ ｐ 、 ２ ａ ｔ
’！順次積層されて一体化されており、中央部に開口部
をもって階段状、枠状に形成されている。そして放熱板
１上に接着固定され、その開口部の放熱板１上に半導体
チップ８を搭載する。Ceramic substrate 2E, 2p, 2at
'! They are sequentially laminated and integrated into a step-like, frame-like shape with an opening in the center. Then, it is adhesively fixed onto the heat sink 1, and the semiconductor chip 8 is mounted on the heat sink 1 in the opening.
階段状の開口部のセラミック基板２Ｅの上面にはメタラ
イズパターン配線２１Ｅが形成され、半導体チップ８表
面に形成された電極８１とボンディングワイヤ９により
接続される。A metallized pattern wiring 21E is formed on the upper surface of the ceramic substrate 2E in the stepped opening, and is connected to an electrode 81 formed on the surface of the semiconductor chip 8 by a bonding wire 9.
階段状の開口部のセラミック基板２Ｆの上面には、抵抗
体２６Ｆ！、２６７２とメタライズ接地配線２５、と電
極２７Ｆｌ、２７Ｆ□とが形成され、抵抗体２６Ｆ、の
一端はメタライズ接地配線２５．に他＄
端は電極２７Ｆ１に、抵抗２６Ｆ２の一端は電極２７□
に他端は電極２７２２にそれぞれ接続されている。On the top surface of the ceramic substrate 2F in the stepped opening is a resistor 26F! , 2672, the metallized ground wiring 25, and electrodes 27Fl, 27F□ are formed, and one end of the resistor 26F is connected to the metallized ground wiring 25. The other end is connected to the electrode 27F1, and one end of the resistor 26F2 is connected to the electrode 27□
and the other end is connected to an electrode 2722, respectively.
電極ｚ７ｐ□はメタライズパターン配線２１ｔと。The electrode z7p□ is connected to the metallized pattern wiring 21t.
電極２７，２はセラミック基板２゜の上面に形成された
メタライズ電源配線２３．とそれぞれボンデインクワイ
ヤ９により接続されている。The electrodes 27, 2 are formed on the metallized power supply wiring 23. formed on the upper surface of the ceramic substrate 2°. and are connected by bond ink wires 9, respectively.
抵抗体２６１□、２６Ｆ２は、一般的に蒸着により形成
され、所望の抵抗値を得るために、エツチング及びレー
ザトリミングによりパターン配線クを施す。また、これ
ら抵抗体２６Ｆｌ、２６７２を形成する為に必要な領域
は、一般的に０，５〜１．ＯＢの幅が必要である。The resistors 261□ and 26F2 are generally formed by vapor deposition, and are patterned by etching and laser trimming to obtain a desired resistance value. Further, the area required to form these resistors 26Fl and 2672 is generally 0.5 to 1.5 mm. The width of the OB is required.
従来の半導体装置用パッケージにおいては、終端層抵抗
体２６Ｆｌ、２６．をボンディングワイヤ９でメタライ
ズ電源配線２３ａと半導体チップ８の電極８１とに接続
する構造となっているので、このボンディング工程は自
動化することが困難であり、半導体装置の価格が増大し
工期が遅延し易いという問題点があり、また、抵抗体２
６Ｆｌ。In a conventional semiconductor device package, termination layer resistors 26Fl, 26. Since the structure is such that the bonding wire 9 connects the metallized power supply wiring 23a and the electrode 81 of the semiconductor chip 8, it is difficult to automate this bonding process, which increases the price of the semiconductor device and delays the construction period. There is a problem that the resistor 2
6Fl.
２６．２をセラミック基板２２の平面上に形成する為、
この領域が必要となり、半導体装置用パッケージの大型
化もしくは搭載可能な半導体チッソの寸法の狭小化する
という問題点があった。26.2 on the plane of the ceramic substrate 22,
This area is required, and there is a problem in that the semiconductor device package becomes larger or the size of the semiconductor chip that can be mounted becomes narrower.
本発明の目的は、価格の低減及び工期の短縮なはかるこ
とができ、かつ大型化及び搭載可能な半導体チップの寸
法の狭小化を防止することができる半導体装置用パッケ
ージを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a package for a semiconductor device that can reduce costs and shorten the construction period, and can prevent an increase in size and a reduction in the size of a semiconductor chip that can be mounted.
本発明の半導体装置用パッケージは、中央部に半導体チ
ップを収納するための開口部が形成され底面に第１の電
源配線が形成され上面に前記半導体チップの電極と外部
回路接続用のリード端子とを接続するためのパターン配
線が形成された枠状の第１のセラミック基板と、この第
１のセラミック基板の開口部の側壁に形成され一端を前
記第１の電源配線と接続し他端を前記パターン配線と接
続する第１の抵抗体と、中央部に前記第１のセラミック
基板の開口部より広い開口部が形成され上面に第２の電
源配線が形成され前記第１のセラミック基板上に積層さ
れた棒状の第２のセラミック基板と、この第２のセラミ
ック基板の開口部の側壁に形成され一端を前記第２の電
源配線と接続し他端を前記パターン配線と接続する第２
の抵抗体とを有している。The package for a semiconductor device of the present invention has an opening for accommodating a semiconductor chip in the center, a first power supply wiring on the bottom, and lead terminals for connecting the electrodes of the semiconductor chip and an external circuit on the top. a frame-shaped first ceramic substrate on which a pattern wiring is formed for connecting the first ceramic substrate; A first resistor connected to the pattern wiring, an opening wider than the opening of the first ceramic substrate formed in the center, and a second power supply wiring formed on the upper surface, laminated on the first ceramic substrate. a rod-shaped second ceramic substrate, and a second ceramic substrate formed on the side wall of the opening of the second ceramic substrate and having one end connected to the second power supply wiring and the other end connected to the pattern wiring.
It has a resistor.
また、第１及び第２のセラミック基板の少なくとも一方
の開口部の側壁にこの側壁面より窪んだ凹部を形成し、
第１及び第２の抵抗体の少なくとも一方を、前記凹部に
設けられ一端をパターン配線と接続し他端を第１及び第
２の電源配線の何れか一方と接続する抵抗素子とした構
造を有している。Further, a recessed portion recessed from the side wall surface is formed on the side wall of the opening of at least one of the first and second ceramic substrates,
At least one of the first and second resistors has a structure in which a resistive element is provided in the recessed part and has one end connected to the pattern wiring and the other end connected to either the first or second power wiring. are doing.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を示す斜視図である。FIG. 1 is a perspective view showing a first embodiment of the present invention.
この実施例は、放熱板１と、この放熱板１上に接着固定
され、中央部に半導体チップ８を収納するための開口部
が形成され底面に第１の電源配線の接地配線（第１図で
は見えない）が形成され上面に半導体チップ８の電極８
１と外部回路接続用のリード端子３とを接続するための
メタライズパターン配線２１Ａが形成された枠状の第１
のセラミック基板２Ａと、この第１のセラミック基板２
Ａの開口部の側壁に形成され一端を接地配線と接続し他
端をメタライズパターン配線２１Ａと接続する第１の抵
抗体２２Ａと、中央部に第１のセラミック基板２Ａの開
口部より広い開口部が形成され上面に第２の電源配線の
メタライズ電源配線２３Ｂが形成され第１のセラミック
基板２Ａ上に積層された枠状の第２のセラミック基板２
Ｂと、この第２のセラミック基板２Ｂの開口部の側壁に
形成され一端をメタライズと電源配線２３ｍ１と接続し
他端をメタライズパターン配線２１Ａと接続する第２の
抵抗体２２Ｂと、メタライズパターン配線２１Ａと接続
するリード端子３とを有する構造となっている。This embodiment includes a heat dissipation plate 1, which is adhesively fixed onto the heat dissipation plate 1, has an opening in the center for accommodating the semiconductor chip 8, and has a ground wiring for the first power supply wiring (see FIG. 1) on the bottom surface. ) are formed on the upper surface of the semiconductor chip 8.
1 and a lead terminal 3 for connecting an external circuit.
ceramic substrate 2A, and this first ceramic substrate 2
A first resistor 22A formed on the side wall of the opening of A and having one end connected to the ground wiring and the other end connected to the metallized pattern wiring 21A, and an opening wider than the opening of the first ceramic substrate 2A in the center. A frame-shaped second ceramic substrate 2 is laminated on the first ceramic substrate 2A, on which a metallized power supply wiring 23B of a second power supply wiring is formed.
B, a second resistor 22B formed on the side wall of the opening of the second ceramic substrate 2B and having one end connected to the metallization and power supply wiring 23m1 and the other end connected to the metallization pattern wiring 21A, and the metallization pattern wiring 21A. It has a structure including a lead terminal 3 to be connected to.
そしてセラミック基板２Ａ、２Ｂの開口部の放熱板１上
に半導体チップ８が搭載され、この半導体チップ８の電
極８１をメタライズパターン配線２１Ａとがボンディン
グワイヤ９により接続される。A semiconductor chip 8 is mounted on the heat sink 1 in the openings of the ceramic substrates 2A, 2B, and the electrodes 81 of the semiconductor chip 8 are connected to the metallized pattern wiring 21A by bonding wires 9.
このような構造とすることにより、抵抗体２２Ａ。With such a structure, the resistor 22A.
２２Ｂとメタライズパターン配線２１Ａ、メタライズ電
源配線２３Ｉ］との間の接続をボンディングワイヤで行
う必要がなくなるので、価格の低減及び工期の短縮がで
き、また大型化するのを防止し半導体チップの寸法の狭
小化を防止することができる。22B, the metallized pattern wiring 21A, and the metallized power supply wiring 23I], it is no longer necessary to use bonding wires to make connections between the metallized pattern wiring 21A and the metallized power supply wiring 23I, thereby reducing costs and shortening the construction period. Narrowing can be prevented.
次に、この実施例の形成方法について説明する。Next, the formation method of this example will be explained.
第２図は、この実施例の第１のセラミック基板２、の形
成方法を説明するための中間工程のセラミック基板２Ａ
の平面図である。FIG. 2 shows a ceramic substrate 2A in an intermediate process for explaining the method of forming the first ceramic substrate 2 of this embodiment.
FIG.
セラミック基板２Ａは、まず、平板状の基板に対しタン
グステンなどの金属ペーストによりメタライズパターン
配線２１Ａを印刷する。次に、メタライズパターン配線
２１Ａの基板中央部側の先端部に貫通孔を設け、この貫
通孔に抵抗体ペースト２２Ａｘを充填する。次に、メタ
ライズパターン配線２１Ａの先端部分２貫通孔の中心部
分から開口し、（第２図中点線部分）半導体チップ搭載
用の開口部を形成する。これにより開口部側壁に抵抗体
ペース）２２ＡＸによる焼結前の抵抗体２２Ａが形成さ
れる。For the ceramic substrate 2A, first, a metallized pattern wiring 21A is printed on a flat substrate using a metal paste such as tungsten. Next, a through hole is provided at the tip of the metallized pattern wiring 21A on the substrate center side, and this through hole is filled with resistor paste 22Ax. Next, an opening is opened from the center of the through hole of the tip end portion 2 of the metallized pattern wiring 21A (dotted line in FIG. 2) to form an opening for mounting a semiconductor chip. As a result, a resistor 22A before sintering with the resistor paste 22AX is formed on the side wall of the opening.
同様にセラミック基板２ＩＩも、開口部側壁のメタライ
ズパターン配線２１Ａと接する箇所に、抵抗体ペースト
を印刷し、セラミック基板２Ａと積層する。Similarly, for the ceramic substrate 2II, a resistor paste is printed on the side wall of the opening at a location in contact with the metallized pattern wiring 21A, and the ceramic substrate 2II is laminated with the ceramic substrate 2A.
そして、セラミック基板２Ａの底面全面及びセラミック
基板２Ｂの上面全面をタングステンなどの金属ペースト
によりメタライズ接地配線、メタライズ電源配線２３Ｂ
を印刷する。この様な状態で、セラミックの焼結温度で
加熱すると金属ペースト、抵抗体ペーストはメタライズ
化される。Then, the entire bottom surface of the ceramic substrate 2A and the entire top surface of the ceramic substrate 2B are metalized with a metal paste such as tungsten, and the ground wiring and the metalized power supply wiring 23B are
print. In this state, when heated at the sintering temperature of ceramic, the metal paste and resistor paste are metalized.
これに、放熱板１．リード端子を金属ろう材により、ろ
う付けを施し、メタライズパターン配線２１Ａの金属材
料の種類により適宜Ｎｉめつき。In addition, heat sink 1. The lead terminals are brazed with a metal brazing material, and Ni-plated as appropriate depending on the type of metal material of the metallized pattern wiring 21A.
Ａｕめっき等を施すことにより半導体装置用パッケージ
は完成する。The semiconductor device package is completed by applying Au plating or the like.
第３図は本発明の第２の実施例を示す要部斜視図である
。FIG. 3 is a perspective view of essential parts showing a second embodiment of the present invention.
この実施例においては、セラミック基板２ｃ。In this embodiment, the ceramic substrate 2c.
２Ｄの開口部の側壁に凹部２４Ｃ，２４Ｄが形成され、
この凹部２４．．２４Ｄに抵抗体としての抵抗素子４Ａ
、４Ｂを固定し、これら抵抗素子４Ａ、４８の電極をメ
タライズパターン配線２１．等にろう付けする構造とな
っている。Recesses 24C and 24D are formed on the side wall of the opening of 2D,
This recess 24. ．． Resistance element 4A as a resistor in 24D
, 4B are fixed, and the electrodes of these resistance elements 4A, 48 are metalized pattern wiring 21. It has a structure that is brazed to etc.
抵抗素子４Ａ、４ｍの接続は、セラミック基板２Ｃ，２
Ｄの焼結後、リード端子３．放熱板１をセラミック基板
２゜、２．にろう付けする時に行なっても良いし、また
、半導体装置用パッケージ完成後、比較的低温の金属ろ
う材で接続しても良い。The connection of the resistance elements 4A and 4m is through the ceramic substrates 2C and 2.
After sintering D, lead terminal 3. The heat sink 1 is placed on the ceramic substrate 2°, 2. This may be done at the time of brazing, or the connection may be made using a relatively low-temperature metal brazing material after the semiconductor device package is completed.
この実施例においては、抵抗体（抵抗素子４Ａ。In this embodiment, a resistor (resistance element 4A) is used.
４Ｂ）を個別に製造することが可能である為、より正確
な抵抗値を得ることが可能であり、かつ取付は位置や抵
抗値の変更等が容易にできるという利点を有する。4B) can be manufactured individually, which has the advantage that it is possible to obtain a more accurate resistance value, and the mounting position and resistance value can be easily changed.
以上説明したように本発明は、抵抗体をセラミック基板
の開口部の側壁に形成する構造とすることにより、この
抵抗体の接続をボンディングワイヤで行う必要がなくな
るので、価格の低減と工期の短縮をはかることができ、
また従来、抵抗体のために設けられた平面が不要となる
ので、同一寸法の半導体チップを搭載する場合は従来よ
り小型化す、ることができ、半導体装置用パッケージの
寸法を同一とすると従来より大型の半導体チワワを搭載
することができる効果がある。As explained above, the present invention has a structure in which the resistor is formed on the side wall of the opening of the ceramic substrate, thereby eliminating the need to connect the resistor with a bonding wire, thereby reducing costs and shortening the construction period. can be measured,
Additionally, since the flat surface previously provided for the resistor is no longer required, it is possible to mount a semiconductor chip of the same dimensions on a smaller package than before, and if the dimensions of a semiconductor device package are the same, it is possible to make the package smaller than before. This has the effect of allowing a large semiconductor Chihuahua to be mounted on it.
第１図及び第２図はそれぞれ本発明の第１の実施例を示
す斜視図及びこの実施例のセラミック基板の形成方法を
説明するための平面図、第３図は本発明の第２の実施例
を示す要部斜視図、第４図は従来の半導体装置用パッケ
ージの一例の要部斜視図である。
１・・・・・・放熱板、２Ａ〜２ｏ・・・・・・セラミ
ック基板、３・・・・・・リード端子、４Ａ、 ４１・
・・・・・抵抗素子、８・・・・・・半導体チップ、９
・・・・・・ポンディングワイヤ、２１Ａ、２１．．２
１□・・・・・・メタライズパターン配線、２２Ａ、２
２！ｌ・・・・・・抵抗体、２２ＡＸ・・・・・・抵抗
体ペースト、２３１１．２３Ｄ、２３゜・・・・・・メ
タライズ電源配線、２４゜、２４Ｄ・・・・・・凹部、
２５ア・・・・・・メタライズ接地配線、２６Ｆｌ、
２６Ｆ２・・・・・・抵抗体、２７Ｆ＋、２７ア２，８
１・・・・・・電極。
代理人 弁理士 内 原 晋
第２図1 and 2 are respectively a perspective view showing a first embodiment of the present invention and a plan view for explaining the method of forming a ceramic substrate of this embodiment, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a perspective view of a main part of an example of a conventional semiconductor device package. 1... Heat sink, 2A~2o... Ceramic board, 3... Lead terminal, 4A, 41.
... Resistance element, 8 ... Semiconductor chip, 9
...... Bonding wire, 21A, 21. ．． 2
1□・・・Metallized pattern wiring, 22A, 2
2! l...Resistor, 22AX...Resistor paste, 2311.23D, 23°...Metallized power supply wiring, 24°, 24D...Recess,
25A...Metalized ground wiring, 26Fl,
26F2...Resistor, 27F+, 27A2,8
1... Electrode. Agent: Susumu Uchihara, patent attorney Figure 2
Claims (1)
成され底面に第１の電源配線が形成され上面に前記半導
体チップの電極と外部回路接続用のリード端子とを接続
するためのパターン配線が形成された枠状の第１のセラ
ミック基板と、この第１のセラミック基板の開口部の側
壁に形成され一端を前記第１の電源配線と接続し他端を
前記パターン配線と接続する第１の抵抗体と、中央部に
前記第１のセラミック基板の開口部より広い開口部が形
成され上面に第２の電源配線が形成され前記第１のセラ
ミック基板上に積層された枠状の第２のセラミック基板
と、この第２のセラミック基板の開口部の側壁に形成さ
れ一端を前記第２の電源配線と接続し他端を前記パター
ン配線と接続する第２の抵抗体とを有することを特徴と
する半導体装置用パッケージ。 ２、第１及び第２のセラミック基板の少なくとも一方の
開口部の側壁にこの側壁面より窪んだ凹部を形成し、第
１及び第２の抵抗体の少なくとも一方を、前記凹部に設
けられ一端をパターン配線と接続し他端を第１及び第２
の電源配線の何れか一方と接続する抵抗素子とした請求
項１記載の半導体装置用パッケージ。[Claims] 1. An opening for accommodating a semiconductor chip is formed in the center, a first power supply wiring is formed in the bottom, and electrodes of the semiconductor chip and lead terminals for connecting an external circuit are formed in the top. A frame-shaped first ceramic substrate on which pattern wiring for connection is formed; one end of the first ceramic substrate is formed on the side wall of the opening of the first ceramic substrate, and one end is connected to the first power wiring, and the other end is connected to the pattern wiring. A first resistor connected to the wiring, an opening wider than the opening of the first ceramic substrate formed in the center, a second power supply wiring formed on the upper surface, and laminated on the first ceramic substrate. a frame-shaped second ceramic substrate, and a second resistor formed on the side wall of the opening of the second ceramic substrate and having one end connected to the second power supply wiring and the other end connected to the pattern wiring. A package for a semiconductor device, comprising: 2. A recess is formed in the side wall of the opening of at least one of the first and second ceramic substrates, and the recess is recessed from the side wall surface, and at least one of the first and second resistors is provided in the recess and has one end. Connect the pattern wiring and connect the other end to the first and second
2. The package for a semiconductor device according to claim 1, further comprising a resistance element connected to one of the power supply wirings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2237424A JPH04116964A (en) | 1990-09-07 | 1990-09-07 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2237424A JPH04116964A (en) | 1990-09-07 | 1990-09-07 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04116964A true JPH04116964A (en) | 1992-04-17 |
Family
ID=17015153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2237424A Pending JPH04116964A (en) | 1990-09-07 | 1990-09-07 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04116964A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9589917B1 (en) * | 2016-03-21 | 2017-03-07 | Raytheon Company | Microwave monolithic integrated circuit (MMIC) having integrated high power thermal dissipating load |
-
1990
- 1990-09-07 JP JP2237424A patent/JPH04116964A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9589917B1 (en) * | 2016-03-21 | 2017-03-07 | Raytheon Company | Microwave monolithic integrated circuit (MMIC) having integrated high power thermal dissipating load |
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