JPH04111530A - 2-input logic circuit - Google Patents

Abstract

PURPOSE:To attain a high integration and a high speed by constituting a NAND circuit or a NOR circuit of only two MOSFETs. CONSTITUTION:A p-type MOSFET Q1 and an n-type MOSFET Q2 of surface channel type are provided, and respective gates are joined to form the pn junction, and the gate of one of them is connected to a first input terminal 10 through a first resistance R1, and the gate of the other is directly connected to a second input terminal 12. Drains of the p-type MOSFET Q1 and the n-type MOSFET Q2 are connected with a second resistance R2 between them, and either side of the second resistance R2 is connected to an output terminal 14. Consequently, two MOSFETs are operated as a ratioless inverter when only one of them is turned on, but a ratio type output is obtained by the operation resistance of MOSFETs and the second resistance R2 when both of MOSFETs are turned on. Thus, the number of transistors is reduced to obtain a high speed and a high integration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to MOSFETs formed by integrating circuits on the same substrate, particularly p-type MOSFETs and n-type MMOSFETs.
The present invention relates to a two-input logic circuit constituted by CMO3 made of OSFET.

[Conventional technology]

FIG. 6(a) is a circuit diagram of an example of a conventional two-input logic circuit. In this circuit, Q ++ and Q lx are p-type MO
S FET, Qll, Qll is n-type MOSFET
, the gates of QII and QIff are connected to each other, and the gates of Qll and Ql
The so-called CMOS (
This is a circuit called a complementary MOS (complementary MOS) type. A p-type MOSFET is on when the gate voltage is at a low level (hereinafter referred to as rLJ or "0") and is off when it is at a high level (hereinafter referred to as rHJ or "1"), and an n-type MOSFET is at this level. It's the opposite. Therefore, if input A is 1 and input B is 0, Q□ and Qll are on, but Qo and Qll are off, so the output Y is 1. Similarly, when A=O1B-1, Q1 and Q10 are on and Qll and Qll are off, so Y=1. Furthermore, when A=O1B-0, QII and Q1□ are on, and Ql
Since l and Q10 are off, it becomes Y-1, and A-B-1
When , Qll and Qll are off and Qll and Qll are on, so it becomes Y-0. Figure 6(b) summarizes these results, and it shows that the circuit in Figure 6(a) has N
It is understood that it operates as an AND circuit.

FIGS. 7(a) and 7(b) are cross-sectional views of n-type and p-type MOSFETs forming CMO3, respectively.

When configuring CMO3, p-type MOSFET and n-type MOSFET
Considering that the gates of SFETs are connected to each other, normally both gate electrodes are formed of the same n'' type polysilicon.In this case, in the case of the n-channel type shown in Figure (a), the gate electrodes are formed near the surface of the p-type substrate. In contrast, the p-channel type shown in FIG. 3B is a buried channel type in which a channel is formed inside the n-type substrate due to work function and other factors.

(Problems to be Solved by the Invention) A conventional two-input logic circuit requires at least four transistors as shown in Figure 6.For this reason, when forming one two-input logic circuit on a silicon chip, M.O.
This requires an area equivalent to four SFETs, which is an obstacle to improving the degree of integration by increasing the number of basic circuits (NAND circuits, NOR circuits, etc.) that can be formed per unit area.

In addition, in the conventional CMO3, as shown in FIG.
The SFET is a buried channel.

Therefore, it is vulnerable to short channel effects, and bunch-through may occur. In order to cope with this short channel effect, it is conceivable to make the gate electrode of the p-type MOSFET shown in FIG. 7(b) a p-type and make the p-type MOSFET a surface channel type.

However, in this case, if the gates are connected as is, a pn junction will occur between both gates, making it impossible to obtain the desired operation. Therefore, the gates of the n-type MOSFET and p-type MOSFET are shorted together using metal wiring. This not only increases the number of work steps, but also causes problems such as extremely low efficiency and increased costs.

The present invention has been made based on the above circumstances, and aims to achieve high speed and high integration by reducing the number of transistors required for the configuration of a logic circuit, is resistant to short channel effects, and requires fewer work steps. The object is to provide a two-input logic circuit that can be formed.

[Means to solve the problem]

A two-input logic circuit according to the present invention for achieving the above object includes a surface channel type p-type MOSFET and an n-type MOSFET, and connects the gates of the p-type MOSFET and n-type MOSFET to each other. to form a p-n junction, one of the gates is connected to the first input terminal via the first resistor, and the other gate is directly connected to the second input terminal, and the p-type MOS FET and n-type MO
This device is characterized in that the drains of the SFETs are connected to each other via a second resistor, and either side of the second resistor is connected to an output terminal.

[Effect]

According to the above-described structure, when zero bias or forward bias is applied between the anode and cathode of the pn junction diode formed by the gates of the p-type MOSFET and the n-type MOSFET, the p-type MOSFET
A voltage of the same level (both Hl or both L) is applied to the gates of the S FET and the n-type MOSFET, and one of the two MOSFETs is turned on and the other is turned off. Therefore, the two MOS FETs operate as a ratioless inverter. Furthermore, when a reverse bias is applied to the diode, the p-type MOSFET, n
Both type MOSFETs are turned on and these MOS
A ratio type output is produced by the operating resistance of the FET and the second resistance.

Also, in the above circuit, the required MOSFET is reduced to two, and the pn junction between these gates is simply the n9 type gate electrode of the n type MOSFET and the p type MOSFET.
Since it is obtained by directly bonding the p-type electrode of ET, no additional area on the silicon chip is required. Therefore, the area required on the silicon chip is greatly reduced, and the speed is increased. Extremely advantageous for processing.

Furthermore, by forming both the n-type MOSFET and the Sp-type MOSFET as a surface channel type, a circuit element that is resistant to short channel effects can be obtained, and the degree of integration and speed can be improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a two-input logic circuit according to a first embodiment of the present invention, and this circuit is composed of p-type MOS F E
It consists of Ql, which is a T, and Q2, which is an n-type MOSFET. This circuit operates as a NAND circuit as described later.

In the circuit of FIG. 1, Q1Q drain and Q.

is connected to the drain of Ql through a resistor R2.
The source of Q2 is connected to the power supply V□, and the source of Q2 is connected to ground. The Q side of the resistor R2 is connected to the output terminal 14. Also, the gate of Q is resistor R
1 to the input terminal 10, and the gate of Q is directly connected to the input terminal 12. The resistance R0 can be obtained, for example, by preventing ions from being implanted when forming a gate electrode by implanting ions into a polysilicon layer, and by doing so, it is possible to obtain a resistance element with a very high value. I can do it. Furthermore, these gates are connected by a pn junction diode D. The formation of this diode D will be described later.

In FIG. 1, an input terminal 10 is supplied with a signal A=0, and an input terminal 12 is supplied with a signal B=O. At this time, the anode and cathode of diode D are at the same potential and are therefore at zero bias. Therefore, no current flows through the diode D, and the gates of Ql and Q2 are both turned off. Therefore Q
l is on, but Qo is off, and the signal Y appearing at the output terminal 14 becomes Hl, that is, 1. In this case Q,,Q
The circuit consisting of , and resistor R2 operates as a ratioless inverter. Assuming that A=B=1, the diode D is also at zero bias in this case, so no current flows. At this time, the gate of Q, , all gates are H
Therefore, Q2 is on, but Ql is off. Therefore, the output Y becomes 0, that is, 0. In this case as well, Q,
, Q, , the circuit consisting of resistor R2 operates as a ratioless inverter.

Next, let A=0 and B=1. In this case, diode D becomes reverse biased and no current flows through diode D. At this time, both Ql and Qz are turned on, and the current supplied from the power source V flows according to their respective conductances g. , Therefore, in this case, the circuit consisting of Q, , Q, , and resistor R2 operates in a ratio type operation. Here Q
Since the resistor R2 is made sufficiently large compared to the operating resistances of 1 and Qt, the output Y is pulled up by the resistor R1 and becomes H1, that is, 1.

Furthermore, it is assumed that A-1 and B=O. In this case, the diode D becomes forward biased, so the gate of Ql and the gate of Q8 are short-circuited. And as mentioned above, the resistance R
1 has a sufficiently large resistance value, both gates are pulled down by the resistor R1 and become L. Therefore, Q is turned on, but Q is turned off, and the output Y becomes 1.

In this case as well, ratioless operation is performed.

FIG. 2 is an operation table of the circuit shown in FIG. 1 summarizing the results obtained so far. It is understood from this that the circuit of FIG. 1 operates as a NAND circuit.

Moreover, the number of MOS FETs used is 2, and 4
Compared to a conventional NAND circuit, which requires 100 MOS FETs, only half of the MOS FETs are required. Therefore, when a large number of NAND circuits according to this embodiment are integrated on the same silicon substrate, the area required is smaller than that of a conventional NAND circuit. This makes it possible to significantly increase density, integration, and speed, and since no special process is required to connect gates, manufacturing time and costs can be significantly reduced. can be reduced to

Figures 3(a) and (b) show the p-type MOSFE of the circuit in Figure 1.
It is a cross-sectional view of T and n-type MOSFET, and FIG. 7(a),
This corresponds to (b). The difference from the case in FIG. 7 is that in this example, as shown in FIG. 7(b), the p-type MOS
The point is that the gate electrode of the FET is p-type. Therefore, the p-type MOSFET becomes a surface channel type, and a p-type MOSFET element that is resistant to short channel effects can be obtained, thereby achieving high integration and high speed. Conventionally, in order to obtain a device that is resistant to short channel effects, the gate of an n-type MO5FET was changed to an n-type MO5FET or a p-type MO5FET.
When the gates of the 5FETs are p-type, it is necessary to short-circuit both gates with metal wiring so that a pn junction does not occur between these gates when connecting them. However, in this embodiment, by actively utilizing this pn junction and forming the diode D, the above problems can be solved at once.

FIG. 4 is a circuit diagram of a two-input logic circuit according to a second embodiment of the present invention, and is the same as FIG. 1! The same reference numerals are given to the bottom portion, and the explanation thereof will be omitted. This circuit differs from the circuit shown in FIG. 1 in that a resistor R1 is provided on the gate side of Q8, and an output terminal 14 is provided on the Q side of resistor Rt. However, this resistance R8
The method of forming is similar to the method of forming the resistor R5 described above.

In FIG. 4, when the input signal is A=B=1, since the diode D is at zero bias, the gates of Q, Q2, Q2 are all at H, Ql is off, and Q2 is on. Therefore, the output Y becomes O. A=B=
In the case of O, the diode D is also at zero bias, so Q,
The gates of ,Q, are all positive, Ql is on, and Q
2 is off.

Therefore, the output Y becomes Hl, that is, 1.

Furthermore, A=0. When B=1, the diode D becomes reverse biased, and the gate of Q becomes H. From this, Q, , Q, are both turned on, and Q, ,
Q, , and resistor R2 operate in a ratio type manner. And the output Y is pulled down by resistor R2, that is, 0
becomes. When A=1 and B=0, the diode D becomes forward biased, so the gates of Ql and Q□ are shorted together, and the gates of Q and Q2 are pulled up by the resistor R1 and become H. becomes. Therefore, Ql is turned off, Q8 is turned on, and the output Y becomes 0, that is, 0.

The results are summarized as shown in FIG. 5, from which it can be understood that the circuit in FIG. 4 operates as a NOR circuit. This circuit also has two MOSFEs, similar to the circuit in Figure 1.
It can be configured by T. Note that other functions and effects are similar to those of the first embodiment.

〔Effect of the invention〕

As explained above, according to the present invention, two MOSFE
Since a NAND circuit or a NOR circuit can be constructed using T alone, the number of elements required to construct these circuits can be reduced to half of the conventional number, making it possible to form these circuits on a silicon chip. The area required to do this is also reduced to about half, making it possible to provide a two-input logic circuit that can achieve significantly higher density, higher integration, and higher speed than conventional logic circuits.

Further, according to the present invention, by making the gate electrode of the p-type MOSFET p''' type, both of the two MOSFETs can be made into surface channel type, so it is possible to make the MOSFET resistant to short channel effects. Therefore, high integration and high speed can be achieved, and two MO
Since the gates of SFET are used as pn junctions, there is no need for metal wiring to short-circuit these gates, making it possible to provide a two-input logic circuit that can reduce manufacturing time and manufacturing costs. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a two-input NAND circuit according to the first embodiment of the present invention, FIG. 2 is an operation table showing the relationship between the input and output of the circuit of FIG. 1, and FIG. n constituting the circuit in Figure 1
A cross-sectional view of type MOS FET, the same figure (b) is p-type MOS
A cross-sectional view of the FET, FIG. 4 is a circuit diagram of a two-input NOR circuit according to the second embodiment of the present invention, FIG. 5 is an operation table showing the relationship between the input and output of the circuit in FIG. 4, and FIG. (a) is a circuit diagram of a conventional 2-input NAND circuit, (b) is an operation table showing the relationship between the input and output of the circuit in (a), and Fig. 7 (a) is a conventional n-type NAND circuit. A cross-sectional view of a MOS FET, and FIG. 3(b) is a cross-sectional view of a conventional p-type MOS FET. 10.12...Input terminal, 14...Output terminal, Ql
, Qz...I) type MOS FET. Qz, Q4--n-type MOS FET. D... Diode, Rz. R3 resistance, VDD... power supply.

Claims (1)

[Claims] Surface channel type p-type MOSFET and n-type MOS
A FET is provided, and the p-type MOSFET and the n-type MOSFET
The gates of T are connected to each other to form a pn junction, one of the gates is connected to the first input terminal via the first resistor, and the other gate is connected directly to the second input terminal, A two-input logic circuit characterized in that the drains of the p-type MOSFET and the n-type MOSFET are connected to each other via a second resistor, and either side of the second resistor is connected to an output terminal.