JPH04109302A - Arithmetic processing system - Google Patents

Abstract

PURPOSE:To easily analyze abnormality by mutually comparing processed result between two arithmetic processors, and at the time of detecting abnormality in a compared result, executing arithmetic processing again and storing the contents of the abnormality. CONSTITUTION:After completing respective operations, two CPUs A, B mutually compare their respective arithmetic results with their opposite results by inter- CPU communication, and when there is no abnormality, respectively store important data indicating their arithmetic processes in the areas 15, 16 of a common RAM 5. Namely, two areas are prepared for each of the CPUs 1 to 4 and trace data and a marker indicating up-to-date data are alternately stored in respective areas. If discrepancy or asynchronism is generated between arithmetic results to be compared, the data are stored and then writing in the tracing data storing areas 15, 16 is aborted. When a person to be a user judges the generation of the abnormality, these areas 15, 16 are dumped by memory dump and a process generating the abnormality is analyzed. Then trace data storage is restarted again.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention relates to arithmetic processing used as a control device for a flying object that requires high reliability and is difficult to maintain, such as in outer space. Regarding the system.

(Conventional technology) In general, arithmetic processing systems installed on artificial satellites, etc.
Because high reliability is required, for example, arithmetic processing units (hereinafter referred to as CPUs) are made redundant and operated in parallel.
Measures are taken to prepare for when abnormalities such as failures occur. However, in conventional systems, when an abnormality occurs and the CPU is switched or arithmetic processing is restarted, the control is performed continuously, so it is difficult for the human user to switch the CPU. It's hard to tell if something has happened that caused the problem.

In particular, this abnormality content is essential when determining whether to manually prohibit the use of the CPU.

For this reason, it has been desired to make it possible to later identify the details of the abnormality when the CPU is switched or arithmetic processing is restarted due to the occurrence of an abnormality.

(Problem to be solved by the invention) As mentioned above, in the conventional arithmetic processing system, the CPU
The systems are made redundant and run in parallel, and if an error occurs, the CPU is switched or the calculation process is redone.
Since the control is continuous, it is difficult for the human user to understand the cause of the abnormality.

This invention was made to solve the above-mentioned problems, and when an abnormality occurs and the CPU is switched or arithmetic processing is redone, the contents of the abnormality can be made identifiable later. The purpose of this study is to provide an arithmetic processing system that makes it extremely easy to analyze the causes of problems.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes a plurality of arithmetic processing units, mutually compares processing results between the two arithmetic processing units, The arithmetic processing system switches to another arithmetic processing device and executes arithmetic processing again when an abnormality is detected based on a comparison result, and is configured to include an abnormality content storage means for storing the abnormality content at the time of the abnormality detection. Further, the arithmetic processing system further includes an abnormality content sending means for reading out and sending out the abnormality content stored in the abnormality content storage means in response to an external command.

(Function) In the arithmetic processing system with the above configuration, the contents of the abnormality can be stored at any time when an abnormality is detected, so that the contents of the abnormality can be easily identified later. It will also be possible to read it out.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 3 shows the hardware configuration, and 1 to 4 are CPUs. These CPUI~4 are pass line BU
The RAM 5 and the configuration board 6 for switching the CPUs are connected to each other through the RAM 5 and the configuration board 6, which are used in common.

In the above configuration, the following operational procedures are followed for boat fishing.

First, out of CPUI ~ 4, usually 2 CPUI, 2
are operated and execute arithmetic processing while checking each other via the common RAM 5. The two CPUs, 2, communicate periodically to check whether the other CPU responds or whether the calculation results match. If it is abnormal, the calculation is first redone, and then it is determined whether there is an abnormality again. In this case, for example, the third CPU 3 is activated to perform a majority vote. Further, if there is an abnormality in the CPU itself, for example, the fourth CPU 4 is started up and used instead.

Further, the arithmetic processing system having the above configuration has functions as shown in FIG. That is, FIG. 1 diagrammatically represents the outline of the trace data saving process at the time of normal termination of a CPU cycle according to the present invention, and 11.12 in the figure represents each CPU cycle.
Various data necessary for calculations in the local RAM of U (L/LAM in the figure), 13.14, the data is transferred to the common RAM, M
(C/LAM in the figure) Area when saving to 5, 1.5,
1.6 indicates an area for trace data.

Two CPUs (One is a mask and the other is a shadow) When the calculations of A and B are completed (task ends),
The results are compared with those of the other party through inter-CPU communication, and if there is no abnormality, important data indicating the progress of the calculation is stored as trace data in areas 15 and 16 of the common RAM 5.

The storage format at that time is shown in Figure 2. That is, the CPUI
Prepare two areas for each of the areas 4 to 4, and save trace data alternately with a marker indicating the latest data.

If there is a discrepancy in the comparison results or if the synchronization is lost, the data at that time is saved, and from then on, writing to the trace data storage areas 15 and 16 in FIG. 2 is stopped.

If the human user determines that an abnormality has occurred in telemetry, commands, etc., he or she can dump this area using a memory dump and perform calculations (
or before the calculation). After the dump for abnormality analysis is completed, the trace data storage is restarted by canceling the prohibition of updating the trace data in preparation for the next abnormality.

Therefore, in the arithmetic processing system with the above configuration, whereas until now it was only a matter of trying to analyze the cause when an abnormality occurred,
For example, if the result of a certain subroutine in the CPU is an unusual value, it can be assumed that there was a temporary abnormality in the CPU, thereby making the analysis easier.

Note that the above trace data includes the results of inter-CPU communication (
There is data indicating whether there was a data mismatch or no response), so even if this data is stored as trace data in the common RA, M5 only when an abnormality occurs, the function of this invention will not be fulfilled. Of course.

[Effects of the Invention] As described above, according to the present invention, when an abnormality occurs and the CPU is switched or arithmetic processing is redone, the content of the abnormality can be made identifiable later. It is possible to provide an arithmetic processing system in which cause analysis is extremely easy.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram illustrating an outline of trace data storage processing when a CPU cycle normally ends, as an embodiment of the arithmetic processing system according to the present invention, and FIG. 2 is a schematic diagram showing the trace data storage process of the same embodiment. FIG. 3, which is a diagram for explaining the regions, is a block circuit diagram showing the hardware configuration of the same embodiment. 1 to 4...CPU, BUS...pass line, 5...
・Common RAM, 6...Configuration port, ]1. 2...CPU local RAM white data, 13.14...Data storage area in common RAM, ]5
゜16...Storage area for toshi trace data in common RAM Patent attorney Takehiko Suzue Figure 1 Figure 3 Figure 2

Claims (2)

[Claims] (1) Equipped with multiple arithmetic processing units, two arithmetic processing units compare processing results with each other, and when an abnormality is detected based on the comparison results, switch to another arithmetic processing unit and execute the arithmetic processing again. An arithmetic processing system comprising: an abnormality content storage means for storing abnormality content upon detection of the abnormality. (2) The arithmetic processing system further comprises abnormality content sending means for reading out and sending out the abnormality content stored in the abnormality content storage means in response to an external command. Arithmetic processing system.