JPS62134729A - Distribution type processor system - Google Patents

Abstract

PURPOSE:To detect immediately an erroneous bit of a data by executing a parity check of an internal data and a bus data, starting a microprogram if there is an error in the bus data, and executing an exclusive OR operation of a data of a DI register and a data of the first RF. CONSTITUTION:When an internal data which is stored in the first RF 18 is sent out to a data bus 1 through a DRV 22 from a processor 10 of the sending- out side, a processor 30 of the receiving side synchronizes with it and inputs the data on the data bus 1, to its own DI register 11, and the data is transferred from the processor 10 to the processor 30. In the processor 10 of the sending-out side, as soon as the internal data is sent out, the same data as that which is sent out to the data bus 1 is brought to a parity check by an internal data PC 13, and its result is held in the internal data PC. Also, the data on the data bus 1 is inputted to the DI register 11 of the processor 10, and also this data is brought to a parity check by a bus data PC 12, and its result is held by the bus data PC 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a 11-type processor system, and more particularly to a 1-11!-type processor system consisting of a plurality of processors connected by a bus and operating on a daily basis.

[Conventional technology]

In recent years, distributed processor systems having a bus configuration in which many processors are connected to a data bus and exchange data have come into widespread use.

In such a distributed processor system, even if there is no error in the data of the sending processor, bus failure or Nostem abnormality may cause bus contention, which disrupts the bus and causes parity errors in the bus data. Sometimes.

Such phenomena cause serious problems for Sostem.
In conventional processor systems, one method is generally used in which parity is added to the data in order to maintain the Kiff characteristics of data on the bus, and parity checking is performed when the data is taken in. There is.

However, in conventional distributed processor systems, if the original data to be sent is correct but an error occurs on the bus, it is possible to quickly detect this and determine which bits are corrupted. There was no means to detect whether it was a bit or not.

[Problem that the invention seeks to solve]

The conventional distributed processor system described above does not have a means to detect error bits in bus data.
The disadvantage is that it takes time to analyze and recover from the failure when an error occurs.

It is an object of the present invention to eliminate error bits in the in-flight when a corruption IJ occurs in the data sent to the bus by adding a small amount of hardware by using the configuration in the processor that is usually present in a distributed processor system. The purpose is to provide a molding processor stem.

[Means for Solving the Problems] A distributed processor system of the present invention is a distributed processor system in which a plurality of processors connected to a bus operate synchronously under a microprogram control system, in which each processor performs an operation. means, a first register file that stores output data of the arithmetic means as internal data and whose output is connected to one input of the arithmetic means, and a second register file that stores output data of the arithmetic means. , ij 1 stored in the first register file
A bus drive means for sending out 1:1 orientation unit data to the bus, an input data register for taking in the data on the bus-L, and an output of the second register file, or 4:
switching means for selectively connecting the output of the 1 input data register to the other input of the arithmetic means; and a bus data parity check for checking the parity of the data taken into the 1iif input data register and holding the result. means, internal data parity checking means for checking the parity of the internal data and holding the result when sending the internal data to the 11:l bus, and the bus data parity checking means. an error detection signal generating means for generating an error detection signal when the checked result differs from the result checked by the internal data parity checking means; When the switching means is switched so that the output data of the input data register is input to the other input of the calculation means, the fJl of the output data of the first register file and the output data of the input data register is different. It has a program control stage [1; Microphone 1:] which controls the calculation means 1 to calculate the logical sum by /3ii.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

The figure is a configuration diagram showing an embodiment of the present invention. 11 of this embodiment (Processor sonor system) consists of a plurality of processors connected in parallel to a data bus L.
, 50, . . . , and each processor operates under a microphone 1 program 11 control system.

The processor 10 includes an input data register (hereinafter abbreviated as DI register) 11 connected to the data bus 1;
A bus data parity check means (hereinafter referred to as
(abbreviated as PC)+2, and internal data P that performs a parity check on internal data in synchronization with the processor 10 sending internal data to the data bus 1 and holds the result.
Cl3, an inverter 14 that inverts the output of the internal data PCl3, and an AND gate 15 that receives the output of the bus data PC12 and the output of the inverter 14 as inputs, and the error detection signal is output from the error detection signal generating circuit. A microprogram control unit (hereinafter abbreviated as MPC) 16 which inputs an error detection signal to switch the control 1ffll, an arithmetic unit (hereinafter abbreviated as A L tJ) +7 controlled by the MPC 16, and ALU1.
A first register file (hereinafter abbreviated as RF) whose input is the output of ALU+7 and whose output is connected to one input of ALtJ17; a second RF19 whose input is the output of ALU+7; output and DI register 11
A multiplexer (hereinafter referred to as MT'X
The bus driver (hereinafter abbreviated as DRV) 22 outputs the data of the first RFI 8 to the data bus 1.

In addition, each processor +0.30.40.50. . . . have the same configuration, so the detailed internal configuration will be explained only for the processor 10, and the other processors 30, 40, 50, . . . will be omitted.

Next, the operation of the distributed processor system of this embodiment configured as shown below will be explained.

First, a case in which data is transferred from the processor 10 to the processor 30 will be described. Sending side processor 10
The internal data stored in the first RFIII from I)R
When the data is sent to the data bus 1 via V22, the processor 30 on the receiving side receives the data on the data bus 1 into its own DI register 11, and transfers the data from the processor 10 via the data bus 1. Data is transferred to processor 30.

At the sending processor 10, at the same time as the internal data is sent, the same data sent to the data bus 1 is parity-checked using the internal data PCl3, and the result is held in the internal data PCl3. Further, the data on the data bus 1 is taken into the DI register 11 of the processor 10, and this data is transferred to the bus data PcI2.
The result is held in the bus data PcI2.

If the data bus 1 is normal, the DI register 11 of the processor 10 contains the first RF signal sent via the DRV 22.
As a result of the parity check on bus data PC12 and internal data PCl3, the outputs of bus data PC12 and internal data PCl3 each become low level. Therefore, the output of the AND gate 15 becomes low level, and the MPC
Is 16 the normal system? Perform ff1l.

Next, when transferring data from Proceno 4J° 40 to Promono 4/30, from Proceno 4J° 40 to Promono 4/30,
A case will be described in which a data transfer to 0 is performed, which causes bus contention and disrupts the bus. In the processor 10 on the sending side, the data of the first RF 18 is sent out to the data bus 1 via the DRV 22 under the micro block diagram control, and is also input to the internal data PCl 3 to perform parity check. is held in internal data PCl3. Since the data of the first RF 18 is normal data, the output of the internal data PCl3 becomes a low level indicating that there is no parity error.

Further, the data sent to the data bus l is taken into the DI register 11, and the bus data Pc12 changes the parity of this data to 1,000? −'7 and retain the result.

Here, due to a system malfunction, the data transfer from the processor 40 to the processor 4) 50 is performed in the same amount as the data transfer from the processor IO to the processor 30, resulting in bus contention and the data bus 1-1= Suppose that the data of is corrupted. Then, the corrupted data (wrong data) is stored in the DI register 11, and the bus data PC+2 detects a parity error in the data on the data bus I, holds the result, and outputs the data with a parity error. It is assumed to be high level without indicating.

The output of the internal data PCI3 is inverted by the inverter 14 and input to the seventh game 5, and the output is ANDed with the output of the bus data PCI2 and output. Bus data PC12
Since the output of the AND gate 15 is at a high level and the output of the internal data PCl3 is at a low level, the output of the AND gate 15 is at a high level. Therefore, MPCl(i instructs the MPX 21 to output iK data from the DI register 11, and performs a two-input lIt, llh logical OR operation on A1., tJIT ( 1. This causes the ALU 17 to set the first I'1FIF
Exclusive OR operation is performed between the correct data from DI register 11 and the incorrect data from DI register 11, and the result (a word different from the original word) is stored in first RF 18. Therefore, the first RF 18 receives a signal that matches the original output data.

! “0” for -, “1” for mismatched bits
' data is stored. Therefore, by selling this data every eight times, it is possible to immediately determine which node on the back of the data has become corrupted and turned into an error bit on the data bus 1.

Note that the bus data PC and internal data PC in the above embodiment are those that are normally used for checking output data and input data in a processor that uses a method of checking by adding parity.

Further, the DI renostar is normally used as a register for receiving data in a pro renostar having a bus configuration.

In addition, the receiver may perform I) the received data or transfer it to other registers within the processor.
[It is also a configuration commonly used in JIII that allows register data to be input to AI and U.

〔Effect of the invention〕

As explained above, the present invention performs a parity check between internal data and bus data, and if there is an error in the bus data, activates a microprogram to check the parity between the DI register data and the first RF data. logical sum 6ii
'ST row has the effect that erroneous bits of data can be detected immediately.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. In the figure, l...data bus, 10, 30.40.50, p1cosenona, 11...
・Input data register, 12... bus data parity-y-nick means,
13... Internal data parity check means, 14
... Inverter, 15 ... AND gate, 16 ... Microphone J program system tfff 1 part,
17... Performance 1 gamma device, Ill, +9... Register Ill, 21...
...Multiplexer, 22...It's a bust.

Claims (1)

[Claims] In a distributed processor system in which a plurality of bus-connected processors operate synchronously under a microprogram control method, each processor has: a calculation means; and output data of the calculation means as internal data. a first register file that stores output data and is connected to one input of the arithmetic means; a second register file that stores output data of the arithmetic means; and the internal register file that is stored in the first register file. bus drive means for sending data to a bus; an input data register for taking in data on the bus; and selectively inputting the output of the second register file or the input data register to the other input of the calculation means. a bus data parity check means for checking the parity of the data taken into the input data register and holding the result; and a bus data parity check means for checking the parity of the internal data when sending the internal data to the bus. internal data parity check means for checking and holding the result; and error detection signal generation for generating an error detection signal when the result checked by the bus data parity check means differs from the result checked by the internal data parity check means. means for switching the switching means to input the output data of the input data register to the other input of the calculation means when the error detection signal is input from the error detection signal generation means, and the first register file; and microprogram control means for controlling the calculation means to calculate an exclusive OR of the output data of the input data register and the output data of the input data register.