JP3028836B2 - Arithmetic processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention is, for example, an arithmetic processing which is required as a control device for a flying object which is required to have high reliability and is not easy to maintain such as space. About the system.

(Prior art) Generally, an arithmetic processing system mounted on an artificial satellite or the like requires high reliability. For example, a method of preparing for the occurrence of an abnormality, such as, for example, is adopted. However, in the conventional system, when an abnormality occurs and the CPU is switched or the arithmetic processing is performed again,
Since the control is performed continuously, it is difficult for the user, who is the user, to know only that the CPU has been switched, but it is difficult to understand what caused the abnormality. In particular, the content of this abnormality is indispensable when judging whether to use the CPU manually or not. For this reason, it has conventionally been desired to be able to identify the contents of the abnormality later when the CPU is switched or the arithmetic processing is redone due to the occurrence of the abnormality.

(Problems to be Solved by the Invention) As described above, in the conventional arithmetic processing system, the CPU
Are made redundant and run in parallel, and if an error occurs, the CPU is switched or the arithmetic processing is redone, etc. Is difficult to understand.

The present invention has been made to solve the above problems, and when the CPU is switched or the arithmetic processing is redone due to the occurrence of an abnormality, the details of the abnormality can be identified later, and the abnormality can be identified. An object of the present invention is to provide an arithmetic processing system in which cause analysis is extremely easy.

[Constitution of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes a plurality of arithmetic processing units, and two of these arithmetic processing units use the same arithmetic processing unit. And periodically compare the computation results with each other, and when an abnormality is detected based on the comparison result, switch to another computation processing device and execute the computation process again. Trace data storage means for taking out trace data indicating the progress of calculation from each processing unit at the time of comparison of calculation results and writing the data in a memory common to each processing unit, and when an abnormality is detected by comparing the calculation results, Control means for prohibiting writing to the area so that the trace data of each processing unit written in the trace data storage means is not overwritten. Constructed.

Further, the apparatus further comprises trace data sending means for reading and sending the trace data written in the memory from the trace data storing means in response to an external command, and the trace data is sent from the trace data storing means by this means. In such a case, the control means is configured to release the write prohibition when an abnormality is detected.

(Operation) In the arithmetic processing system having the above configuration, the arithmetic results of two arithmetic processing units that perform the same arithmetic operation are periodically compared, and at the time of the comparison, each trace data is cyclically written to the memory. Since the overwriting of the trace data of each processing unit is prohibited when an error is detected, the trace data at the time of occurrence of an error always remains in the memory even if the configuration is used to write the data cyclically to the memory. By analyzing the contents of the memory of the trace data storage means, it is possible to easily identify abnormal contents.

Furthermore, by giving a command command from the outside,
Since the contents of the memory can be transmitted from the trace data storage means, it is possible to easily acquire the contents of the memory from a remote place and to analyze the contents of the abnormality. At this time, since the memory write prohibition is released after sending the memory contents, the abnormality monitoring function based on the trace data can be returned again.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. 1 and FIG.

FIG. 3 shows the hardware configuration.
Is the CPU. These CPUs 1 to 4 are mutually accessible via a bus line BUS, and are connected to a commonly used RAM 5 and a configuration port 6 for switching the CPU.

In the above configuration, the following operation procedure is generally followed. First, of the CPUs 1 to 4, usually two CPUs 1 and 2 are operated, and execute arithmetic processing while checking each other via the common RAM 5. The two CPUs 1 and 2 periodically communicate with each other to check whether the partner CPU responds or the calculation results match. If an error is found, the calculation is re-executed first, and then the error is found again. If, for example, the third
Start CPU3 and make a majority decision. If there is an abnormality in the CPU itself, for example, the fourth CPU 4 is started up and used instead.

Further, the arithmetic processing system having the above configuration has a function as shown in FIG. That is, FIG. 1 schematically shows the outline of trace data saving processing at the time of a normal end of a CPU cycle according to the present invention. In the figure, reference numerals 11 and 12 represent local RAMs (L / LAM in the figure) of each CPU. Various data required for calculation, 1
Reference numerals 3 and 14 denote areas for storing the data in the common RAM (C / LAM in the figure) 5, and reference numerals 15 and 16 denote areas for trace data.

Two CPUs (one as master and the other as shadow)
When the operation is completed (task end), A and B compare the result of the other with the result of communication between CPUs. If there is no abnormality, the important data indicating the progress of the operation is stored as trace data in areas 15 and 16 of the common RAM 5 save. FIG. 2 shows the storage format at that time. That is, two areas of each of the CPUs 1 to 4 are prepared, and trace data is alternately stored with a marker indicating the latest data. If the results of the comparison do not match or the synchronization is lost, the data at that time is stored, and thereafter, the trace data storage area 1 shown in FIG.
Stop writing to 5,16.

Here, if the human being determines that an abnormality has occurred due to telemetry, a command command, or the like, this area is dumped by a memory dump, and what happens during (or before) the computation at the time of the abnormality Is analyzed. After the dump for abnormality analysis is completed, the update of the trace data is prohibited from being prohibited in preparation for the next abnormality, so that the trace data storage is resumed.

Therefore, in the arithmetic processing system having the above configuration, while the cause analysis at the time of occurrence of an abnormality has been groping in the past, for example, a subroutine result of the CPU 1 has an unusual value. The analysis can be made easier, for example, it can be estimated that there is an abnormality.

Since the trace data includes data indicating the result of the inter-CPU communication (whether the data did not match or there was no response), only this data is used as trace data and stored in the common RAM 5 only when an error occurs. Even if it is stored, the function of the present invention is of course performed.

[Effects of the Invention] As described above, according to the present invention, when the CPU is switched or the arithmetic processing is redone due to the occurrence of an abnormality, the details of the abnormality can be made identifiable later. An arithmetic processing system in which cause analysis is extremely easy can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram schematically showing an outline of a trace data saving process at the time of a normal end of a CPU cycle as an embodiment of an arithmetic processing system according to the present invention, and FIG. 2 is a trace data saving process of the embodiment. FIG. 3 is a diagram for explaining an area.
FIG. 2 is a block circuit diagram showing a hardware configuration of the embodiment. 1-4 CPU, BUS bus line, 5 common RAM,
6: Configuration port, 11, 12, CPU
Data in the local RAM, 13, 14 ... Data storage area in the common RAM, 15, 16 ... Storage area for trace data in the common RAM.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G05B 9/03 G05B 9/02

Claims (2)

(57) [Claims] 1. A system comprising a plurality of arithmetic processing units, of which two
The same arithmetic processing is executed by using one arithmetic processing device, the arithmetic results are mutually compared periodically, and when an abnormality is detected based on the comparison result, the processing is switched to another arithmetic processing device and the arithmetic processing is executed again. In an arithmetic processing system, trace data storage means for extracting trace data indicating the progress of arithmetic operation from each arithmetic processing device and cyclically writing the trace data in a memory common to each arithmetic processing device when comparing the arithmetic results of the two arithmetic processing devices; Control means for prohibiting writing to the area so that the trace data of each processing device written in the trace data storage means is not overwritten when an abnormality is detected in the comparison of the calculation results. Arithmetic processing system. And a trace data sending means for reading and sending the trace data written in the memory from the trace data storing means in response to a command from the outside. 2. The arithmetic processing system according to claim 1, wherein, when is transmitted, the control means releases the write prohibition at the time of detecting an abnormality.