JPH056286A - Processor system - Google Patents

Abstract

PURPOSE:To facilitate fault analysis or the specification of a broken-down processor. CONSTITUTION:This system is provided with a comparing means 3 which is provided to compare coincidence between the respective outputs of plural micro- processors 1 and 2, a storing means 4 which is provided to store the history of one arbitrary output from the processor and a control line 6 which is provided to stop write to the storing means 4 when the comparing means 3 detects non-coincidence between the outputs from the processors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor system having a redundant monitoring function.

[0002]

2. Description of the Related Art A conventional processor system of this type is
Having a plurality of processors and one comparing means,
The comparing means compares the outputs of the processors for coincidence, and if a non-coincidence is detected, it is a mechanism for stopping the processors.

[0003]

In this conventional processor system, when the comparison means detects a mismatch, it does not have the state history information of the output until the mismatch occurs, so that the failure analysis and the failure processor It was difficult to identify.

[0004]

A processor system according to the present invention comprises a comparing means for comparing individual outputs of a plurality of processors, a storage section for storing a history of any one output of the processors, and a comparing means for the processor. And a control means for stopping the writing to the storage means when a discrepancy in the outputs from the above is detected.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a state history device according to an embodiment of the present invention.

The microprocessors 1 and 2 have a duplicated system configuration and perform the same operation in parallel with each other.

The comparing means 3 includes microprocessors 1 and 2.
In this example, the outputs of the microprocessors 1 and 2 are held in the register 31 inside the comparison means 3, and the output of the register 31 is compared by the comparison circuit 32. I am taking it.

The storage means 4 is means for storing the output of the microprocessor 1. In this example, the counter 5 sequentially updates the address for writing the output to the storage means 4, so that the writing to the storage means 4 becomes full. When it becomes, the address is returned to the initial value and overwritten.

The control means 6 controls the writing of the storage means 4, and normally, a write enable signal is sent to the information line 10.
The storage means 4 is notified via 1. However, when the comparison means 3 detects a mismatch, the control means 6 causes the information line 10
The comparison means 3 receives a notice of non-coincidence via 2 and simultaneously notifies the storage means 4 of non-permission of writing via the information line 101.

Next, the operation will be described.

The comparison means 3 compares the outputs of the microprocessor 1 and the microprocessor 2 as described above. When a match is detected, the comparison means 3 has a structure in which no signal is sent out, so the outputs are compared in order.

When the mismatch is detected, the mismatch signal is notified to the microprocessors 1, 2, the register 31, the counter 5 and the control means 6 through the information line 102. Microprocessors 1, 2, register 31 and counter 5
Is designed to stop when a mismatch signal is notified. Further, when the control means 6 receives the disagreement signal, the writing to the storage means 4 is stopped as described above.

In this example, two microprocessors 1,
Although only the case of 2 has been described, the present invention is not limited to this, and it is obvious that the same applies to three or more processors.

[0015]

As described above, according to the present invention, by writing the output from the processor in the storage means, when the comparison means detects the mismatch, the history until the mismatch occurs can be held. This has the effect of facilitating fault analysis and identification of the faulty processor.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Microprocessor 2 Microprocessor 3 Comparison means 4 Storage means 5 Counter 6 Control means 31 Register 32 Comparison circuit 101 Information line 102 Information line

Claims (1)

Claim: What is claimed is: 1. Comparing means for comparing the coincidence of individual outputs of a plurality of processors, storage means for storing a history of any one output of the processor, and the comparing means for the processor. And a control means for stopping writing to the storage means when a mismatch of outputs from the above is detected.