JPH04106944A - Wafer testing - Google Patents

Wafer testing

Info

Publication number
JPH04106944A
JPH04106944A JP22479490A JP22479490A JPH04106944A JP H04106944 A JPH04106944 A JP H04106944A JP 22479490 A JP22479490 A JP 22479490A JP 22479490 A JP22479490 A JP 22479490A JP H04106944 A JPH04106944 A JP H04106944A
Authority
JP
Japan
Prior art keywords
wafer
stage
probe
tester
height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22479490A
Other languages
Japanese (ja)
Inventor
Yuji Miyagi
雄治 宮城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22479490A priority Critical patent/JPH04106944A/en
Publication of JPH04106944A publication Critical patent/JPH04106944A/en
Pending legal-status Critical Current

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  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To test wafers automatically without removing a probe card and enhance the rate of operation by installing an insulation board having a certain level of insulation resistance which allow electric current to flow, the current being smaller than a current value of a minimum resolution by a tester. CONSTITUTION:An insulation board is set up on a stage where the insulation board has a certain level of insulation resistance which allows electric current to flow, the current being smaller than a current value of a minimum resolution by a tester. The elevation of a stage surface and the thickness of a wafer placed on the stage are measured with a capacitance sensor. The measurement results and the wafer's height placed in contact with a probe for a probe card are stored and the insulation board set up on the stage is carried under the probe based on the measurement results of the wafer where a measurement condition setting change signal is output to the tester. The height of the insulation board which is brought in contact with the probe is determined based on the height data stored. Then, the stage is made to rise up to a position where an arbitrary setting value is added to the height so as to inspect the characteristics of the probe card with the tester. This construction makes it possible to inspect automatically wafers without removing the probe card and hence improve the rate of operation.

Description

【発明の詳細な説明】 [産業上の利用分野1 本発明はウェハ検査工程におけるウェハの試験方法に関
し、特にウェハの測定結果に基づいてプローブカードの
特性検査をプローバに取付けた状態でテスタを用いて測
定しつつウェハの試験を行う方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a wafer testing method in a wafer inspection process, and in particular to a test method for testing the characteristics of a probe card based on wafer measurement results using a tester attached to a prober. The present invention relates to a method for testing wafers while making measurements.

〔従来の技術1 従来におけるウェハ検査工程でのウェハの試験方法につ
いて第2図のフロー図を用いて説明する。
[Prior Art 1] A conventional wafer testing method in a wafer inspection process will be described with reference to the flowchart shown in FIG.

図において、プローバにウェハをセットし、測定条件を
設定するための操作10(以下「セットアツプ」と称す
。)を行う工程で不良が設定数連続して発生した場合に
プローバにアラームを発生させるための連続不良設定1
1を行い、同様に特定のBINが連続して発生したとき
プローバにアラームを発生させるための連続BIN設定
I2を行い一連のセットアツプ操作を終了させ、ウェハ
をロード13L、ステージに乗せアライメント14を行
い、プローバに接続したテスタを用いてウェハの測定を
開始15する。
In the figure, an alarm is generated on the prober if a set number of defects occur consecutively in the process of setting the wafer on the prober and performing operation 10 (hereinafter referred to as "set-up") for setting the measurement conditions. Continuous failure setting 1 for
1, and similarly perform continuous BIN setting I2 to generate an alarm on the prober when a specific BIN occurs continuously, complete the series of setup operations, load the wafer 13L, place it on the stage, and perform alignment 14. Then, measurement of the wafer is started using a tester connected to a prober (15).

テスタに接続したプローブカードのプローブが接触して
いるウェハ上のICの測定結果が良品か否かを判断+6
L、良品であれば現在測定していウェハの全ICの測定
が完了したか否かを判断17シ、全ICの測定が完了し
ていなければ次のICへインデックスし、再び測定を開
始15する。全ICの測定が完了したならば全ウェハを
測定したか否かを判断18し、まだ残っていればウェハ
をアンロードし、次のウェハをロード13シ、上記操作
を繰り返す。
Determine whether the measurement result of the IC on the wafer that is in contact with the probe of the probe card connected to the tester is a good product or not +6
L. If it is a good product, determine whether the measurement of all ICs on the wafer currently being measured has been completed 17. If the measurement of all ICs has not been completed, index to the next IC and start measurement again 15. . When the measurement of all ICs is completed, it is determined 18 whether all the wafers have been measured, and if there are any remaining wafers, the wafer is unloaded, the next wafer is loaded 13, and the above operation is repeated.

ICの測定結果判断工6で不良品の場合は連続不良か否
かを判断19シ、連続不良でなければ連続BINか否か
を判断20シ、連続BINでなければ不良ICに対して
マーキング21を行い、残りのICがあるか否かを判断
171.、、同様に繰り返す。
If it is a defective product in the IC measurement result judgment step 6, judge whether it is a continuous defect or not 19. If it is not a continuous defect, judge whether it is a continuous BIN 20. If it is not a continuous BIN, mark the defective IC 21. 171. and determines whether there are any remaining ICs. ,, repeat in the same way.

連続不良の判断19あるいは、連続BINの判断20で
連続不良又は連続したBINの値がプローバに設定した
設定値に達した場合、基本的チエツク22としてプロー
ブカードのプローブとICのパッドの位置が合っている
か否かを判断し、合っていなければアライメントのズレ
又は特定のプローブのズレのいずれであるかを判断23
シ、アライメントズレの場合は、アライメント14から
操作を繰り返し、特定プローブがズしている場合は、プ
ローブカードの交換24を行い、測定中のウェハと残り
分のウェハについてセットアツプ10から行う。
If the continuous failure judgment 19 or the continuous BIN judgment 20 shows that the value of continuous failures or consecutive BINs reaches the set value set in the prober, a basic check 22 is to check whether the probes of the probe card and the pads of the IC are aligned. If it does not match, determine whether it is a misalignment or a misalignment of a specific probe 23
If the alignment is misaligned, repeat the operation from alignment 14. If the specific probe is misaligned, replace the probe card 24, and perform setup 10 for the wafer being measured and the remaining wafers.

基本的なチエツク22で問題がなければ測定を中断25
シ、テスタの機能チエツクを行いテスタの良否の判断2
6を行い、不良であればテスタの修理27を行う。この
判断においてテスタが正常であれば、プローバからプロ
ーブカードを外しチエツク28を行いプローブカード専
用の測定器でプローブの高さバラツキ、接触抵抗値、リ
ーク量の測定を行い良否の判断29を行い、プローブカ
ードに問題がなければ製品の問題30と判断し、測定続
行あるいは廃棄の選択を行って作業を続行する。
If there is no problem in the basic check 22, stop the measurement 25
Check the function of the tester and judge whether the tester is good or bad 2
6, and if the tester is defective, the tester is repaired 27. If the tester is normal in this judgment, remove the probe card from the prober, perform a check 28, measure the height variation of the probe, contact resistance value, and leakage amount with a measuring instrument dedicated to the probe card, and make a judgment 29 as to whether it is good or bad. If there is no problem with the probe card, it is determined that there is a product problem 30, and the work continues with the selection of continuing measurement or discarding.

プローブカードを不良と判断したときはプローブカード
を交換3Iシ、測定中のウェハと残り分のウェハについ
てセットアツプ10から作業を行っていた。
When the probe card was determined to be defective, the probe card was replaced (3I), and work was started from setup (10) on the wafer being measured and the remaining wafers.

[発明が解決しようとする課題] 最近のウェハ検査工程においては、DRAMのような大
量生産に合わせた多数個並列測定の比率の増大、ASI
C,TAB等に関してはプローブカードが多ビン化して
きいおり年々増加していく傾向にあるが、現在のプロー
ブカードの技術では、従来のシングル測定で、かつ少数
ビンのプローブカードと比較し、価格は5〜20倍位に
なったが、価格とは相反してプローブの長さの変化、プ
ローブピッチの縮小化、針量角度の多段化からプローブ
の寿命は従来よりも172〜1710位になっている。
[Problem to be solved by the invention] In recent wafer inspection processes, the ratio of parallel measurement of multiple devices has increased in line with mass production such as DRAM, and ASI
Regarding C, TAB, etc., the number of probe cards is increasing year by year as the number of bins increases, but with the current probe card technology, the price is lower than that of the conventional single measurement probe card with a small number of bins. However, contrary to the price, the life of the probe has become 172 to 1710 times longer than before due to changes in the length of the probe, reduction in the probe pitch, and multistage needle amount angle. ing.

従ってウェハ検査工程におけるプローブカードの信頼性
を従来のように得ることが困難になってきた。
Therefore, it has become difficult to obtain the reliability of the probe card in the wafer inspection process as in the past.

このため測定時のコンタクト回数に対するプローブカー
ドのチエツク回数が増大し、テスタ、プローバの検査装
置そのものの性能、信頼性は向上しているのに稼動率が
向上しないという問題点があった。
For this reason, the number of checks of the probe card increases relative to the number of contacts made during measurement, and although the performance and reliability of testers and prober inspection devices themselves have improved, there has been a problem that the operating rate has not improved.

またプローブカードのチエツク作業の増加により作業工
数も増加し、ウェハのテストコストも従来より上昇する
という問題点があった。
In addition, the number of man-hours increases due to the increase in the number of probe card checking operations, and the wafer test cost also increases compared to the conventional method.

本発明の目的はプローブカードを外すことなく自動的に
良否を判定し、稼動率を向上させるウェハの試験方法を
提供することにある。
An object of the present invention is to provide a wafer testing method that automatically determines pass/fail without removing the probe card and improves the operating rate.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するため、本発明に係るウェハの試験方
法においては、テスタによる最小分解能の電流値よりも
少ない電流が流れる程度の絶縁抵抗を有する絶縁板をス
テージに設置し、ステージ表面の高さとステージに乗せ
たウェハの厚さを容量センサーで測定し、その測定結果
を記憶し、かつ該ウェハをプローブカードのプローブに
接触させたときの高さを記憶し、ウェハの測定結果に基
づいて、ステージに設置した前記絶縁板を前記プローブ
の下まで移動させ、テスタに測定条件設定変更の信号を
出力し、記憶させた高さデータから絶縁板がプローブに
接触する高さを求め、該高さに任意設定値を加えた位置
までステージを上昇させ、テスタてプローブカードの特
性を検査させ、基準範囲内の値であるか否かを判断しな
からウェハの測定を行うものである。
In order to achieve the above object, in the wafer testing method according to the present invention, an insulating plate having an insulation resistance that allows a current smaller than the minimum resolution current value of the tester to flow is installed on the stage, and the height of the stage surface and Measure the thickness of the wafer placed on the stage with a capacitive sensor, store the measurement result, and store the height when the wafer is brought into contact with the probe of the probe card, and based on the measurement result of the wafer, Move the insulating plate installed on the stage to below the probe, output a signal to change the measurement condition setting to the tester, find the height at which the insulating plate contacts the probe from the stored height data, and calculate the height. The stage is raised to a position where an arbitrary set value has been added to the wafer, the tester is used to inspect the characteristics of the probe card, and the wafer is measured after determining whether the value is within the reference range.

[作用] テスタから受は取ったデータを基に連続した不良又は連
続したBINの値がプローバで設定した値に達した場合
、プローバのステージの一部に取付けられた絶縁板をプ
ローブに自動的に接触させ、テスタでプローブカードの
特性の検査を行う。
[Function] Based on the data received from the tester, if there are consecutive failures or consecutive BIN values reach the value set on the prober, the insulating plate attached to a part of the stage of the prober will be automatically attached to the probe. Test the characteristics of the probe card with a tester.

[実施例] 次に本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.

(実施例1) 第】図は本発明の一実施例を示すフロー図である。(Example 1) FIG. 1 is a flow diagram showing one embodiment of the present invention.

図において、処理ステップ50〜61は第2図の従来例
における処理ステップ10〜21に対応するものであり
、説明を一部省略する。
In the figure, processing steps 50 to 61 correspond to processing steps 10 to 21 in the conventional example of FIG. 2, and their explanation will be partially omitted.

まず、連続不良設定5I及び連続BIN設定52を行う
。次に、テスタによる最小分解能の電流値よりも少ない
電流が流れる程度の絶縁抵抗を有する絶縁板をステージ
の表面と同一高さに設置する。ここで、ウェハの径9位
置及び厚さを測定する容量センサーを用いて、ステージ
表面の高さとステージに乗せたウェハの厚さを測定し、
その測定結果をプローバの制御部に記憶させ、かつステ
ージ上のウェハをプローブカードのプローブに接触させ
たときの高さをプローバの制御部に記憶させる。
First, continuous failure setting 5I and continuous BIN setting 52 are performed. Next, an insulating plate having an insulation resistance that allows a current smaller than the minimum resolution current value of the tester to flow is installed at the same height as the surface of the stage. Here, the height of the stage surface and the thickness of the wafer placed on the stage are measured using a capacitive sensor that measures the diameter and thickness of the wafer.
The measurement result is stored in the control section of the prober, and the height when the wafer on the stage is brought into contact with the probe of the probe card is stored in the control section of the prober.

次にプローブカードのプローブをウェハ上の各rCに接
触させて特性測定を行う。
Next, the probe of the probe card is brought into contact with each rC on the wafer to measure the characteristics.

連続不良の判断59あるいは、連続BIN60で連続し
た不良又は連続したBINの値がプローバで設定した設
定値に達した場合、プローバの制御部よりテスタへIC
の測定プログラムからプローブカードの特性検査を行う
ためのプログラムに変更させる測定条件設定変更信号6
2を送り、またステージに取付けた絶縁板をプローブ下
へ移動63させ、プローブの制御部に記憶させた高さデ
ータから計算を行い適正な接触が得られるようにプロー
ブカードのプローブに絶縁板をコンタクト64させ、テ
ストスタート信号をテスタへ送り、交換したプログラム
を実行させ、プローブカードの絶縁板を用いたリーク量
の特性検査65を行い、プローブカードの良否を判断6
6シ、不良であればテスタのプログラムを測定プログラ
ムに戻すために測定条件設定信号72を送り、作業を中
断67aし、プローブカードを交換68シ、結果が良好
であれば同様に作業を中断67bし、テスタの機能チエ
ツクを行いテスタの良否の判断69を行い、不良であれ
ばテスタの修理70を行う。この判断においてテスタが
正常であれば製品の問題71と判断し、測定続行あるい
は廃棄の選択を行いウェハ検査工程の作業を続行させる
Judgment of continuous failures 59 or when the value of consecutive failures or consecutive BINs reaches the set value set by the prober in continuous BIN 60, the IC is sent from the control section of the prober to the tester.
Measurement condition setting change signal 6 to change from the measurement program to the program for testing the characteristics of the probe card
2, move the insulating plate attached to the stage under the probe 63, calculate it from the height data stored in the probe control unit, and place the insulating plate on the probe of the probe card so that proper contact can be obtained. Contact 64, send a test start signal to the tester, run the replaced program, perform a leakage characteristic test 65 using the insulating plate of the probe card, and judge the quality of the probe card 6.
6th, if the tester's program is defective, send a measurement condition setting signal 72 to return the tester's program to the measurement program, suspend the work 67a, replace the probe card 68sh, and if the result is good, similarly suspend the work 67b Then, the function of the tester is checked to determine whether the tester is good or bad (69), and if it is defective, the tester is repaired (70). In this determination, if the tester is normal, it is determined that there is a problem 71 in the product, and a selection is made to continue measurement or discard, and the wafer inspection process is continued.

(実施例2) 実施例1で説明した絶縁板の一部にステージ表面と同一
高さになるように設置した導電性の高い ・金属(例え
ば金メツキしたプレート)(以下「プレートJと称す。
(Example 2) A highly conductive metal (for example, a gold-plated plate) (hereinafter referred to as "Plate J") was installed on a part of the insulating plate described in Example 1 so as to be at the same height as the stage surface.

)を設けることにより、絶縁板だけではテスタを用いて
プローブカードのリーク量だけしか測定できなかったも
のをリーク量測定後プレーシ側にステージを動かし接触
位置を換えることにより自動的にプローブの高さバラツ
キ及び接触抵抗値も含んだ測定を行うことができるとい
う利点がある。
), the height of the probe can be automatically adjusted by moving the stage to the plate side and changing the contact position after measuring the leakage amount, which could only be measured by using an insulating plate with a tester. This method has the advantage of being able to perform measurements that include variations and contact resistance values.

[発明の効果] 以上説明したように本発明は、ステージに絶縁板を取付
けることにより通常のウェハ測定において連続した不良
又は連続したBINが設定値に達した場合、プローブカ
ードを外すことなく自動的に良否を判定することもでき
、稼動率を従来より向上させることができる効果がある
[Effects of the Invention] As explained above, the present invention has an insulating plate attached to the stage so that when consecutive defects or consecutive BINs reach a set value during normal wafer measurement, the probe card can be automatically measured without removing the probe card. It is also possible to determine the quality of the product, which has the effect of improving the operating rate compared to the past.

またプローブカードのチエツク作業も同様に自動的に行
えるようになったので作業工数を減少させることができ
、ウェハのテストコストを下げることができる効果も有
する。
In addition, since the probe card check operation can be performed automatically, the number of man-hours can be reduced, and wafer testing costs can also be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明にかかるウェハの試験方法を示すフロー
図、第2図は従来例を示すフロー図である。 特許出願人  日本電気株式会社 V+
FIG. 1 is a flowchart showing a wafer testing method according to the present invention, and FIG. 2 is a flowchart showing a conventional example. Patent applicant: NEC Corporation V+

Claims (2)

【特許請求の範囲】[Claims] (1)テスタによる最小分解能の電流値よりも少ない電
流が流れる程度の絶縁抵抗を有する絶縁板をステージに
設置し、ステージ表面の高さとステージに乗せたウエハ
の厚さを容量センサーで測定し、その測定結果を記憶し
、かつ該ウエハをプローブカードのプローブに接触させ
たときの高さを記憶し、ウエハの測定結果に基づいて、
ステージに設置した前記絶縁板を前記プローブの下まで
移動させ、テスタに測定条件設定変更の信号を出力し、
記憶させた高さデータから絶縁板がプローブに接触する
高さを求め、該高さに任意設定値を加えた位置までステ
ージを上昇させ、テスタでプローブカードの特性を検査
させ、基準範囲内の値であるか否かを判断しながらウエ
ハの測定を行うことを特徴とするウエハの試験方法。
(1) An insulating plate having an insulation resistance that allows a current smaller than the minimum resolution current value by the tester to flow is installed on the stage, and the height of the stage surface and the thickness of the wafer placed on the stage are measured with a capacitive sensor. The measurement result is stored, and the height when the wafer is brought into contact with the probe of the probe card is stored, and based on the measurement result of the wafer,
Move the insulating plate installed on the stage to below the probe, output a signal to change measurement condition settings to the tester,
Determine the height at which the insulating plate contacts the probe from the stored height data, raise the stage to a position where an arbitrary setting value is added to the height, and test the characteristics of the probe card with a tester to confirm that it is within the standard range. A wafer testing method characterized by measuring the wafer while determining whether the wafer has a value.
(2)前記絶縁板の一部に導電抵抗値の低い金属を有す
ることを特徴とする請求項第(1)項記載のウエハの試
験方法。
(2) The wafer testing method according to claim (1), wherein a part of the insulating plate includes a metal having a low conductive resistance value.
JP22479490A 1990-08-27 1990-08-27 Wafer testing Pending JPH04106944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22479490A JPH04106944A (en) 1990-08-27 1990-08-27 Wafer testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22479490A JPH04106944A (en) 1990-08-27 1990-08-27 Wafer testing

Publications (1)

Publication Number Publication Date
JPH04106944A true JPH04106944A (en) 1992-04-08

Family

ID=16819307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22479490A Pending JPH04106944A (en) 1990-08-27 1990-08-27 Wafer testing

Country Status (1)

Country Link
JP (1) JPH04106944A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111929566A (en) * 2020-08-20 2020-11-13 厦门市三安集成电路有限公司 Wafer testing method, device and control equipment thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111929566A (en) * 2020-08-20 2020-11-13 厦门市三安集成电路有限公司 Wafer testing method, device and control equipment thereof

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