JPH04106929A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to relax the restrictions on etching time for self-alignment contact and stabilize manufacture by using an Si3N4 film, etc., as stopper at the time of contact etching. CONSTITUTION:A field oxide film 2, a gate oxide film 3, an SiO2 film 5, and a gate electrode 4 are formed on a P-type silicon substrate 1. Then, an SiO2 film is made to grow and etched back, thereby forming a side wall 7 comprising the SiO2 film on the electrode 4. An Si2N4 film 12 is also made to grow to so that a phosphorous silicate glass film 8 may be formed as an interlaminar insulation film 8. The film 8 is selectively etched with a resist 9 as a mask, thereby forming a contact hole 10. The film 12 is adapted not to disappear by selecting the condition for etching rate. Then, the film 12 in the contact hole and the film 3 are removed by etching, which makes it possible to provide enough time to etch and hence enhance yields.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a contact hole.

[Conventional technology]

As semiconductor devices become faster and more highly integrated, patterns become finer and the size of contact holes approaches submicron.

As the contact hole shrinks, the distance to the gate electrode and the alignment margin become stricter.

Recently, self-aligned (self-aligned) contacts are often used, which do not require an alignment margin between the contact hole and the gate electrode.

A method of manufacturing a semiconductor device using self-line contacts according to the prior art will be described with reference to FIGS. 3(a) to 3(e).

First, as shown in FIG. 3 (a), a layer of 5000 mm thick is formed on a P-type silicon substrate 1 by LOCO3 selective oxidation method.
A field oxide film 2 for device isolation is formed to a thickness of 3
A gate oxide film 3 of 0.000 nm is formed, and polysilicon with a thickness of 3000 nm and silicon with a thickness of 3000 nm are formed using the CVD method.
By sequentially growing 02 films and selectively etching the 5
An i02 film 5 and a gate electrode 4 are formed, and arsenic ions are implanted to form N-type diffusion layers 6 and 6a.

Next, as shown in FIG. 3(b), by etching back the SiO□ film deposited by the CVD method to a thickness of 3000, a sidewall 7 is formed on the gate electrode 8i4.
form.

Next, as shown in FIG. 3(c), a PSG film 8 having a thickness of 3,000 wafers is deposited by the CVD method.

Next, as shown in FIG. 3(d), selective etching is performed using the photoresist as a mask to form contact holes 10 in a cell-aligned manner.

Next, as shown in FIG. 3(e), aluminum wiring 11 is formed to complete the element section.

[Invention or problem to be solved]

The self-line contact process according to the conventional technology consists of the sidewall of the gate electrode that should be left and the BSG that should be removed.
Since the membrane is the same 5i02, there is a drawback that there is little margin for machining and notching time.

Therefore, if over-etching is performed in consideration of interlayer film thickness variations and etching rate variations, the gate electrode will be exposed to the contact hole, resulting in a short-circuit failure.

Further, when the interlayer film thickness is increased, over-etching becomes necessary, which further reduces the yield.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes, in the contact hole forming step, forming a gate electrode made of a polysilicon film, and then forming sidewalls on the gate electrode by depositing and etching back an insulating film; After depositing an insulating film such as a silicon nitride film on the entire surface, PS
After depositing an interlayer insulating film such as a G film, there is a step of selectively etching only the interlayer insulating film using lithography technology to form a contact hole, and then sequentially etching the insulating film inside the contact hole and the gate insulating film. The process consists of the following steps:

〔Example〕

Regarding the first embodiment of the present invention, FIGS. 1(a) to (f)
Explain with reference to.

First, as shown in FIG. 1 (a), a field 2 with a thickness of 5000 nm is formed on a P-type silicon substrate 1 by the LOGO3 selective oxidation method, and a gate oxide film 3 with a thickness of 300 nm is formed.
A polysilicon film with a thickness of 3,000 thick and a gate oxide film with a thickness of 3,000 thick are formed by the CVD method, and an SiO2 film 5 and a gate electrode 4 are formed by lithography.

Next, as shown in FIG. 1(b), a 3,000-thick SiO2 film is grown by CVD and etched back to form a sidewall 7 made of an SiO2 film on the gate electrode 4. Next, as shown in FIG.

Next, as shown in FIG. 1(c), a 5i3N4 (silicon nitride) film 12 with a thickness of 1000 layers is grown by the CVD method, and a PSG film 8 with a thickness of 1.0 μm is grown as an interlayer insulating film.

Next, as shown in FIG. 1(d), contact holes 10 are formed by selectively etching the PSG film 8 using the resist 9 as a mask.

At this time, the Si3N4 film 12 is prevented from being lost by etching by selecting conditions where the etching rate is high for the 5i02 film and the PSG film, and the etching rate is high for the 5isN4 film.

Next, as shown in FIG. 1(e), the Si3N4 film 12 and gate oxide film 3 in the contact hole are removed by etching.

Next, as shown in FIG. 1(f), the resist 9 is removed and aluminum wiring 11 is formed to complete the element section.

Next, as a second embodiment of the present invention, a stacked DRA
When applied to M memory cells, Fig. 2(a)
This will be explained with reference to (f).

First, as shown in FIG. 2(a), a field oxide film 2, a gate oxide film 3, and a gate electrode [
4. Form a SiC2 film.

Next, phosphorus is ion-implanted to form N-type diffusion layers 13, 13a, and a sidewall 7 made of 5IO2 is formed, and then arsenic is ion-implanted to form N-type diffusion layers 6, 6a to complete the LDD structure. obtain.

Next, as shown in Figure 2<b), a thickness of 1000 mm is applied to the entire surface.
A contact hole 17 is formed on the N-type diffusion layer 6.13, and polysilicon 15 is grown to a thickness of 2,000 yen and selectively etched.

Next, as shown in FIG. 2(c), an 813 N4 film is grown on the entire surface as a capacitive insulating film for the capacitor, and a 400-thickness polysilicon film is grown, and then polysilicon is grown to a thickness of 2000-thickness, and selectively etched to form a polysilicon film. Silicon 16 is formed, and a PSG film 8 with a thickness of 1.0 μm is grown as an insulating film between the eyebrows.

Next, as shown in FIG. 2(d), the resist 9 and the PSG film 8 are etched as a mask to form the contact hole 1.
form 0.

Next, as shown in FIGS. 2(e) and 2(f), S i s N 4M 12 and 5i02 in the contact hole 10
The film 14 is etched, the resist 9 is removed, and an aluminum wiring 11 is formed to complete the element section.

In this example, the Si3N4 film used as the capacitive insulating film is used as a contact etching stopper, so
The present invention can be applied without increasing the number of manufacturing steps.

〔Effect of the invention〕

By using the Si3N4 film as a stopper during contact etching, the etching time for the self-line contact was made more flexible, and a stable manufacturing process could be achieved.

Since the SiO□ etching time after removing the aged Si3N4 film can be shortened, it is easier to control the Si02 film on the gate electrode in the contact hole, and short circuits between the contact and the gate electrode are reduced. , reliability has improved, and it has become possible to form contacts with stable yields.

[Brief explanation of drawings]

1(a) to (f) are cross-sectional views showing a first embodiment of the present invention, FIGS. 2(a) to (f) are cross-sectional views showing a second embodiment of the present invention, and FIG. Figures (a) to (e) are cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Gate oxide film, 4... 5in2 film, 5...
・Polysilicon film, 6, 6a...N-type diffusion layer, 7...
・Side wall, 8... PSG film, 9... Resist, 10... Contact hole, 11... Aluminum wiring, 12... Si3N4 film, 13... N-type diffusion layer,
14...5i02 film, 15...polysilicon, 16
...Polysilicon, 17...Contact hole.

Claims (1)

[Claims] 1. A step of sequentially forming a gate insulating film, a polysilicon film, and a first insulating film on the surface of a semiconductor substrate of one conductivity type, and sequentially selecting the first insulating film and the polysilicon film. etching to form a gate electrode; forming an opposite conductivity type layer on the surface of the semiconductor substrate; forming sidewalls on the gate electrode by depositing and etching back a second insulating film; forming a contact hole by depositing a third insulating film and a fourth insulating film and selectively etching only the fourth insulating film, and depositing the third insulating film in the contact hole and the gate insulating film. 1. A method of manufacturing a semiconductor device, comprising the step of sequentially etching a film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film, the second insulating film, and the fourth insulating film are silicon oxide films, and the third insulating film is a silicon nitride film.