JPH0399474A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which is excellent in write efficiency and readout characteristics and densely integrated by a method wherein impurity is of the same conductivity type as the substrate is diffused into the substrate at the same time when impurity whose conductivity type is opposite to that of a semiconductor substrate is diffused into the substrate to form a source and a drain region. CONSTITUTION:Impurity such as boron 14 whose conductivity type is the same as that of a silicon substrate 1 is injected into the substrate 1. At this point, a high impurity concentration layer 15 whose conductivity type is the same as that of the substrate 1 is formed on the regions of the surface of the substrate 1 which are to serve as a source and a drain. Then, impurity such as arsenic 16 whose conductivity type is opposite to that of the substrate 1 is injected into the substrate 1 to form injected layers 17 which serve as a drain and source region later. Next, impurity injected into the injected layers 17 is diffused by a thermal treatment to form a source region 7 and a drain region 8. A impurity concentration layer 15 whose conductivity type is the same as that of the silicon substrate is formed outside the source region 7 and the drain region 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to a method of manufacturing a nonvolatile memory semiconductor device in which data is written using avalanche injection.

[Conventional technology]

The most commonly used conventional device of this type is an N-channel type E F ROM (Electrically
Promable Read Only Memory
y) There is a device. FIG. 5a is a plan view of this EPROM device, and FIG.
FIG. 5C is a sectional view taken along the line ■--■ in FIG. 5a.

In the figure, 1 is a P-type silicon substrate, 2 is a field oxide film for element isolation, 3 is a first gate oxide film, 4 is a first polycrystalline silicon film which is a floating gate, 5 is a second gate oxide film, 6 is a second polycrystalline silicon film serving as a control gate; 7
and 8 are a source region and a drain region formed in silicon substrate 1 using second polycrystalline silicon film 6 and field oxide film 2 as masks, respectively. Also,
9 is a PSG film which is an insulating film between the eyebrows, and lO is an aluminum wiring.

[Problem to be solved by the invention]

In the EPROM device configured as described above, it is disclosed in Japanese Patent Publication No. 64-3072 that the P-type impurity diffusion layer 12 is provided in the channel region 11 near the surface of the silicon substrate 1 to promote the generation of hot electrons and improve the writing efficiency.
It is well known as shown in the publication.

In the EPROM device shown in FIG. 5, the channel region! ! The overall figure shows the case where a P-type impurity diffusion layer 12 is formed using a resist as a mask. When the impurity concentration of 2 is increased, the initial threshold voltage (when there are no electrons in the floating gate) also increases significantly, and the read characteristics as a ROM deteriorate.

Therefore, as shown in Japanese Patent Publication No. 64-3072, hot electrons are generated in the channel region near the drain region 8.
A P-type impurity diffusion layer is formed by opening a resist hole only in the nearby channel region! 2 is considered, but this method requires a margin for mask alignment with the control gate 6, causing the problem that miniaturization is difficult.

On the other hand, as a method of providing P-type impurity diffusion layer 12 only in a part of channel region 11 without requiring a mask, there is a method shown in US Pat. No. 4,114,255. here,
An impurity layer of the same conductivity type as the silicon substrate 1, which is formed under the field oxidation WA2 for the purpose of element isolation, is sufficiently diffused in the lateral direction to reach the channel region. In this case, two transistors with different impurity concentrations in the channel regions are arranged in parallel between the drain region 8 and the source region 7. In a normal EPROM, the drain region 8 and control gate 6 of each memory transistor are arranged in parallel. 0 that are common and arranged in a matrix, for example LM EF
In ROM, there are 512 or 10 pieces on one aluminum 1iio.
Typically, the drains of 24 memory transistors are connected. When writing to EPROM, write 7 to the drain.
It is performed by applying a relatively high voltage of ~1OV,
If the memory transistors arranged in parallel are punched through, the voltage of the drain region 8 will drop, resulting in a decrease in write performance.The memory transistor shown in the above-mentioned U.S. Pat. No. 4,114,255 has a channel region with a low impurity concentration. Because the transistors are lined up side by side, the above problems are likely to occur.

This invention was made to solve the above-mentioned conventional problems, and its purpose is to provide a manufacturing method for obtaining a densely integrated semiconductor device with good write efficiency and read characteristics. do.

[Means to solve the problem]

A semiconductor device manufacturing method according to the present invention is a nonvolatile memory semiconductor device in which a floating gate electrode and a control gate electrode are respectively formed on a channel region in a semiconductor substrate via an insulating film, and writing is performed by avalanche injection. A manufacturing method, comprising: forming a first insulating film, a first conductor layer, a second insulating film, and a second conductor layer on a whole surface of a semiconductor substrate having a first conductivity type, and etching a second conductor layer, a second insulating film, and a first conductor layer in sequence using a resist as a mask to determine the source-drain distance of the memory transistor; and etching the resist and the second conductor layer. Alternatively, using the first conductor layer as a mask, impurities of the same first conductivity type as the semiconductor substrate are added,
A step of implanting into the semiconductor substrate which will become a drain region at least near the channel, and a step of implanting a conductive material of a conductivity type opposite to the first conductivity type (a second conductivity type) using the resist, the second conductor layer, or the first conductor layer as a mask. ) into the semiconductor substrate in regions that will become sources and drains; and diffusing the first conductivity type impurity and the second conductivity type impurity implanted into the semiconductor substrate. It is characterized by:

[Effect]

In the method for manufacturing a semiconductor device of the present invention, when forming a source region and a drain region by diffusing an impurity of a conductivity type opposite to that of the semiconductor substrate, at the same time, by diffusing an impurity of the same conductivity type as the semiconductor substrate, A high concentration impurity diffusion region having the same conductivity type as the semiconductor substrate can be formed at least outside the drain region.

As a result, for example, it is possible to increase the impurity concentration in the channel region near the drain of a memory transistor in an EPROM device to improve writing efficiency, and it is also possible to increase the impurity concentration only in a part of the channel region (near the drain). , it is possible to suppress the threshold voltage and improve read characteristics.

Further, transistors having different impurity concentrations in the channel regions can be arranged in series between the drain region and the source region, and the occurrence of punch-through can be suppressed.

〔Example〕

Hereinafter, one embodiment of the present invention will be described as an N-channel floating gate type E.
This will be explained using a PROM device as an example.

1A to 1E are sectional views showing the manufacturing process of the EPROM device according to this embodiment, and FIG. 2 is a sectional view of the completed EPROM device. Note that FIGS. 1A to 1E and FIGS. 2A and 2B show cross-sectional views taken along the line I--I of FIG. 5A (plan view) described above.

First, as shown in FIG. 1a, a non-active region on the entire surface of a P-type silicon substrate 1 is oxidized to a thickness of approximately 0.
A field oxide film 2 of about 61 Jj is formed, and a first gate oxide film 3 of about 300 layers thick is formed in the active region by thermal oxidation.

Next, as shown in FIG. 1, a first polycrystalline silicon film 4, which will become a floating gate, is deposited by about 3,000 people using the CVD method, and then an impurity such as phosphorus is thermally diffused into the first polycrystalline silicon film 4. The first polycrystalline silicon film 4 is etched using photolithography to determine the length of the floating gate (the distance shown in FIG. 5a). Thereafter, the first polycrystalline silicon film 4 is thermally oxidized to A second polycrystalline silicon film 6, which will become a control gate, is deposited on the second gate oxide film 5 by approximately 4,000 people using the CVD method. Using photolithography, the second polycrystalline silicon film 6 is sequentially formed using the resist!3 as a mask to determine the source-drain distance of the memory transistor.
．． Second gate oxide film5. and first polycrystalline silicon film 4
etching.

Next, as shown in FIG. 1C, an impurity of the same conductivity type as that of the silicon substrate 1, such as boron 14, is implanted using an ion implantation technique at an energy of 50 K eV to I.times.10"cm.sup.-'
inject. At this time, a high concentration layer 15 of impurities of the same conductivity type as the silicon substrate 1 is formed on the surface of the silicon substrate 1 in regions that will become the source and drain.

Next, as shown in FIG. 1d, after removing the oxide film 3a and resist 13 on the surfaces of the source/drain regions, an impurity of a conductivity type opposite to that of the silicon substrate 1, such as arsenic 16, is implanted at 50 KeV using ion implantation technology. 4×1 due to the energy of
01'cI11-2 implantation is performed to form an implantation layer 17 which will later become a source region and a drain region.

Next, as shown in FIG. 1e, heat treatment is performed at 950° C. for about 20 minutes to diffuse the impurities injected into the injection layer 17, forming a source region 7 and a drain region 8. Further, on the outside of the source region 7 and drain region 8, a high concentration layer 1 of impurities of the same conductivity type as the silicon substrate 1 is provided.
5 is formed.

Thereafter, in the same manner as described in the prior art, a PSG film 9, which is an insulating film between the eyebrows, and an aluminum wiring line 10 are formed to complete the EPROM device shown in FIG.

As described above, in the method for manufacturing a semiconductor device according to the above embodiment, boron 14, which is an impurity of the same conductivity type as that of the silicon substrate 1, implanted into the source/drain regions forms the diffusion layers of the source region 7 and the drain region 8. As shown in FIG. 1e and FIG. 2, a high concentration layer 15 of an impurity of the same conductivity type as the silicon substrate 1 is formed outside the source region 7 and drain region 8, as shown in FIG. 1e and FIG. can be formed in a self-aligned manner without requiring a mask.

FIG. 3 shows the impurity concentration distribution near the surface of the channel region 11 between the source and drain, where the solid line a is for the case according to the embodiment of the present invention, and the dotted line is for the case according to the prior art. . The impurity concentration at the center of the channel region 11 in both the prior art (dotted line b) and the embodiment (solid line a) is approximately 4X IQ"am-", whereas the impurity concentration in the drain in the embodiment (solid line a) The peak value of impurity concentration near region 8 is approximately 7 x 10 * 6 cIll
−*.

Also, the channel area! ! It has been found that in order to increase the impurity concentration near the drain region 8 from the center, the boron 14 to be implanted into the source region 7 and drain region 8 needs to be implanted at an energy of 50 KeV to approximately 2×10 cIn''2 or more. Ta.

In addition, as shown in the above embodiment, boron 14 was applied to the source/drain region 7.8 at 50 K eV at I x 10
” (to) When −2 was implanted, the threshold voltage seen from the control gate of the memory transistor was about 1.2■,
When the entire surface of the channel region ti is made to have the same impurity concentration as the channel impurity peak value (7X 10" cm-3) indicated by the solid line a in FIG. 2, the threshold voltage is approximately 2.0 to 2.2.
It became V.

Furthermore, a high concentration layer 1 of impurities of the same conductivity type as the silicon substrate 1 is provided outside the diffusion layers of the source region 7 and drain region 8.
5, the punch-through voltage mentioned in the conventional problem is naturally improved.

In the above embodiment, a high concentration layer 15 of impurities of the same conductivity type as that of the silicon substrate 1 was formed outside the source region 7 and drain region 8, but as shown in FIGS. Impurities of the same conductivity type as substrate 1 (boron 1
4), after forming a resist 16 having an opening 16a in at least a part of the region on the drain side adjacent to the channel region using a photolithography technique, implanting the resist 16 on the drain side using the resist 16 as a mask. Even if the high concentration layer 15 of impurities of the same conductivity type as the silicon substrate 1 is formed only in the region, substantially the same effect as in the embodiment described above can be obtained.

Further, in the above embodiment, boron 14 ions were implanted with the resist 13 for gate etching and the oxide film 3a for the first gate left;
Oxidation r! Ion implantation may be performed with A3a removed.

In addition, an impurity of the same conductivity type as the silicon substrate 1 (boron 14
) (FIG. 1c), the impurity of the same conductivity type (boron 14) is diffused by performing a predetermined heat treatment, and then the diffusion layers of the source region 7 and drain region 8 may be formed. , and a similar effect can be obtained even when applied to a P-channel transistor.

〔Effect of the invention〕

As described above, according to the method of manufacturing a semiconductor device of the present invention, the impurity concentration in the channel region near the drain of a memory transistor such as an EFROM device can be increased, and writing efficiency can be improved. Further, since the impurity concentration can be increased only in a portion of the channel region (near the drain), the threshold voltage can be suppressed and the read characteristics can be improved.

Further, transistors having different impurity concentrations in the channel regions can be arranged in series between the drain region and the source region, which has the effect of suppressing the occurrence of punch-through.

[Brief explanation of drawings]

FIG. 1 a % e is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a semiconductor device manufactured by the above manufacturing method, and FIG. 3 is an impurity concentration distribution on the surface of a channel region. 4a to 4b are process sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention, and FIGS. 5a to 5c are plan views showing a conventional semiconductor device, respectively. They are a sectional view taken along the I line and a sectional view taken along the m-1t line. In the figure, 1 is a silicon substrate, 3 is a first gate oxide film, 4 is a first polycrystalline silicon film, 5 is a second gate oxide film, 6 is a second polycrystalline silicon film, 7 is a source region, and 8 is a drain The regions 13 and 16 are resist, 14 is boron, 15 is a high concentration layer, and 16 is arsenic. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claim] A method for manufacturing a semiconductor device of a nonvolatile memory in which a floating gate electrode and a control gate electrode are each formed on a channel region in a semiconductor substrate via an insulating film, and writing is performed by avalanche injection. forming a first insulating film, a first conductor layer, a second insulating film, and a second conductor layer on one main surface of a semiconductor substrate having a first conductivity type; etching a second conductor layer, a second insulating film, and a first conductor layer in sequence using a resist as a mask to determine a source-drain interval; Using the conductor layer as a mask, impurities of the same first conductivity type as the semiconductor substrate are added,
A step of implanting into the semiconductor substrate which will become a drain region at least near the channel, and a step of implanting a conductive material of a conductivity type opposite to the first conductivity type (a second conductivity type) using the resist, the second conductor layer, or the first conductor layer as a mask. ) into the semiconductor substrate in regions that will become sources and drains, and by diffusing the first conductivity type impurity and the second conductivity type impurity implanted into the semiconductor substrate. and a drain region, and a step of forming a first conductivity type high concentration impurity diffusion layer at least outside the drain region near a channel.