JPH039426B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides a programmable read-only memory inserted into an IC socket.
Semiconductor integrated circuit devices (hereinafter referred to as LSI) such as Read Only Memory (hereinafter referred to as PROM)
The present invention relates to a discriminating device for discriminating the direction or type of.

For example, to write information to a PROM, the PROM to be written is inserted into a socket of a writing device, and a predetermined signal is applied to the PROM through this socket. In this case, if the PROM is inserted into the socket with the wrong product name or direction, the PROM that should receive the specified voltage or signal may
Since the pins (terminals) of the PROM will be different, an abnormal voltage will be applied to the PROM or an abnormal current will flow when power is supplied and writing starts. Because of this, the PROM may be destroyed. Therefore, great care must be taken when inserting an LSI such as a PROM into a socket.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a discriminating device that protects the LSI from destruction even when the wrong type of LSI or LSI is inserted in the wrong direction into a socket.

According to the present invention, there is provided a means for detecting the electrical characteristics of a plurality of predetermined pins in a socket into which a PROM is inserted in, for example, a writing device for a PROM, and an electrical characteristic of each of the plurality of pins detected thereby. means for determining the type or direction of the inserted PROM by a combination of the above, and when the type or direction determined by this determining means matches a predetermined one, the writing device is activated. means for making it work.

FIG. 1 shows a block diagram of a PROM writing device embodying the present invention.

In the figure, reference numeral 51 denotes a socket into which the PROM 50 is inserted, and has pins 1' to 24' that contact pins 1 to 24 of the PROM 50 in a one-to-one correspondence, respectively. 52 is an input/output interface (hereinafter referred to as PIA), which is
It has pins P ₁ to P ₂₄ connected to pins 1' to 24' of PROM 50. This PIA52 is
Microcomputer (hereinafter referred to as MC) 58
The operation is controlled by the write circuit 59 and the pins 1' to 24' of the socket 51 are connected;
Also, the pins 21' and 19' are connected to the pins P ₂₁ '' and P ₁₉ ''.

53 and 54 are discrimination circuits. The discrimination circuits 53 and 54 compare the voltage levels appearing at the terminals P21 and P19 of the PIA 52 with the internal reference voltage level in response to the control signal φ ₈ from the MC 58, and the comparison result is a binary signal "1". ” or “0” is output. Although not particularly limited, these discrimination circuits 53 and 54 are configured to send the above-mentioned binary signals to the MC 58 by control signals φ ₃ and φ ₄ from the MC 58 .

55, 56 and 57 are flip-flop circuits (hereinafter referred to as FF). These FF55,
The set and reset states of 56 and 57 are controlled by control signals φ ₆ and φ ₂ from the MC 58, and output a voltage as a power supply in the set state.

In other words, FF55 is in the set state.
The power supply voltage for the PROM 50 is output to the terminal ₂₄ ' of the PIA 52.

Further, the FFs 56 and 57 output test power supply voltages for determining the direction of the PROM 50 to the terminals 21'' and 29'' in the set state. Furthermore, these
Since the FF56 and the FF57 can perform the same operation, they can essentially be combined into one.

The MC 58 starts its operation upon receiving an operation start instruction signal at the terminal STR, and outputs control signals for the various circuits described above.

The write circuit 59 receives the control signal φ ₇ from the MC 58 and outputs a write information signal.

A power supply 60 supplies power supply voltage to the FFs 55, 56, 57, and the like.

62 is a display device, and a control signal φ ₅ is sent from the MC58.
The direction of the PROM 50 attached to the socket 51 is indicated by receiving the signal.

According to this embodiment, certain pins of socket 51', such as 21' and 19' and the
Resistor between pins 21″ and 19″ of FF56 and 57
R ₂ and R ₁ are connected.

FIG. 5 shows an outline of the configuration of the PIA 52. In this figure, all other pins except pins P ₁₉ and P ₂₁ are functionally connected to the write circuit 5, as shown by pins P ₁₂ and P ₁₂ ' as representatives.
9, the write information and voltage supplied from the FF 55 and the like are supplied to each pin of the socket 51.

Pins P ₁₉ ′ and P ₁₉ ″ are provided corresponding to the terminal P ₁₉ , and similarly, pins P ₂₁ ′ and P ₂₁ ″ are provided corresponding to the pin P ₂₁ . The pins P ₁₉ and P ₁₉ ″ are substantially directly connected to each other, but the pins P ₁₉ and P ₁₉ ′ are connected to each other by a transistor controlled by the control signal φ ₁ from the MC58. The above pin P ₁₉ ′ is connected via the switch S ₁ .
Combined with 8. Pin P ₁₉ ″ is coupled to the discrimination circuit 54 as described above. Similarly, pins P ₂₁ and P ₂₁ ″ are substantially directly connected, and pins P ₂₁ and P ₂₁ ′ are connected to each other as described above. is connected to via a switch S ₂ consisting of a transistor controlled by a control signal φ ₁ .

When determining the direction of the PROM 50, the resistor R ₂ is connected to the pins 21' and 19' of the socket 51.
Voltage is supplied through _R1 . The voltage levels generated at the pins 21' and 19' in accordance with the supply voltage are determined by the determination circuits 53 and 54.

The pins of the socket 51 that connect the above resistors R ₁ and R ₂ will cause changes in voltage and current characteristics depending on whether the PROM 50 is installed in the socket 51 in the normal direction or in the opposite direction. selected from among things.

Although not particularly limited, PROM can be used, for example, as a third
As shown in the figure, it has an output buffer circuit BA1 whose output terminal is connected to pin 21, and an output buffer circuit BA2 whose output terminal is connected to pin 19. Also, an output buffer circuit BA whose output terminal is connected to pin 9, which is symmetrical with pin 21 above.
3, and pin 7 located in point symmetry with the above pin 19.
Input buffer circuit IP1 with input terminal connected to
It has

Each of the circuits described above is composed of a plurality of N-channel insulated gate field effect transistors (hereinafter referred to as MISFETs) formed on one semiconductor substrate.

For example, as shown in FIG. 5, the output buffer circuit BA1 includes a depletion type load _MISFETQ1 connected between the power supply terminal _VDD and the output terminal _N1 , the gate and source of which are short-circuited, and the output terminal N1.
and an enhancement-type drive MISFETQ ₂ connected between the circuit's ground terminal GND and the circuit's ground terminal GND.

As shown in Figure 5, ground pin 1 of PROM50
If a positive voltage V _T is applied to the pin 21 through a resistor while the power supply pin 24 is grounded and the power supply pin 24 is open, the source of MISFETQ ₁ and the drain of MISFETQ ₂ will be connected to the positive voltage V _T. Semiconductor substrate SUB
The diode _D1 formed substantially between is in a reverse biased state and is in an off state. On the other hand, due to the above positive voltage V _T , the load MISFETQ ₁
The source S acts substantially as a drain, and the drain D acts substantially as a source. The MISFETQ ₁ is turned on by the positive voltage applied to the gate. Depending on the on state of the above MISFETQ ₁ , the voltage from pin 21 to the above MISFETQ ₁ is
A current path is formed that leads to V _DD , another circuit LCKT, and the ground terminal GND. Therefore, a voltage drop occurs across resistor R ₂ and the potential at pin 21 becomes low.

As shown in Figure 3, with pin 12 grounded,
Positive voltage V _T on pins 21, 19 through resistors R ₂ , R ₁
, both terminals 21 and 19 become low level.

When the direction of the PROM 50 in FIG. 3 is rotated by 180 degrees as shown in FIG. 4, the pins 21, 19 and 12 at the same positions as in FIG. 3 are changed to pins 9, 7 and 24, respectively.

In this case, since pin 24 is used as a power supply terminal, the equivalent circuit of buffer circuit BA3 connected to pin 9 is as shown in FIG.

Due to the positive voltage applied to pin 9, the depletion load MISFETQ ₆ is properly turned on, and a current path is formed from pin 9 to the MISFET Q ₆ and the grounded power supply terminal V _DD . As a result, the potential at pin 9 becomes a low level.

The input buffer circuit IP1 is originally, for example, the sixth
As shown, depreciation load MISFETQ ₃ ,
Consists of drive MISFETQ ₄ , etc. A protection diode _DZ is connected to the input side of the input buffer circuit in order to prevent the gate of MISFETQ ₄ from being destroyed by high voltage such as static electricity applied to pin 7. If it is as shown in Figure 4 above, the buffer circuit corresponding to Figure 6
IP1 is connected as shown in Figure 8. in this case,
For voltage applied to pin 7, the protection diode D _Z becomes reverse biased and remains off. Therefore, the potential at pin 7 is a positive voltage V _T
reach a high level.

The operation of the writing device shown in FIG. 1 is as follows.

In the initial state, the FFs 55 to 57 are MC
58 to the reset state.

The PROM 50 is attached to the socket 51, and then the control operation of the MC 58 is started.

The MC58 uses the control signal _φ1 to open the switches _S1 and _S2 of the PIA52, so that the potentials at the terminals _P21 and _P19 are disturbed by the undesired potentials appearing at the terminals _P21 ' and _P19 '. to avoid being Next, the FFs 57 and 5 are connected so that the voltage of the power supply 60 is applied to one end of each of the resistors _R1 and _R2 by the control signal _φ2 .
6 to the set state.

The voltage applied to pins P19 and P21 of PIA 52 by the above voltage is applied to pin 1 of socket 51.
It is determined by the electrical characteristics of pins 19 and 21 of PROM 50, which contact pins 9' and 21', respectively.

The voltages applied to the pins P19 and P21 are determined by the determination circuits 53 and 54, respectively, when the control signal _φ8 is outputted from the MC58.

The input binary signals of P ₁₉ and P ₂₁ are sent to the discrimination circuit 5.
3 and 54, respectively, and is compared with a reference binary signal "0" set inside each of the signals.

The discrimination output of the discrimination circuit 53 is the control signal φ ₃
is supplied to MC58 by. Similarly, the discrimination output of the discrimination circuit 54 is determined by the next control signal _φ4 .
8. The MC 58 determines the direction of the PROM 50 attached to the socket 51 based on the above two determination outputs.

The PROM shown in Figure 3 above is located in socket 5.
1 in the correct orientation, the discrimination circuits 53 and 54 output low level signals corresponding to the low levels of pins P ₂₁ and P ₁₉ .

When the MC 58 detects the two low-level discrimination outputs from the discrimination circuits 53 and 54, in other words, when it detects the normal mounting state of the PROM 50,
At the next timing, set FF55,
Make sure that the PROM50 is supplied with the proper power supply voltage. Almost simultaneously, the switches S ₁ and S ₂ of the PIA 52 are turned on, and the FFs 56 and 57 are reset. Next, the operation of the write circuit 59 is started.

When the PROM 50 is installed in the socket 51 at a position rotated by 180 degrees, the MC 58 receives a low level signal from the discrimination circuit 53 and a high level signal from the discrimination circuit 54. The MC 58 detects that the mounting direction of the PROM 50 is different from the normal direction based on the discrimination output of the discrimination circuit 54, and causes the display 62 to display the error in the mounting direction. In this case, the MC 58 leaves the FF 55 in the reset state.

In addition, in the above, pin 21 of socket 51
is at a low level during determination both when the PROM 50 is in a normal direction and when it is in a different direction. Therefore, if the correct type of PROM is installed in the socket, pin 2 of the above socket 51
1' is not useful for determining the direction of PROM.

The potential of pin 21' is used to detect different types of LSIs inserted into the socket.

As mentioned above, the combination of electrical characteristics of the multiple pins of the socket in which the PROM is installed is determined in advance, and then when the PROM to be written is inserted into the socket, the combination of the multiple pins of that PROM is determined in advance. Detects the electrical characteristics of the pin, determines the combination of electrical characteristics of each pin, and compares it with the combination determined in advance. Based on this comparison result, power is supplied to the PROM and If you control writing, it will try to write.
When inserting a PROM into a socket, even if you accidentally insert it backwards or insert the wrong type of PROM, the combination will not match the predetermined combination.
Based on this, control can be performed to prohibit power supply and writing to the PROM.
Therefore, even if you insert the wrong type of LSI into the socket or the wrong direction, this LSI will not be destroyed.

Please note that it may be inserted by mistake in advance.
Display 6 depending on PROM type and pin characteristics
2, for example, 62A and 62B (not shown), so that when the wrong type of PROM is inserted, the display 62A indicates an abnormality, and when the PROM is inserted in the wrong direction, the display 62B indicates an abnormality. can. This is convenient because the type of incorrect insertion into the socket can be seen on the display.

The present invention is not limited to the above-mentioned embodiments, and can be applied to other LSIs other than PROMs, such as by changing the number of pins for detecting electrical characteristics.

Alternatively, the resistors R ₁ and R ₂ and FFs 56 and 57 may be replaced with constant current circuits, and the current may be controlled to flow from the constant current circuits to the socket pins using the control signal φ ₂ .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a discriminating device according to an embodiment. FIG. 2 is a schematic diagram for explaining block 52 of FIG. 1. 3 and 4 are schematic diagrams of the PROM. 5 through 8 are circuit diagrams of example circuits used in PROM. 50...PROM, 51...Socket, 52...
...Input/output interface, 53, 54...Discrimination circuit, 55, 56, 57...Flip-flop circuit, 58...Microcomputer, 59...Power source, 60...Power source, 62...Display device.

Claims (1)

[Scope of Claims] 1. A socket to which a lead of a semiconductor integrated circuit device comes into contact, and a determination result of the electrical characteristics of a desired lead of the semiconductor integrated circuit device detected through the socket. a control means for detecting whether the circuit device is normally installed in the socket and forming a control signal based on the detection result; a voltage forming means for forming an operating voltage to be supplied to the circuit device and whose operation is controlled by the control signal so as not to form the operating voltage in an abnormal mounting state of the semiconductor integrated circuit device; In the apparatus, the control means controls the semiconductor integrated circuit mounted in the socket by comparing a combination of potentials appearing at a desired plurality of leads of the semiconductor integrated circuit device with a combination of potentials determined in advance. A discriminating device, characterized in that it is capable of detecting the type of circuit device, and is configured to control the operation of the voltage forming means based on the detection result of the mounting state and the detection result of the type. 2. The discrimination device according to claim 1, wherein the control means controls a display means for displaying the detection results. 3. The control means comprises a microcomputer which is operated to form the control signal after the detection.
2. Discrimination device according to item 1 or 2. 4. Claims 1 to 3, wherein the voltage forming means is configured to form an operating voltage to be supplied to a semiconductor integrated circuit device comprising a programmable read-only memory. The discrimination device according to one of the above.