JPH0391217A - Laminated ceramic capacitor and manufacture thereof - Google Patents

Laminated ceramic capacitor and manufacture thereof

Info

Publication number
JPH0391217A
JPH0391217A JP22769489A JP22769489A JPH0391217A JP H0391217 A JPH0391217 A JP H0391217A JP 22769489 A JP22769489 A JP 22769489A JP 22769489 A JP22769489 A JP 22769489A JP H0391217 A JPH0391217 A JP H0391217A
Authority
JP
Japan
Prior art keywords
electrodes
laminated
insulated
alternately
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22769489A
Other languages
Japanese (ja)
Inventor
Hikoharu Okuyama
彦治 奥山
Keiichi Nakao
恵一 中尾
Masahiro Kato
昌弘 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22769489A priority Critical patent/JPH0391217A/en
Publication of JPH0391217A publication Critical patent/JPH0391217A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To obtain a laminated ceramic capacitor of high laminated layer having no positional deviation of inner electrodes and no short circuit by passing individual inner electrodes alternately laminated with dielectric layers to both ends for leading outer electrodes, alternately insulating the inner electrodes at every other one at both ends, and providing the outer electrodes. CONSTITUTION:Dielectric ceramic green sheets 11a on which inner electrodes 12 are printed are sequentially laminated repeatedly at the same position while applying a temporary pressure to manufacture a laminated molded form. The obtained molded form is cut into chips, the end face of the side coated with the outer electrodes of the chip is masked, a barium titanate film is formed as an insulating film 14, and insulated. Inner electrodes 12 not insulated previously at the other end face are entirely similarly insulated, chips in which the electrodes 12 of both ends are alternately insulated at every other layer are baked, coated with silver paste as outer electrodes, and baked to form outer electrodes 13.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は積層セラミックコンデンサ及びその製造方法に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

従来の技術 近年、電子機器の小型化に伴い積層セラ□ツクコンデン
サの需要が咬す1す高1っている。
BACKGROUND OF THE INVENTION In recent years, as electronic devices have become smaller, the demand for multilayer ceramic capacitors has increased.

積層セラミックコンデンサの一般的な製造方法は、まず
チタン酸バリウム系磁器等の誘電体粉末と有機バインダ
及び有機溶剤からなるヌラリーを用いてドクターブレー
ド法等によりグリーンシートを作製する。
A general method for manufacturing a multilayer ceramic capacitor is to first prepare a green sheet using a doctor blade method or the like using a nullary made of dielectric powder such as barium titanate ceramic, an organic binder, and an organic solvent.

次に、このシートの上にパラジウム、白金等の貴金属を
主成分とした電極ペーストを用いてスクリーン印刷法等
によシ内部電極を形成する。
Next, internal electrodes are formed on this sheet by screen printing or the like using an electrode paste whose main component is a noble metal such as palladium or platinum.

次に、内部電極を形成したグリーンシートを内部電極層
が誘電体層を挾んで交互に対向するように−層ごとに位
置ずらしを行いながら、5〜10に9/cdの圧力を加
えて順次複数枚積層し、所望の積層数を得た後、20〜
s o kg / ciの圧力で加圧を行い、所望の大
きさのチップに切断後、120σC〜1400℃で焼成
する。こうして得られた焼結体の両端部に現われる前記
内部電極に銀、銀−パラジウム等を塗布し、焼き付ける
ことによって外部電極を形成し、積層セラミックコンデ
ンサを製造している。
Next, apply a pressure of 9/cd to 5 to 10 while shifting the position of each layer so that the internal electrode layers sandwich the dielectric layers and alternately face each other. After laminating multiple sheets and obtaining the desired number of layers, 20~
Pressure is applied at a pressure of so kg/ci, and after cutting into chips of a desired size, they are fired at 120σC to 1400°C. Silver, silver-palladium, or the like is coated on the internal electrodes appearing at both ends of the sintered body thus obtained, and the external electrodes are formed by baking to manufacture a multilayer ceramic capacitor.

また、第6図は従来の積層セラミックコンデンサの外観
及び内部を示し、1は誘電体層、2は内部電極、3は外
部電極を示す。
Further, FIG. 6 shows the appearance and interior of a conventional multilayer ceramic capacitor, in which 1 is a dielectric layer, 2 is an internal electrode, and 3 is an external electrode.

発明が解決しようとする課題 しかしながら、前記のような構造では積層数が多くなる
に従い、内部電極を交互に対向させる際の位置合わせの
誤差が問題となり、内部電極層部分の位置ずれが顕著に
現われ、焼成後の素子において電気容量のバラツキを招
く原因となシ、積層セラミックコンデンサの製造におい
て大きな問題点となっている。
Problems to be Solved by the Invention However, in the structure described above, as the number of laminated layers increases, errors in positioning when the internal electrodes are alternately opposed become a problem, and misalignment of the internal electrode layer portions becomes noticeable. This is a major problem in the manufacture of multilayer ceramic capacitors, as it causes variations in capacitance in the fired elements.

さらに、もう一つの問題点として積層の際の位置ずらし
及び加圧によって、高積層の積層成形体の場合、第6図
に示すように内部電極2の重なシあった部分(以下、有
効電極部分と記す)の端部において、内部電極2の屈曲
が生じ、対向する内部電極2どうしがこの屈曲部分2&
で短絡し不良を招く場合が多くあった。
Furthermore, another problem is that due to displacement and pressure during lamination, in the case of a highly laminated laminate, as shown in FIG. The internal electrodes 2 are bent at the ends of the bent portions 2 and 2, and the opposing internal electrodes 2
There were many cases where short-circuiting occurred and caused defects.

そこで本発明は前記問題点に鑑み、積層による内部電極
の位置ずれや短絡のない高積層の積層セラミックコンデ
ンサ及びその製造方法を提供するものである。
In view of the above-mentioned problems, the present invention provides a highly laminated multilayer ceramic capacitor that is free from misalignment of internal electrodes and short circuits due to lamination, and a method for manufacturing the same.

課題を解決するための手段 前記問題点を解決するために本発明は、誘電体層と交互
に積層される個々の内部電極が外部電極を取出す両端部
にまで貫通し、前記両端部に釦いて前記内部電極が交互
に一層おきに絶縁処理を施された上に前記両端部に外部
電極を設けてなるという構成を備えたものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a structure in which the individual internal electrodes alternately laminated with dielectric layers penetrate to both ends from which the external electrodes are taken out, and buttons are attached to both ends. The internal electrodes are alternately insulated every other layer, and external electrodes are provided at both ends.

作用 本発明は前記した構成によって、従来の製造方51、 法におけるグリーンシートの位置ずらしの工程が省略さ
れるため、内部電極の位置ずれは一切問題では々くなジ
、また内部電極全面が有効電極となるため、第6図に示
した有効電極部分の端部での短絡は防止され、同時に有
効電極部分の大幅な面積の増大によって従来通9の積層
数でより大きi電気容量を得ることが可能である。
Effects of the present invention With the above-described configuration, the step of shifting the position of the green sheet in the conventional manufacturing method 51 is omitted, so there is no problem with misalignment of the internal electrodes, and the entire surface of the internal electrodes can be used effectively. Since it becomes an electrode, a short circuit at the end of the effective electrode portion shown in FIG. 6 is prevented, and at the same time, a larger i-electric capacity can be obtained with the conventional number of laminated layers of 9 by greatly increasing the area of the effective electrode portion. is possible.

さらに、前記した構成において幅が−様な連続した棒状
の内部電極パターンを用いた場合、任意の長さで積層成
形体を切断することによって同一ロットの積層成形体か
ら様々な電気容量を持つ積層セラミックコンデンサを得
ることができる。つま9、切断位置によって電気容量を
任意に制御することが可能となるわけである。
Furthermore, when a continuous rod-shaped internal electrode pattern with a variable width is used in the above-described configuration, it is possible to cut the laminated molded product at an arbitrary length to create a laminated molded product with various capacitances from the same lot of laminated molded products. Ceramic capacitors can be obtained. The capacitance can be arbitrarily controlled by changing the cutting position of the tab 9.

実施例 以下、本発明の一実施例について図面を参照しながら説
明する。第1図は本発明の実施例における個々の内部電
極12が後述する外部電極13を取出す両端部にまで貫
通し、前記両端部においてこの内部電極12を両端部で
交互に一層おきに絶6ベ 縁皮膜14により絶縁処理を行った後に外部電極3を設
けてなるという構成を備えた積層セラミックコンデンサ
の断面を示したものである。第1図で11は誘電体層で
ある。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows that each internal electrode 12 in an embodiment of the present invention penetrates to both ends from which external electrodes 13 (to be described later) are taken out, and the internal electrodes 12 are connected alternately every other layer at both ends. This figure shows a cross section of a multilayer ceramic capacitor having a structure in which an external electrode 3 is provided after insulation treatment is performed using an edge film 14. In FIG. 1, 11 is a dielectric layer.

次に、その製造方法について詳述する。1ず、チタン酸
バリウムを主成分とする厚さ20μmの誘電体セラミッ
クグリーンシートと、パラジウムを主成分とする内部電
極ペースト(昭栄化学工業姪製 ML3724 )とを
用意し、電極幅I mW、長さ100111ff、隣接
する電極間隔が5朋であるスクリーン印刷版を用いて、
従来の方法により仮加圧10に9/dを加えながら、内
部電極12を印刷した誘電体セラミックグリーンシート
11aを第2図に示すように同じ位置において順次積層
を繰り返し、60層の積層成形体を作製し、最後に本加
圧として20kg/c11.3秒の条件でプレスを行っ
た。次に、得られた積層成形体を所望の大きさのチップ
に切断し、どのようにして得られたチップの外部電極を
塗布する側の端面を第3図に示すようにマスキングをし
、チタン酸バリウムをター7・\−7 ゲットとしてRFスパッタ法にょシー層おきに内部電極
12上に厚さ1000〜3000Aのチタン酸バリウム
膜を絶縁皮膜として形成し絶縁処理を施す。次に、残る
もう一方の端面で前記において絶縁処理を施さなかった
内部電極12を上述と全く同様の方法を用いて絶縁処理
を施した。第3図で15はマスク板、16はチップ外周
部を示す。
Next, the manufacturing method will be described in detail. 1. First, prepare a dielectric ceramic green sheet with a thickness of 20 μm mainly composed of barium titanate and an internal electrode paste (ML3724 manufactured by Shoei Kagaku Kogyo Meiko Co., Ltd.) mainly composed of palladium. Using a screen printing plate with a diameter of 100111ff and a distance between adjacent electrodes of 5 mm,
While applying a temporary pressure 10 of 9/d using a conventional method, dielectric ceramic green sheets 11a having internal electrodes 12 printed thereon are repeatedly laminated in the same position as shown in FIG. 2, thereby forming a 60-layer laminate molded product. was produced, and finally, pressing was performed under the conditions of 20 kg/c for 11.3 seconds as main pressurization. Next, the obtained laminated molded body is cut into chips of a desired size, and the end face of the obtained chip on the side where the external electrode is applied is masked as shown in Fig. 3, and titanium is coated. A barium titanate film with a thickness of 1000 to 3000 A is formed as an insulating film on the internal electrode 12 every other layer by RF sputtering using barium acid as a target, and an insulating treatment is performed. Next, the other remaining end surface of the internal electrode 12, which had not been subjected to the insulation treatment in the above, was subjected to the insulation treatment using the method completely similar to that described above. In FIG. 3, reference numeral 15 indicates a mask plate, and reference numeral 16 indicates a chip outer periphery.

こうして第1図に示すような両端の内部電極12が一層
おきに絶縁処理を施されたチップを途中350’Cで6
時間保持し、バインダを除去した後、1300°Cで2
時間焼成を行った。焼成後、得られた焼結体を素子5g
に対して純水400y/を内壁に80番のサンドペーパ
ーを張り付けたポットの中に入れ、ボールミル 面取りを行った後、市販の銀ペースト(福田金属箔粉工
業駁製 GM−104)を外部電極として塗布し、80
0’C,30分で焼付けを行い、積層セラミックコンデ
ンサとしての電気容量を測定した。
In this way, the internal electrodes 12 at both ends were insulated every other layer as shown in FIG.
After holding for an hour and removing the binder, it was heated to 1300°C for 2
Time firing was performed. After firing, the obtained sintered body was packed into 5g of elements.
Pour 400 y/m of pure water into a pot with No. 80 sandpaper pasted on the inner wall, and after chamfering with a ball mill, apply commercially available silver paste (GM-104, manufactured by Fukuda Metal Foil & Powder Industry Co., Ltd.) to the external electrode. Apply as 80
Baking was performed at 0'C for 30 minutes, and the capacitance as a multilayer ceramic capacitor was measured.

下記の表は従来の方法と本発明による方法との製造にお
いて、得られた積層セラミックコンデンサの電気容量を
設計値と比較した時の命中率と短絡による不良の状況を
それぞれ試料数1 000個に対して比較したものであ
り、本発明によって明らかに電気容量の命中率と短絡に
よる歩留シが向上していることがわかる。
The table below shows the hit rate and failure status due to short circuit when the capacitance of the obtained multilayer ceramic capacitors is compared with the design value in manufacturing using the conventional method and the method according to the present invention, and the number of samples is 1,000. It can be seen that the present invention clearly improves the accuracy of capacitance and the yield due to short circuits.

表 會た、第4図は従来の方法と本発明による方法とにおい
て一定の電気容量を得るために必要な積層数の違いを示
したものであり、明らかに本発明品は構造的に有効電極
面積が従来品と比べて大きいため、少ない積層数で大き
な電気容量を得るこ9 ・・−/ とができる点で有利であることがわかる。
Figure 4 shows the difference in the number of laminated layers required to obtain a certain capacitance between the conventional method and the method according to the present invention, and it is clear that the product according to the present invention is a structurally effective electrode. It can be seen that since the area is larger than that of conventional products, it is advantageous in that a large electrical capacity can be obtained with a small number of laminated layers.

以上のように本実施例によれば、積層セラ□ツクコンデ
ンサの個々の内部電極が外部電極を取出す両端部にまで
貫通し、前記両端部においてこの内部電極を両端部で交
互に一層おきに絶縁処理を施された上に外部電極を設け
てなることによって、内部電極の位置ずれを解消し、電
気容量の命中率を向上させることができ、さらに内部電
極の短絡による不良を改善することができる。また、本
発明品は積層セラミックコンデンサの電気容量を構造の
面から大幅に増大させるための有効な手段であることが
証明された。
As described above, according to this embodiment, the individual internal electrodes of the multilayer ceramic capacitor penetrate to both ends from which the external electrodes are taken out, and the internal electrodes are alternately insulated every other layer at both ends. By providing an external electrode on top of the processed material, it is possible to eliminate misalignment of the internal electrode, improve the accuracy of capacitance, and further improve defects caused by short circuits in the internal electrode. . Furthermore, the product of the present invention has been proven to be an effective means for significantly increasing the capacitance of a multilayer ceramic capacitor from a structural standpoint.

尚、本実施例では内部電極の絶縁処理にスパッタリング
法を用いたが、真空蒸着法によっても同様の効果が得ら
れることを確認した。
In this example, sputtering was used to insulate the internal electrodes, but it was confirmed that the same effect could be obtained by vacuum evaporation.

発明の効果 以上のように本発明は、積層セラミックコンデンサの個
々の内部電極が外部電極を取出す両端部にまで貫通し、
前記両端部においてこの内部電極を両端部で交互に一層
おきに絶縁処理を施された0 1 上に外部電極を設けてなることによって、内部電極の位
置ずれの問題を解消し、電気容量の命中率を向上させ、
同時に内部電極の短絡による不良を改善し、さらに積層
セラミックコンデンサの電気容量を構造の面から増大さ
せるための有効な手段であり、今後の積層セラミックコ
ンデンサの製造に画期的な効果をもたらすものである。
Effects of the Invention As described above, the present invention provides a structure in which each internal electrode of a multilayer ceramic capacitor penetrates to both ends from which the external electrode is taken out.
By providing an external electrode on top of the internal electrodes, which are insulated alternately at every other layer at both ends, the problem of misalignment of the internal electrodes can be solved and the accuracy of the capacitance can be improved. improve the rate,
At the same time, it is an effective means for improving defects caused by short circuits in internal electrodes and increasing the capacitance of multilayer ceramic capacitors from a structural standpoint, and will bring revolutionary effects to the manufacturing of multilayer ceramic capacitors in the future. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の個々の内部電極が外部電極を
取出す両端部にまで貫通し、前記両端部においてこの内
部電極を両端部で交互に一層おきに絶縁処理力(施され
た上に外部電極を設けてなる積層セラミックコンデンサ
の断面を示す説明図、第2図は本発明において積層の様
子を説明するための図、第3図は本発明において端部に
現われた内部電極に絶縁処理を施す際のマスキングの様
子を説明するための図、第4図は従来の方法と本発明に
よる方法とにおいて一定の電気容量を得るために必要な
積層数の違いを説明するための図、第6図は従来の積層
セラミックコンデンサの構造を11 一部を切欠して示す図、第6図は同有効電極部分の端部
での内部電極の屈曲を説明する図である。 11・・・・・・誘電体層、11a・・・・・・誘電体
層う□ンクグリーンシート、12・・・・・・内部電極
、13・・・・・・外部電極、14・・・・・・絶縁皮
膜。
FIG. 1 shows that the individual internal electrodes of the embodiment of the present invention penetrate to both ends from which the external electrodes are taken out, and that the internal electrodes are insulated alternately at every other layer at both ends. FIG. 2 is a diagram for explaining the state of lamination in the present invention, and FIG. 3 is an explanatory diagram showing a cross section of a multilayer ceramic capacitor in which an external electrode is provided at the end of the capacitor. FIG. 4 is a diagram for explaining the state of masking during processing, and FIG. 4 is a diagram for explaining the difference in the number of laminated layers required to obtain a constant capacitance between the conventional method and the method according to the present invention. Fig. 6 is a partially cutaway view showing the structure of a conventional multilayer ceramic capacitor, and Fig. 6 is a view illustrating the bending of the internal electrode at the end of the effective electrode portion. ...Dielectric layer, 11a... Dielectric layer □ Green sheet, 12... Internal electrode, 13... External electrode, 14... Insulating film.

Claims (2)

【特許請求の範囲】[Claims] (1)誘電体層と交互に積層される個々の内部電極が外
部電極を取出す両端部にまで貫通し、前記両端部におい
て前記内部電極が交互に一層おきに絶縁処理を施された
上に前記両端部に外部電極を設けてなることを特徴とす
る積層セラミックコンデンサ。
(1) The individual internal electrodes alternately laminated with dielectric layers penetrate to both ends from which external electrodes are taken out, and at both ends, the internal electrodes are alternately insulated every other layer, and A multilayer ceramic capacitor characterized by having external electrodes at both ends.
(2)誘電体セラミックグリーンシート上に連続した棒
状のパターンで内部電極を形成し、このシートを交互に
位置ずらしを行うことなく同じ位置において積層し、得
られた積層成形体を所望の大きさのチップに切断後、両
端部に現われる内部電極についてまず一方の内部電極は
一層おきにスパッタリング等によって絶縁処理を行い、
他方の内部電極は短絡を避けるため前記において絶縁処
理を行わなかった内部電極を一層おきにスパッタリング
等によって絶縁処理を行った後に焼成し、その後両端部
に外部電極を設けたことを特徴とする積層セラミックコ
ンデンサの製造方法。
(2) Internal electrodes are formed in a continuous rod-like pattern on dielectric ceramic green sheets, and the sheets are laminated at the same position without shifting the positions alternately, and the resulting laminated molded product is shaped into the desired size. After cutting into chips, one of the internal electrodes that appears at both ends is insulated by sputtering etc. every other layer.
The other internal electrode is a laminated layer characterized in that the internal electrodes that were not insulated in the above are insulated by sputtering or the like every other layer in order to avoid short circuits, and then fired, and then external electrodes are provided at both ends. Method of manufacturing ceramic capacitors.
JP22769489A 1989-09-01 1989-09-01 Laminated ceramic capacitor and manufacture thereof Pending JPH0391217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22769489A JPH0391217A (en) 1989-09-01 1989-09-01 Laminated ceramic capacitor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22769489A JPH0391217A (en) 1989-09-01 1989-09-01 Laminated ceramic capacitor and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0391217A true JPH0391217A (en) 1991-04-16

Family

ID=16864882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22769489A Pending JPH0391217A (en) 1989-09-01 1989-09-01 Laminated ceramic capacitor and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0391217A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170736A (en) * 2000-11-29 2002-06-14 Kyocera Corp Laminated electronic component and its manufacturing method
JP4573956B2 (en) * 2000-06-30 2010-11-04 京セラ株式会社 Multilayer electronic component and manufacturing method thereof
JP2013187537A (en) * 2012-03-05 2013-09-19 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4573956B2 (en) * 2000-06-30 2010-11-04 京セラ株式会社 Multilayer electronic component and manufacturing method thereof
JP2002170736A (en) * 2000-11-29 2002-06-14 Kyocera Corp Laminated electronic component and its manufacturing method
JP2013187537A (en) * 2012-03-05 2013-09-19 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component and method of manufacturing the same

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