JPH0387021A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable diffused layers having specified impurity profiles to be formed in excellent controllability by a method wherein the atmosphere is controlled so as to diffuse the impurity from a silicon oxide layer containing the impurity to a semiconductor layer. CONSTITUTION:Element isolation films 2, a gate insulating film 3 and a gate electrode 4 are formed and then resist films 6 and silicon nitride films 5a, 5b are formed. Furthermore, an arsenic-added doped glass 8 is deposited and then heat-treated in the atmosphere of nitrogen firstly containing 10% of hydrogen and secondly 100% of nitrogen. Next, arsenic is shallowly diffused to form source.drain regions comprising n<->, n<+> diffused layers 9, 10. Then, interlayer insulating films 11, barrier metals 12 and wiring layers 13 are formed by heat treatment in reducing atmosphere for a long time at slightly lower temperature. Through these procedures, the diffused layers having specified impurity profiles can be formed in excellent controllability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device that improves the method of introducing impurities.

(Prior Art) In recent years, in semiconductor integrated circuits, elements have become increasingly finer and their densities have continued to increase. However, miniaturization of element dimensions is approaching its limit, and it is becoming difficult to improve the performance and reliability of even higher-density integrated circuits simply by miniaturizing element dimensions.

Therefore, methods have been adopted in which a trench is dug in the surface of a semiconductor substrate or a semiconductor layer, an insulating layer, a metal layer, etc. are laminated to form an element with a three-dimensional structure.

For example, in a MOS capacitor, which is a component of a dynamic RAM (DRAM), by digging a trench on the surface of a silicon substrate and forming a capacitor within this trench, the capacitance can be substantially increased without increasing the occupied area. This method is being considered. However, in order to improve the reliability of the capacitor against breakdown over time, it is necessary to differentiate the memory contents by setting the potential of the upper electrode to OV and 5V. A method has been adopted in which an impurity diffusion layer having a concentration higher than that is formed.

By the way, in the case of DRAM, since a large number of cells are arranged, there is a problem that when increasing the density, the separation voltage between the impurity diffusion layers of the capacitor formed in the structure decreases as the distance between the grooves becomes shorter. .

To solve this problem, for example, when forming an n-type impurity diffusion layer on the groove surface of a p-type substrate, under the impurity diffusion layer on the groove surface, a p-type impurity diffusion layer with a slightly higher concentration than the substrate concentration is added. layer, forming a double diffusion layer or the so-called Hi
The method used is to create a C structure. It is also known that this HiC structure has strong soft error resistance when the capacitance is reduced.

However, it is extremely difficult to accurately form a double diffusion layer on the surface of a trench, and the general ion implantation method is difficult to ensure uniformity of concentration at the bottom and sidewalls of the trench. In addition, when diffusing from a silicon oxide film containing impurities called doped glass, it is easy to ensure uniformity of the concentration between the bottom and sidewalls, but There was a problem in that the peeling process had to be repeated, resulting in a significant increase in the number of processes.

In addition, the technology of forming doped glass containing multiple impurities and diffusing impurities from this doped glass can be expected to simplify the process, but at the current level of technology, multiple impurities can be simultaneously mixed into a desired profile with good controllability. It is extremely difficult to diffuse and has not yet been put to practical use.

Furthermore, not only the case where doped glass containing a plurality of impurities as described above is used, but also impurity diffusion technology from doped glass is considered to be a method that does not have controllability in reality.

For this reason, it is considered impossible to form a semiconductor device having a double diffusion layer on the groove surface.

(Problem to be Solved by the Invention) As described above, it has been practically impossible to form a double diffusion layer on the groove surface with good controllability.

Furthermore, not only in the case of DRAMs, impurity diffusion techniques from silicon oxide containing a plurality of impurities have until now been considered to be uncontrollable methods.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for easily forming a diffusion layer with good controllability when diffusing impurities from a silicon oxide layer containing impurities to a semiconductor layer. .

[Structure of the Invention] (Means for Solving the Problems) Therefore, in the present invention, when diffusing impurities from a silicon oxide layer containing impurities to a semiconductor layer, specific impurities are oxidized or reduced by controlling the diffusion atmosphere. In this way, the diffusion coefficient of impurities in the silicon oxide layer is controlled.

(Function) By the way, doped glass, which is called a diffusion source, usually contains C.
Although it is formed by a VD method or a spin coating (so-called 5OG) method, the contained impurities are thought to be in various chemical states depending on the formation method and formation conditions.

The chemical state of such dopant impurities will greatly influence the diffusion behavior of the dopant in the glass.

For example, we used arsenic as a dopant impurity and investigated the diffusion behavior of arsenic in doped glass. As a result,
They found that in the oxidized state, where arsenic is bonded to oxygen atoms in the silicon oxide network, diffusion in the doped glass is very fast, whereas in the reduced state, diffusion in the doped glass is very slow.

It has been found that this phenomenon is not limited to arsenic, but also occurs with other dopant impurities. moreover,
It was also found that the rate at which these impurities diffuse through the substrate after reaching the substrate interface does not vary much depending on the type of impurity.

The present invention was made with attention to this point, and by controlling the diffusion atmosphere during heat treatment, the dopant in the doped glass is reduced or oxidized, thereby controlling its diffusion behavior, and achieving the desired result. It becomes possible to introduce dopants into the semiconductor layer with precise control over the concentration and depth of dopants.

In addition, when doped glass containing multiple impurities is used, by selecting the diffusion atmosphere, it is possible to selectively promote the diffusion of a specific dopant impurity and suppress the diffusion of other dopant impurities. becomes.

In addition, by changing the diffusion atmosphere during heat treatment, the diffusion of a specific dopant is promoted for a certain period of time.
It is then possible to suppress the process for a certain period of time or vice versa, and it is also possible to form a diffusion layer with a specific concentration profile.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(d) show manufacturing steps for forming extremely thin n'' and n- type diffusion layers as the source/drain regions of MOSFETs using the method of the embodiment of the present invention. FIG.

First, as shown in FIG. 1(a), a normal LOCOS
The element isolation insulating film 2 is formed by a thermal oxidation method, and a silicon oxide layer with a thickness of 10n1 and a silicon oxide layer with a thickness of 30nm are formed by a thermal oxidation method.
A 0 nm polycrystalline silicon film is deposited and patterned by photolithography and reactive ion etching to form gate insulating film 3 and gate electrode 4.

After this, as shown in FIG. 1(b), a silicon nitride film is formed on the entire surface of the substrate, and a resist film is further applied and a normal patterning process is performed to form a resist film 6 as an etching mask only in the element isolation region. After leaving the remaining silicon nitride film 5a, the silicon nitride film 5a in the area covered with the resist film 6 and the silicon nitride film 5b in the side wall portion of the gate electrode are removed by reactive ion etching.

Then, the resist film 6 is removed, and LPGVD (low pressure CVD) is applied.
D) 6×1O20cI of arsenic with a film thickness of 1100n using method
11-3 doped glass 8 is deposited.

Then, as shown in Fig. 1(C), a heating device using a lamp was used to heat the product in a nitrogen atmosphere containing 10% hydrogen.
After heat treatment at 000℃ for 60 minutes, an additional 100℃
% 1200°C in a nitrogen atmosphere.

Rapid heating treatment for 2 minutes (RT A: Rapid T
arsenic is diffused extremely shallowly into silicon from the doped glass 8 to form source/drain regions of an LDD structure consisting of an n- diffusion layer 9 and an n-diffusion layer 10. Here, by performing heat treatment in a reducing atmosphere at a slightly low temperature for a long time, diffusion of arsenic from within the silicon oxide film is suppressed, and arsenic is diffused slightly deeply at a low concentration to form the n- diffusion layer 9. After this, by using high temperature heat treatment with a high solid solution concentration of arsenic in silicon, a high concentration arsenic diffusion layer is formed on the silicon surface, thereby increasing the arsenic concentration I x 10
A high concentration and shallow n-diffusion layer 10 with a 20cm-3 arsenic diffusion depth of 0.07 μm and a relatively low-concentration and deep n-diffusion layer 9 with an arsenic concentration of lXl0 cm and an arsenic diffusion depth of 0.1 μm. It becomes possible to form a step-like shape.

Thereafter, the doped glass 8 to which arsenic has been added is removed by etching with diluted hydrofluoric acid, an interlayer insulating film 11 is deposited, and then contact holes for wiring are formed.

Thereafter, as shown in FIG. 1(d), barrier metal 12 and lead-out wiring 13 are formed by a known method to complete the MOS transistor.

The arsenic concentration profile of the n-diffusion layer and n-diffusion layer thus formed is shown in FIG. 2(a). For comparison, a conventional method was used at 1200℃ in a nitrogen atmosphere for 2 hours.
Phosphorus and arsenic in the n- diffusion layer (phosphorus) and n+ diffusion layer (arsenic) when the phosphorus and arsenic are diffused from the silicon oxide layer containing phosphorus and arsenic into the silicon substrate by performing high-speed heat treatment for 30 minutes. The concentration profile of
Shown in Figure (b).

As is clear from these comparisons, according to the embodiments of the present invention, it is possible to form shallower n- and n+ diffusion layers.

Further, FIG. 3 shows the results of measuring the chemical bonding state of arsenic in the doped glass by X-ray excited electron spectroscopy (XPS). In the figure, the horizontal axis indicates binding energy. Curve a is
The chemical bonding state of arsenic is shown when heat treatment is performed for 4 hours in a nitrogen atmosphere at 1000℃, and the curve is 1000℃.
The chemical bonding state of arsenic is shown when heat treatment is performed for one hour in a nitrogen atmosphere containing 10% hydrogen. As can be seen from this figure, in the case of curve a, arsenic remains in an oxidized state, whereas in the case of curve a, arsenic is in a reduced state.

In the above embodiments, the case where impurities are introduced into a silicon substrate has been described, but it is not limited to a silicon substrate, and can be applied to any substrate, thin film, single crystal, polycrystalline, or amorphous silicon. Needless to say, semiconductors other than silicon may be used.

Further, in the above embodiments, the case where diffusion is performed in an atmosphere containing hydrogen has been described, but the diffusion is not limited to an atmosphere containing hydrogen as long as the desired impurities can be reduced.

Further, in the above embodiment, only arsenic was used as an impurity to form a diffusion layer with a stepped concentration profile, but it is also possible to apply impurities other than arsenic, or to combine multiple types of impurities. You may also use it.

Next, as a second embodiment of the present invention, a case will be described in which a trench type MOS capacitor with a HiC structure is formed in a silicon substrate.

FIG. 14(a) to FIG. 4(d) are process cross-sectional views showing the manufacturing process when forming a trench type MOS capacitor using the method of the embodiment of the present invention.

First, as shown in FIG. 4(a), a normal LO
An element isolation insulating film 22 is formed by the COS method, and further,
After depositing a silicon oxide layer 23 to serve as a mask when forming grooves by CVD method, these are patterned by photolithography and reactive ion etching, and using this silicon oxide layer as a mask, carbon tetrachloride CC14 is used as the main component. Grooves 24 are formed by reactive ion etching using etching gas.

Thereafter, as shown in FIG. 4(b), the masking silicon oxide layer 23 is removed by etching with diluted hydrofluoric acid.
Example Eva, film thickness 10 by LPGVD (low pressure CVD) method
A doped glass 25 doped with 0.0 cm of boron and 0-3 of arsenic at 2.times.10 ctn 6.times.10.sup.20 cm.sup.-3 is deposited. Then, heat treatment is performed at 1000° C. for 60 minutes in a nitrogen atmosphere containing 10% hydrogen using a normal heat diffusion furnace to reduce arsenic in the doped glass 25, suppress its diffusion, and reduce the arsenic in the doped glass 25. By selectively diffusing only unreduced boron from the doped glass into the silicon substrate, P-
A region 26 is formed on the surface.

Furthermore, as shown in FIG. 4(C), the temperature is raised to 900° C. and the atmosphere is changed to nitrogen containing 10% oxygen to oxidize the arsenic in the doped glass 25 again and make it easy to diffuse. , further increase the temperature by 1
By raising the temperature to 000°C, switching to a nitrogen atmosphere, and performing heat treatment for 30 minutes, arsenic and boron are simultaneously diffused from the doped glass into the silicon substrate, and the n+ region 27
and forming a double diffusion layer of the P- region 26.

Furthermore, as shown in FIG. 4(d), the doped glass 25 containing arsenic and boron is removed by etching with diluted hydrofluoric acid, and then heated to 900"C in a 50% dry atmosphere diluted with argon gas to form a capacitor. A silicon oxide film 28 with a thickness of 10 nm is formed as an insulating film, and a plate electrode 29 made of a phosphorus-doped polycrystalline silicon layer is further formed on top of this to complete a trench type MOS capacitor.

In this way, a trench type MOS capacitor is formed at 1000°C in a nitrogen atmosphere containing 10% hydrogen.
Heat treatment was performed for 60 minutes to reduce arsenic in the doped glass 25, suppress its diffusion, and keep it in the doped glass, while only boron was selectively diffused from the doped glass into the silicon substrate (Figure 4(b)). ) is shown in FIG. 5(a).

Moreover, FIG. 5(b) shows the dopant impurity profile after switching to a nitrogen atmosphere and performing heat treatment for 30 minutes (FIG. 4(C)). In these cases, from the impurity profile shown in FIG. 5(a), arsenic in the doped glass 25 is reduced in a nitrogen atmosphere containing 10% hydrogen, its diffusion is suppressed, it remains in the doped glass, and only boron is selectively It can be seen that the doped glass is diffused into the silicon substrate. Furthermore, from the dopant impurity profile in FIG. 5(b), arsenic is oxidized again by heat treatment in an oxygen-containing atmosphere, and arsenic is diffused into the silicon substrate 21 together with boron by subsequent heat treatment in a nitrogen atmosphere. A good double diffusion layer of region 27 and P region 26 is formed.

It can be seen that by the method of the present invention, a plurality of dopant impurity diffusion layers having complex shapes can be formed with good controllability through a simple process.

In this example, the atmosphere is changed in the following order: an atmosphere that reduces impurities, an atmosphere that oxidizes impurities, and an atmosphere that does not reduce impurities, but these orders can be changed as necessary.

Next, FIGS. 6(a) to 6(d) are sectional views showing the manufacturing process of a trench capacitor according to the third embodiment method of the present invention. First, as shown in FIG. 6(a), a trench groove is cut in the p-type wheel crystal silicon substrate 1 using a well-known process. Next, as shown in Figure 6(b), low pressure chemical vapor deposition (LPCV) was performed at 700°C using TE01 (tetraethoxysilane) and TEB (triethylborate) as raw materials.
D) silicon glass containing boron on its surface (BSG: B concentration - 6X10"toIls 3/
cm) Form a film 81. At this time, when the BSG film 8□ reached a thickness of 3 nm, arsenic was added using TEOA (triethoxyarsine) as a raw material (BAsSG: Ba degree -6 × 1
019at01183/cm As concentration -5×1o20atoms 3 /Cl0), BAsSG film 8S and gold film 00na+ are deposited on top of this film.

Next, a dopant is diffused into the silicon substrate 1. First, in order to suppress the diffusion of As in the silicon oxide film and diffuse B, the As is reduced by annealing in a hydrogenated inert gas at 900° C. for 1 hour. , 1 in hydrogenated inert gas
Diffusion for 4 hours at 000°C. Next, in order to diffuse As, oxidation is performed at 900° C. for 1 hour in an oxidizing atmosphere, and then diffusion is performed again at 1000° C. for 20 minutes in nitrogen.

Through these diffusion steps, the thickness of the BSG film 81 can be reduced, and a decrease in the surface concentration of As in the silicon substrate 1 can be prevented. By the above method, n is formed in the silicon substrate 1.
A dopant (As) layer 10 and a p-dopant (B) layer 26 can be formed. After this, BSG film 8 and BAsSG
Peel off with Membrane 8S heavy film acid, etc. (Figure 6(C)).

Thereafter, an ONO film 3 is formed on the inner surface of the trench by a well-known method, and an electrode 4 is embedded and patterned to complete the capacitor (FIG. 6(d)).

It was formed by the above diffusion method. The impurity profile of the capacitor is shown in FIG. 7(b). As is clear from this figure, although B diffuses to a depth of 500 inches, As diffuses only to a shallow depth of 80 mm, achieving an ideal profile. For comparison, the impurity profile when B and As are similarly diffused from the BAsSG film layer into the silicon substrate is shown in the seventh column.
Shown in Figure (a). From this figure, it can be seen that the diffusion depth of B is insufficient for diffusion from the − layer, and As is formed deeper than 100 mm from the surface, and as a result, the difference in the diffusion depth of B and As becomes smaller, making it ideal. It won't be.

Further, FIG. 7(C) shows an impurity profile when a capacitor is formed by changing the thermal diffusion conditions of the third embodiment. The difference from the third example is that the heat treatment time in the H2-added atmosphere ranged from 4 hours to 2.5 hours (represented by a solid line).
The reason is that I changed it.

First, as a result of comparing the depth of B in FIG. 7(b) with a heat treatment time of 4 hours and B in FIG. 7(e) with a heat treatment time of 2.5 hours, we found that the heat treatment in this H2-added atmosphere It was found that by shortening the time, only the diffusion of B could be shallowly controlled.

In addition to the heat treatment time, the BSG film was changed from 311I11 to 2
Figure 7 (C
) are overlaid with broken lines. From this figure, it was found that by making the BSG film thinner, the As diffusion depth could be deeply controlled. This is because the time it takes for As to reach the Si substrate is delayed. From the above, the diffusion depth of each impurity of B and As can be controlled independently by changing the heat treatment time in a reducing atmosphere for B, and by changing the thickness of the BSG film for As. It turned out that it is possible.

In addition, the combination of the above BAsSG film and BSG film is
It may be changed to a combination of SG film and BSG film. Further, in this embodiment, B and As are used, but other dopants such as p and sb may be used. Further, although this embodiment shows an example in which two types of dopants are introduced, it is also possible to include three or more types of dopants. Moreover, a laminated film having not only two layers but three or more layers may be used.

As detailed above, according to this embodiment, by forming the solid-phase diffusion source film into multiple layers, it becomes possible to control the thicknesses of the dopant diffusion layers diffused into a plurality of silicon substrates at the same time. This is effective in increasing the reliability of the semiconductor device and simplifying the manufacturing process.

The present invention is not limited to the above embodiments, but may be modified as follows.

■ As in the above-mentioned embodiment, the surface of the doped glass may be exposed to a reducing or oxidizing atmosphere during thermal diffusion in order to reduce or oxidize the dopant impurities in the doped glass. After removing this atmosphere, the thermal diffusion process may be performed again with the doped glass surface exposed to nitrogen or an inert gas. Dopant impurities can also be reduced or oxidized by such a process.

■ Heat treatment was performed once in each atmosphere, but
You can go as many times as you like.

(2) In the above embodiment, the case where the atmosphere is changed within the same device has been described, but a different device may be used each time the atmosphere is changed.

(2) The reducing atmosphere is not limited to N2, but may also be other hydrogen-containing substances such as silane, diborane, or a mixed gas of these and an inert gas such as N2 or Ar.

(2) In addition to 02, the oxidizing atmosphere may be a simple substance containing oxygen, such as HO, or a mixed gas of these and an inert gas such as N2 or Ar.

③ The substrate is not limited to St, but may also be other group Ⅰ semiconductors such as diamond, Ge, or compound semiconductors such as GaA.
Furthermore, it can be applied to SOS, SOI substrates, etc.

[Effects of the Invention] As explained above, according to the method of the present invention, when the impurity is diffused from the silicon oxide layer containing impurities to the semiconductor layer, specific impurities are oxidized or reduced. Since the diffusion coefficient of impurities therein is controlled, it is possible to form a diffusion layer having a desired impurity profile with extremely good controllability.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are MOSs according to embodiments of the present invention.
Figure 2(a) shows the impurity profile of the impurity diffusion layer of the MOSFET formed by the method shown in Figure 1. Figure 2(b) shows the manufacturing process of the FET. Figure 3 shows the impurity profile of the impurity diffusion layer of the formed MOSFET, Figure 3 shows the results of measuring the chemical bonding state of arsenic in doped glass by X-ray excited electron spectroscopy, Figures 4 (a) to 4. FIG. 4(d) is a diagram showing the manufacturing process of a MOS capacitor according to the second embodiment of the present invention, and FIG. 5(a) is an impurity profile of the diffusion layer formed in the process shown in FIG. 4(b). FIG. 5(b) is a diagram showing the impurity profile of the diffusion layer formed in the step shown in FIG. 4(e), FIG. 6 is a diagram showing the third embodiment of the present invention, FIG. 7 is a diagram illustrating a third embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Element isolation insulating film, 3... Gate insulating film, 4... Gate electrode, 5a,
5b...Silicon nitride film, 6...Resist film, 8.
...Doped glass, 9...n-diffusion layer, 10...
n+ diffusion layer, 11... interlayer insulating film, 12... barrier metal, 13... wiring layer, 21... silicon substrate,
22... Element isolation insulating film, 23... Silicon oxide layer, 24... Groove, doped glass, 26... P- region, 27... N+ region 28... Silicon oxide film, 2
9...Plate electrode.

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device including a step of diffusing impurities from a silicon oxide layer containing impurities into a semiconductor layer, in which the diffusion step is performed by controlling a diffusion atmosphere to diffuse specific impurities in the silicon oxide layer. A method for manufacturing a semiconductor device, comprising an oxidation step for oxidation or a reduction step for reduction. (2) The silicon oxide layer is formed to include a plurality of impurities, one of which has a different concentration in the thickness direction of the silicon oxide layer, and then the impurity is diffused from the silicon oxide layer. The method for manufacturing a semiconductor device according to claim (1).