JPH038373A - Vertical type field-effect transistor - Google Patents
Vertical type field-effect transistorInfo
- Publication number
- JPH038373A JPH038373A JP1144910A JP14491089A JPH038373A JP H038373 A JPH038373 A JP H038373A JP 1144910 A JP1144910 A JP 1144910A JP 14491089 A JP14491089 A JP 14491089A JP H038373 A JPH038373 A JP H038373A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- surge
- mosfet
- diode
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 17
- 230000015556 catabolic process Effects 0.000 claims abstract description 22
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 23
- 238000000034 method Methods 0.000 description 11
- 238000010521 absorption reaction Methods 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は縦型電界効果トランジスタの特性改善に関し特
に、ドレイン・ソース間に印加されたサージに対し破壊
耐量を大幅に向上できる縦型電界効果トランジスタに関
する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to improving the characteristics of vertical field effect transistors, and particularly relates to improving the characteristics of vertical field effect transistors, and particularly relates to the improvement of vertical field effect transistors that can significantly improve breakdown resistance against surges applied between the drain and source. Regarding transistors.
従来、この種の縦型電界効果トランジスタは、ドレイン
・ソース間に印加されたサージを吸収するためＭＯＳＦ
ＥＴのセル領域の外側にダイオードを形成した縦型電界
効果トランジスタがある。Conventionally, this type of vertical field effect transistor uses a MOSFET to absorb surges applied between the drain and source.
There is a vertical field effect transistor in which a diode is formed outside the cell region of the ET.
第３図（ａ）は従来の縦型電界効果トランジスタの平面
図である。第３図（ａ）に於てサージ吸収用ダイオード
１はＭＯＳＦＥＴのセル領域２の外側に形成され、ゲー
トパット３．ゲートパット−４、ソースパット５の下部
にも形成される場合がある。FIG. 3(a) is a plan view of a conventional vertical field effect transistor. In FIG. 3(a), a surge absorbing diode 1 is formed outside the cell region 2 of the MOSFET, and a gate pad 3. It may also be formed under the gate pad 4 and the source pad 5.
第３図（ｂ）は第３図（ａ）のＸ−Ｘに沿った縦断面図
である。サージ吸収用ダイオード１９のアノード層９は
ＭＯＳＦＥＴのＰイー３層１０と同時あるいはＰイー３
層１０の形成に先立って形成される。FIG. 3(b) is a longitudinal sectional view taken along the line XX in FIG. 3(a). The anode layer 9 of the surge absorbing diode 19 is formed at the same time as the PE3 layer 10 of the MOSFET or at the same time as the PE3 layer 10 of the MOSFET.
It is formed prior to the formation of layer 10.
ドレイン・ソース間耐圧が３０Ｖを超える場合、ドレイ
ン・ソース間耐圧は主にＮ−ドレイン８の抵抗率及び厚
さにより決まるため、ＭＯＳＦＥＴ部の耐圧とサージ吸
収用ダイオード１９の耐圧はほぼ同程度となる。ドレイ
ン・ソース間耐圧が約８０Ｖの場合Ｎ−ドレイン８の抵
抗率は約１Ω口（５Ｘ １０ ”／ｄ）、厚さは約１２
μｍである。When the drain-source breakdown voltage exceeds 30V, the drain-source breakdown voltage is mainly determined by the resistivity and thickness of the N-drain 8, so the breakdown voltage of the MOSFET section and the surge absorption diode 19 are approximately the same. Become. When the drain-source breakdown voltage is about 80V, the resistivity of N-drain 8 is about 1Ω (5×10”/d), and the thickness is about 12
It is μm.
上述した従来技術の縦型電界効果トランジスタではサー
ジ吸収用ダイオード１９とＭＯ８ＦＥＴ２０の耐圧がほ
ぼ等しいので、ドレイン・ソース間にサージが印加され
た場合、サージ吸収用ダイオード１９とＭＯ８ＦＥＴ２
０のブレークダウンがほぼ同時に起こり、ブレークダウ
ン電流がＭＯ８ＦＥＴ２０にも流りてしまい、ＭＯ８Ｆ
ＥＴ２０に寄生的に存在するバイポーラトランジスタ２
１がターンオンン破壊しやすいという欠点がある。In the conventional vertical field effect transistor described above, the surge absorption diode 19 and the MO8FET 20 have approximately the same breakdown voltage, so when a surge is applied between the drain and source, the surge absorption diode 19 and the MO8FET 2
0 breakdown occurs almost simultaneously, the breakdown current also flows to MO8FET20, and MO8F
Bipolar transistor 2 parasitically present in ET20
The drawback is that 1 is easily destroyed on turn.
なお、通常フレークダウン電流工、による電圧降下（Ｒ
１１（ベース抵抗）ＸＩＢ）が約０．６ｖを超えるとバ
イポーラトランジスタ２１がターンオンンてしまう。バ
イポーラトランジスタは熱暴走に対し正の温度係数を持
つため１個のＭＯ８ＦＥＴセルで寄生バイポーラトラン
ジスタがターンオンンてしまうと電流集中、熱暴走が起
こり破壊してしまう。Note that the voltage drop (R
11 (base resistance) XIB) exceeds about 0.6V, the bipolar transistor 21 turns on. Bipolar transistors have a positive temperature coefficient against thermal runaway, so if a parasitic bipolar transistor is turned on in one MO8FET cell, current concentration and thermal runaway occur, resulting in destruction.
〔課題を解決するための手段〕
本発明の縦型電界効果トランジスタは、ＭＯＳＦＥＴの
セル領域の外側にＭＯＳＦＥＴのブレークダウン耐圧よ
りは低いサージ吸収用ダイオードを有している。[Means for Solving the Problems] The vertical field effect transistor of the present invention includes a surge absorbing diode having a breakdown voltage lower than the breakdown voltage of the MOSFET outside the cell region of the MOSFET.
本発明においては、ＭＯＳＦＥＴのセル領域の外側のサ
ージ吸収用ダイオード形成領域のドレイン表面の濃度を
高くすることによりサージ吸収用ダイオードの耐圧をＭ
ＯＳＦＥＴの耐圧よりも低くしている。従って、ドレイ
ン・ソース間に印加されたサージによるブレークダウン
電流が主にサージ吸収用ダイオードに流れ、ＭＯＳＦＥ
Ｔに流れないためサージ破壊耐量が大幅向上するという
相違点を有する。In the present invention, the withstand voltage of the surge absorbing diode is increased by increasing the concentration on the drain surface of the surge absorbing diode forming region outside the cell region of the MOSFET.
It is lower than the withstand voltage of OSFET. Therefore, the breakdown current due to the surge applied between the drain and source mainly flows to the surge absorption diode, and the MOSFE
The difference is that the surge breakdown resistance is greatly improved because it does not flow into the T.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の一実施例の平面図である。サー
ジ吸収用ダイオード１はセル領域２の外側の部分にのみ
形成される。FIG. 1(a) is a plan view of one embodiment of the present invention. The surge absorbing diode 1 is formed only outside the cell region 2.
第１図（ｂ）は第１図（ａ）のＹ−Ｙに沿った縦断面図
である。サージ吸収用ダイオード２２はＭＯ３ＦＥＴ２
０よりも耐圧を低くするためＰウェル層９の外側６に於
てＮ−ドレイン８の表面部２１をリンの拡散あるいはイ
オン注入によりＮ−ドレイン８よりも高濃度にされる。FIG. 1(b) is a longitudinal sectional view taken along YY in FIG. 1(a). The surge absorption diode 22 is MO3FET2
In order to make the withstand voltage lower than zero, the surface portion 21 of the N-drain 8 on the outer side 6 of the P-well layer 9 is made to have a higher concentration than the N-drain 8 by phosphorus diffusion or ion implantation.
第２図（ａ）〜（ｇ）は本発明の縦型電界効果トランジ
スタを形成するための工程を示す例であり、６０Ｖ耐圧
の場合ではドレイン基板としては２×１０ ”／ａｔ！
程度にアンチモンがドープされたＮ＋シリコン基板７に
１Ωｃｍ（約５．６ Ｘ １０ ”／ＣＩ＋り程度にリ
ンがドープされた厚さ約１２μｍのエピタキシャル層（
Ｎ−ドレイン）８が形成されたものが用いられる。FIGS. 2(a) to 2(g) are examples showing steps for forming a vertical field effect transistor of the present invention. In the case of a withstand voltage of 60V, the drain substrate is 2×10"/at!
An epitaxial layer (approximately 12 μm thick) doped with phosphorus to an extent of 1 Ωcm (approximately 5.6
An N-drain (N-drain) 8 is used.
第２図（ａ）はＮ′″ドレイン８の表面部２１をＮ−ド
レイン８よりも高濃度にするための工程であり、フォト
レジスト工程で拡散用の窓２３を形成した後リンを打込
みエネルギー１２０ＫｅＶ、 ドーズ量７ Ｘ １０
”／ｌｒｉ程度でイオン注入することにより８層２１
を形成する。全ての拡散工程終了後では８層２１の表面
濃度は約９ Ｘ １０ ”／ａ＋ｔ、深さは約３．０μ
ｍ程度である。FIG. 2(a) shows a process for making the surface portion 21 of the N''' drain 8 more highly concentrated than the N- drain 8. After forming a diffusion window 23 in a photoresist process, phosphorus is implanted with energy. 120KeV, dose 7 x 10
8 layers 21 by ion implantation at about ”/lri.
form. After all the diffusion steps are completed, the surface concentration of the 8 layers 21 is approximately 9×10”/a+t, and the depth is approximately 3.0μ.
It is about m.
第２図（ｂ）はサージ吸収用ダイオード２２の７ノ−Ｆ
層９を形成するための工程でフォトレジスト工程で拡散
用の窓２４を形成した後ポロンを打込みエネルギー７０
ＫｅＶ、 ドーズ量８Ｘ１０”／ｄ程度でイオン注入
することによりアノード層９が形成される。７ノ一ド層
９はＭＯ８ＦＥＴＯ２０のベース抵抗の低減、ドレイン
・ソース間耐圧の向上のためＭＯ８ＦＥＴ２０にも形成
される場合もある。全ての拡散工程終了後ではアノード
層９０表面濃度は約Ｉ Ｘ １０ ”／ｃｌ、深さは約
４μｍである。Figure 2(b) shows the 7-F of the surge absorbing diode 22.
In the process for forming layer 9, after forming the diffusion window 24 in the photoresist process, poron is implanted with an energy of 70
The anode layer 9 is formed by ion implantation at a KeV dose of about 8×10”/d.The anode layer 9 is also formed in the MO8FET20 to reduce the base resistance of the MO8FETO20 and improve the breakdown voltage between the drain and source. After all the diffusion steps are completed, the surface concentration of the anode layer 90 is about I x 10 ''/cl, and the depth is about 4 μm.
第２図（ｃ）は厚さ約５００人のゲート酸化膜１３を選
択的に形成するための工程、第２図（ｄ）はゲート電極
としてのポリシリコン層１４を選択するための工程であ
る。ポリシリコン層１４は５Ｘ Ｉ Ｑ ”／ａ＆程度
にリンをドープした厚さ約０．６μのＮ形のものが用い
られる。FIG. 2(c) shows a process for selectively forming a gate oxide film 13 with a thickness of approximately 500 nm, and FIG. 2(d) shows a process for selecting a polysilicon layer 14 as a gate electrode. . The polysilicon layer 14 is of N type and has a thickness of about 0.6 μm and is doped with phosphorus to about 5X I Q ”/a&.
第２図（ｄ）はＭＯ８ＦＥＴ２０のベース層１０を形成
するための工程でありポーンを打込みエネルギー約７０
ＫｅＶ、 ドーズ量約８Ｘ１０”／Ｃ１１！のイオン
注入後窒素雰囲気で温度１２００℃で約１時間の押込み
を行うことによりベース層１０を形成する。この場合ベ
ース層１０の表面濃度は約５ Ｘ １０ ′７／ａｎｔ
、深さ約３．５ μｍである。FIG. 2(d) shows the process for forming the base layer 10 of the MO8FET 20, in which a pawn is implanted with an energy of about 70%.
The base layer 10 is formed by implanting KeV ions at a dose of about 8×10”/C11! and then indenting in a nitrogen atmosphere at a temperature of 1200° C. for about 1 hour. In this case, the surface concentration of the base layer 10 is about 5×10 '7/ant
, the depth is approximately 3.5 μm.
第２図（ｅ）はソース層１１を選択的に形成するための
工程であり、フォトレジスト工程により、アルミニウム
あるいは酸化膜あるいはポリシリコンが選択的に残され
、イオン注入あるいは拡散のマスク材として用いられる
。ソース層１１はリンを打込みエネルギー約８０ＫｅＶ
、 ドーズ量的５Ｘ １０１６／ｃｄのイオン注入後
窒素雰囲気で温度的１０００℃で約３０分アニールして
形成される。FIG. 2(e) shows a process for selectively forming the source layer 11, in which aluminum, oxide film, or polysilicon is selectively left in the photoresist process, and is used as a mask material for ion implantation or diffusion. It will be done. The source layer 11 is implanted with phosphorus with an energy of approximately 80 KeV.
After ion implantation at a dose of 5×10 16 /cd, annealing is performed at a temperature of 1000° C. for about 30 minutes in a nitrogen atmosphere.
この場合ソース層１１の表面濃度は約ｌＸｌ０”／−１
深さは約１．０μｍである。In this case, the surface concentration of the source layer 11 is approximately lXl0''/-1
The depth is approximately 1.0 μm.
第２図（「）は層間絶縁膜１５、及びコンタクトホール
を形成するための工程で層間絶縁膜１５としてはリンを
８モル程度含んだ厚さ約５００００程度の酸化膜をＣＶ
Ｄにより形成したものを用いる。またコンタクトホール
はウェットあるいはドライエツチングによる酸化膜エツ
チングにより形成される。Figure 2 () shows a process for forming an interlayer insulating film 15 and a contact hole.As the interlayer insulating film 15, an oxide film with a thickness of about 50,000 and containing about 8 moles of phosphorus is used.
The one formed by D is used. Further, the contact hole is formed by etching the oxide film by wet or dry etching.
第２図（ｇ）はソース電極としてのアルミニウム１６、
ＥＱ１７．ゲート電極（ポリシリコンゲートとコンタク
トされている）を選択的に形成する工程であり、アルミ
ニウムを蒸着あるいはスパッタにより厚さ約３．５μｍ
つけて選択的にエツチングすることにより各電極のパタ
ーンを得る。この後裏面にドレイン電極１８としてＡｇ
を主体とする金属層が蒸着により形成される。FIG. 2(g) shows aluminum 16 as a source electrode,
EQ17. This is a process of selectively forming the gate electrode (contacted with the polysilicon gate), and aluminum is deposited or sputtered to a thickness of approximately 3.5 μm.
A pattern of each electrode is obtained by selectively etching the electrode. After this, Ag is placed on the back side as the drain electrode 18.
A metal layer mainly consisting of is formed by vapor deposition.
なお、以上はｎチャネル型の縦型電界効果トランジスタ
の場合について述べたが、本発明はｐチャネル型の縦型
電界効果トランジスタについても同様に適用できる。Note that although the case of an n-channel type vertical field effect transistor has been described above, the present invention can be similarly applied to a p-channel type vertical field effect transistor.
以上説明したように本発明は、ＭＯＳＦＥＴのセル領域
の外側にＭＯＳＦＥＴのドレイン・ソース間耐圧よりも
低いサージ吸収用ダイオードを内蔵させることにより、
ドレイン・ソース間に印加されたサージによるブレーク
ダウン電流をこのサージ吸収用ダイオードのみに流すこ
とにより、ＭＯＳＦＥＴに寄生的に存在するバイポーラ
トランジスタがターンオンせず、サージ破壊耐量を大幅
に向上できる効果がある。As explained above, the present invention has a built-in surge absorbing diode outside the cell area of the MOSFET, which has a lower breakdown voltage between the drain and source of the MOSFET.
By allowing the breakdown current caused by the surge applied between the drain and source to flow only through this surge absorbing diode, the bipolar transistor that exists parasitically in the MOSFET will not be turned on, and the surge breakdown capability can be greatly improved. .
第１図（ａ）は本発明の縦型電界効果トランジスタの平
面図、第１図（ｂ）は第１図（ａ）のＹ−Ｙ線に沿った
縦断面図、第２図（ａ）〜（ｇ）は本発明の縦型電界効
果トランジスタの製造工程を示す縦断面図、第３図（ａ
）は従来の縦型電界効果トランジスタの平面図、第３図
（ｂ）は第３図（ａ）のＸ−Ｘ線に沿った縦断面図であ
る。
１・・・・・・サージ吸収用ダイオード（従来例）、２
・・・・・・ＭＯＳＦＥＴＯのセル領域、３・・・・・
・ゲートバット、４・・・・・・ゲートフィンガー ５
・・・・・・ソースバット、６・・・・・・サージ吸収
用ダイオード（本発明）、７・・・・・・Ｎ＋ドレイン
、８・・・・・・Ｎ−ドレイン、９・・・・・・Ｐウェ
ル（７ノード）、９’・・・・・・ｐウェル、ｌＯ・・
・・・・Ｐベース、１１・・・・・・Ｎ＋ソース、１１
′・・・・・・Ｎ層層、１２・・・・・・酸化膜、１３
・・・・・・ゲート酸化膜、１４・・・・・・ゲート電
極（ポリシリコン）、１５・・・・・・層間絶縁膜、１
６・・・・・・ソース電極、１７・・・・・・ＥＱＲ（
Ｐアルミニウム）、１８・・・・・・ドレイン電極（Ａ
ｇ）、１９・・・・・・サージ吸収用ダイオード（従来
例）、２０・・・・・・ＭＯＳＦＥＴ部、２１・・・・
・・Ｎ層、２２・・・・・・サージ吸収用ダイオード（
本発明）。FIG. 1(a) is a plan view of a vertical field effect transistor of the present invention, FIG. 1(b) is a vertical cross-sectional view along the Y-Y line of FIG. 1(a), and FIG. 2(a) ~(g) are vertical cross-sectional views showing the manufacturing process of the vertical field effect transistor of the present invention, and FIG.
) is a plan view of a conventional vertical field effect transistor, and FIG. 3(b) is a longitudinal sectional view taken along the line X--X in FIG. 3(a). 1... Surge absorption diode (conventional example), 2
...MOSFETO cell area, 3...
・Gate bat, 4...Gate finger 5
... Source bat, 6 ... Surge absorption diode (present invention), 7 ... N+ drain, 8 ... N- drain, 9 ... ...P well (7 nodes), 9'...p well, lO...
...P base, 11...N+ source, 11
'...N layer, 12...Oxide film, 13
......Gate oxide film, 14...Gate electrode (polysilicon), 15...Interlayer insulating film, 1
6... Source electrode, 17... EQR(
P aluminum), 18... Drain electrode (A
g), 19... Surge absorption diode (conventional example), 20... MOSFET section, 21...
...N layer, 22...Surge absorption diode (
present invention).
Claims (1)
電界効果トランジスタに於て前記ソース及び前記ドレイ
ンの間に縦型電界効果トランジスタよりは耐圧の低いダ
イオードを内蔵した事を特徴とする縦型電界効果トラン
ジスタA vertical field effect transistor having a source and a gate on the front surface and a drain on the back surface, characterized in that a diode having a lower breakdown voltage than that of the vertical field effect transistor is built in between the source and the drain. transistor
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1144910A JPH038373A (en) | 1989-06-06 | 1989-06-06 | Vertical type field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1144910A JPH038373A (en) | 1989-06-06 | 1989-06-06 | Vertical type field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH038373A true JPH038373A (en) | 1991-01-16 |
Family
ID=15373123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1144910A Pending JPH038373A (en) | 1989-06-06 | 1989-06-06 | Vertical type field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH038373A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0472771A (en) * | 1990-07-13 | 1992-03-06 | Matsushita Electron Corp | Mosfet |
| US5313088A (en) * | 1990-09-19 | 1994-05-17 | Nec Corporation | Vertical field effect transistor with diffused protection diode |
| US6855981B2 (en) | 2001-08-29 | 2005-02-15 | Denso Corporation | Silicon carbide power device having protective diode |
-
1989
- 1989-06-06 JP JP1144910A patent/JPH038373A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0472771A (en) * | 1990-07-13 | 1992-03-06 | Matsushita Electron Corp | Mosfet |
| US5313088A (en) * | 1990-09-19 | 1994-05-17 | Nec Corporation | Vertical field effect transistor with diffused protection diode |
| US6855981B2 (en) | 2001-08-29 | 2005-02-15 | Denso Corporation | Silicon carbide power device having protective diode |
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