JPH0381180B2 - - Google Patents
Info
- Publication number
- JPH0381180B2 JPH0381180B2 JP57159853A JP15985382A JPH0381180B2 JP H0381180 B2 JPH0381180 B2 JP H0381180B2 JP 57159853 A JP57159853 A JP 57159853A JP 15985382 A JP15985382 A JP 15985382A JP H0381180 B2 JPH0381180 B2 JP H0381180B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- processing unit
- central processing
- clock
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15985382A JPS5949647A (ja) | 1982-09-14 | 1982-09-14 | メモリ制御方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15985382A JPS5949647A (ja) | 1982-09-14 | 1982-09-14 | メモリ制御方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5949647A JPS5949647A (ja) | 1984-03-22 |
JPH0381180B2 true JPH0381180B2 (zh) | 1991-12-27 |
Family
ID=15702656
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15985382A Granted JPS5949647A (ja) | 1982-09-14 | 1982-09-14 | メモリ制御方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5949647A (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62102343A (ja) * | 1985-10-29 | 1987-05-12 | Yaskawa Electric Mfg Co Ltd | デジタル計算機用記憶装置 |
JP3001892B2 (ja) * | 1988-03-31 | 2000-01-24 | 日本電気ホームエレクトロニクス株式会社 | メモリアクセス回路 |
JPH02143979A (ja) * | 1988-11-25 | 1990-06-01 | Matsushita Electric Works Ltd | 半導体メモリ |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5226125A (en) * | 1975-08-25 | 1977-02-26 | Nippon Telegr & Teleph Corp <Ntt> | Buffer memory system |
-
1982
- 1982-09-14 JP JP15985382A patent/JPS5949647A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5226125A (en) * | 1975-08-25 | 1977-02-26 | Nippon Telegr & Teleph Corp <Ntt> | Buffer memory system |
Also Published As
Publication number | Publication date |
---|---|
JPS5949647A (ja) | 1984-03-22 |
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