JPH03792B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a notched insulated gate static induction transistor that can perform high-speed switching and consumes little power.

(Prior Art) Conventionally, insulated gate transistors have been used for high frequency amplification and integrated circuits, but they have the drawback of low driving capability. For example, a complementary insulated gate transistor integrated circuit (C-MOS) is known as an application of insulated gate transistors, but although it consumes less power, it has a small driving capability and a slow operating speed. In order to overcome these drawbacks, one of the inventors of the present invention proposed an insulated gate static induction transistor (for example, Japanese Patent Application No.
No. 1756) and a notched insulated gate static induction transistor (for example, Japanese Patent Application No. 13707/1983) have been proposed. Insulated gate static induction transistors are designed so that the effect of the drain electric field extends to the source, and because current flows not only at the semiconductor/insulating film interface but also through the substrate, it has features such as high driving ability. In particular, in the notch type insulated gate static induction transistor, since the channel is formed in the depth direction of the semiconductor substrate, the channel length and gate length can be easily controlled, and it is suitable for shortening the channel. Therefore, the drive capability can be increased and the parasitic capacitance can be reduced, so that it exhibits excellent performance as a high-speed transistor or a high-speed, low-power consumption integrated circuit.

The prior art will be explained below using FIG. 3. FIG. 3a shows an example of the cross-sectional structure of a conventional notched insulated gate static induction transistor. Code 3 in the same figure
0 indicates a semiconductor substrate, and a U-shaped groove is provided in a part of its main surface. And this U
A drain region 31 and a channel region are located in the shape groove.
33, source regions 32 are provided in order in the depth direction,
A drain electrode 31' is connected to the drain region 31. The drain region 31 and the source region 32 each have an impurity density of about 10 ¹⁸ to 10 ²¹ cm ⁻³ , and the conductivity type may be p-type or n-type.
Further, the region 31 may be used as a source region and the region 32 may be used as a drain region. The channel area 33 is
It has an impurity density of about 10 ¹² to 10 ¹⁶ cm ^-3 . The conductivity types of the drain region 31 and the source region 32 may be the same or opposite, or they may have a multilayer structure, but the depletion layer spreading from the drain region 31 in at least a part of the operating region is the source region 32. The impurity density is determined together with the depth of the U-shaped groove in order to reach . A gate insulating film 34 such as an oxide film is provided in contact with the channel region 33 and has a thickness of about 100 to 1000 Å. On the opposite side of the gate insulating film 34, a gate electrode 3 made of metal, polycrystalline silicon, etc.
4' is provided. Note that the reference numeral 35 in the figure indicates a field oxide film. The conventional notched insulated gate static induction transistor shown in Figure 3a is formed in the depth direction of the semiconductor substrate, so the dimensions of the transistor can be controlled with the precision of film formation, and short channel It is well suited for high-speed transistors, resulting in high-speed, low-power integrated circuits. However, in conventional notched insulated gate static induction transistors, especially when short channels are used to increase speed, current flows between the drain and the source even at a distance from the gate surface due to the influence of the drain electric field. This current component cannot be controlled by the gate voltage. Therefore,
It has drawbacks such as a large leakage current when off and a low breakdown voltage between the drain and source.
For example, Figure 3b shows the drain current of a conventional notched insulated gate static induction transistor designed with a channel length of approximately 0.5 μm, a channel impurity dose of approximately 2×10 ¹³ cm ^-2 , and a gate oxide film thickness of approximately 250 Å. - This is an example of drain voltage characteristics. Even when the gate voltage is 0V, drain current flows as the drain voltage increases. Of course, by selecting the impurity density of the channel region 33, it is possible to suppress such current flowing through the bulk side to some extent. The channel length in figure c is approximately 0.5μ.
This is an example of the drain current-drain voltage characteristics of a conventional notched insulated gate static induction transistor designed with a channel impurity dose of about 6×10 ¹³ cm ^-2 and a gate oxide film thickness of about 250 Å. In this way, although the leakage current during off-time is improved, the electrostatic induction effect on the drain side becomes less likely to reach the source side, and the driving ability is sacrificed to some extent, such as by increasing the threshold voltage of the element.

(Problems to be Solved by the Invention) An object of the present invention is to overcome the drawbacks of the above-described notched insulated gate static induction transistor, improve the characteristics, and provide a switching device that can perform faster switching and consume less power. An object of the present invention is to provide an embedded insulated electrostatic induction transistor.

(Means for Solving the Problems) Therefore, in the present invention, as shown in FIG. A channel region 13 is provided, and the channel region 13' sandwiched between the drain region 11 and the source region 12 on the bulk side has a high impurity density. The impurity density of the channel region 13' on the bulk side is set so that no leakage current flows between the drain and the source under the influence of the drain electric field in normal use.

(Function) As a result, in such a structure, the channel can be shortened without increasing the threshold voltage or the leakage current between the drain and source, and high-speed switching can be performed, reducing power consumption. This results in a notch-type insulated gate static induction transistor with less noise.

(Example) FIG. 1a shows an example of a cross-sectional structure of a notched insulated gate static induction transistor according to the present invention.
Reference numeral 10 in the figure indicates a semiconductor substrate, and a U-shaped groove is provided in a part of the main surface thereof.
A drain region 11 is provided in this U-shaped groove so as to be in contact with the upper end of the side wall of the U-shaped groove,
Further, a source region 12 is provided so as to be in contact with the lower end of the side wall of the U-shaped groove, and a drain electrode 11' is connected to the drain region 11. Drain region 11 and source region 12 are each 10 ¹⁸ to 10 ²¹ cm
It has an impurity density of about ^-3 , and the conductivity type can be p-type or n-type. Further, the region 11 may be used as a source region, and the region 12 may be used as a drain region. The channel region 13 is provided near the side wall surface of the U-shaped groove and has an impurity density of about 10 ¹² to 10 ¹⁶ cm ⁻³ . Its conductivity type is drain region 11
and the source region 12 may be the same or opposite, but at least in a part of its operating region,
In order for the depletion layer spreading from the drain region 11 to reach the source region 12, its conductivity type and impurity density are determined together with the depth of the U-shaped groove. A drain region 1 is provided adjacent to the channel region 13.
A channel region 13' on the bulk side is provided between the drain region 11 and the source region 12.
and has a conductivity type opposite to that of the source region 12, and its impurity density is set so that leakage current does not flow between the drain and source due to the influence of the drain electric field. A gate insulating film 14 such as an oxide film is provided in contact with the channel region 13.
It has a film thickness of about Å. And gate insulating film 1
On the opposite side of 4, a gate electrode 14' made of metal, polycrystalline silicon, or the like is provided. In addition, the first
Reference numeral 15 in the figure a indicates a field oxide film.

Such a channel region 13 near the surface of the side wall of the U-shaped groove can be formed by performing epitaxial growth after digging the U-shaped groove, and the thickness can also be controlled with the precision of film formation. In particular, the growth method is molecular layer epitaxy (MLE).
By using layer epitaxy, low-temperature growth is possible, which reduces the redistribution of impurities and increases the precision of film formation to the order of one molecular layer.

FIG. 1b shows the gate voltage-drain current characteristics of a notched insulated gate static induction transistor according to the present invention in comparison with a conventional type. in this case,
It is designed to have a channel length of approximately 0.5 μm, a channel impurity dose of approximately 4×10 ¹³ cm ⁻² , and a gate oxide film thickness of approximately 250 Å. Even with the same impurity density in the bulk channel as in the conventional type, the threshold voltage can be lowered.

FIG. 2 shows a cross-sectional structure of one gate when the notched insulated gate static induction transistor of the present invention is applied to a complementary insulated gate integrated circuit. The N-channel transistor in the semiconductor substrate 20 is
n ⁺ drain region 21, N ⁺ source region 23, channel region 25, bulk side channel region 25',
It has a drain electrode 21', a gate insulating film 27, and a gate electrode 27', and the P channel transistor has a p ⁺ drain region 22, a p ⁺ source region 2
4, channel region 26, bulk side channel region 26', drain electrode 22', gate insulating film 27,
It has a gate electrode 27'. n ⁺ drain region 21, p ⁺ drain region 22, n ⁺ source region 23,
Each p ⁺ source region 24 has an impurity density of about 10 ¹⁸ to ^{10 21} cm ⁻³ . Channel areas 25, 26
each has an impurity density of about 10 ¹² to 10 ¹⁶ cm ^-3 , and at least in a part of its operating region, the depletion layer spreading from the drain regions 21 and 22 reaches the source regions 23 and 24. The impurity density is determined along with the depth of the U-shaped groove. The bulk side channel regions 25', 26' have a conductivity type opposite to that of the drain regions 21, 22 and the source regions 23, 24 (therefore, the regions 25' are p-type,
The region 26' is n-type), and the impurity density is set so that no current flows between the drain and source due to the influence of the drain electric field. The gate insulating film 27 such as an oxide film is
It has a film thickness of about 100 to 1000 Å. Note that 28 in the figure indicates a field oxide film. Also, P
A p-well 29 is provided to separate the channel and N-channel transistors. Gate electrode 27' is a logic input, drain electrodes 21' and 22' are logic outputs, and a power supply voltage is applied between source regions 23 and 24.

Even though shortening the channel makes it easier for the electrostatic induction effect of the drain voltage to reach the source region and increases the drive capability of the device, the notched insulated gate electrostatic induction transistor of the present invention does not allow the electrostatic induction effect of the drain voltage to easily reach the source region. By appropriately selecting the impurity densities of 25' and 6', it is possible to reduce the leakage current during off-time and reduce the standby power. Therefore, a complementary insulated gate integrated circuit with high speed and low power consumption can be provided.

(Effects of the Invention) As described above, the present invention improves the shortcomings of the conventional notch type insulated gate static induction transistor, and even when the channel is shortened and the static induction effect of the drain voltage is sufficiently obtained. , unnecessary drain-source current can be reduced. Therefore, the present invention can provide a notch type insulated gate static induction transistor that can perform high speed switching and has low power consumption, and can be used to integrate high speed and low power consumption insulated gate type transistors. It is possible to provide a circuit, and its industrial value is great.

[Brief explanation of the drawing]

FIG.
1 is a cross-sectional structure diagram, and FIG. 1B shows an example of drain current-gate voltage characteristics. FIG. 2 is a cross-sectional structural diagram of one embodiment of an integrated circuit using the notched insulated gate static induction transistor of the present invention.
Figure 3 shows an example of a conventional notch-type insulated gate static induction transistor, in which a is a cross-sectional structural diagram, b is an example of drain current-drain voltage characteristics, and c is a drain current. - This shows another example of drain voltage characteristics. 10, 20, 30: semiconductor substrate, 11, 21,
22, 31: drain region, 12, 23, 24,
32: Source region, 13, 25, 26: Channel region, 13', 25', 26': Bulk side channel region, 11', 21', 22', 31': Drain electrode, 14, 27, 34: Gate insulating film, 14',
27', 34': gate electrode, 15, 28, 35:
Field oxide film, 29:p well.

Claims (1)

[Scope of Claims] 1. A drain region having a U-shaped groove on the main surface of a semiconductor substrate, having a high impurity density and provided in contact with at least a part of the upper end of a side wall of the U-shaped groove; a source region with high impurity density provided so as to be in contact with at least a portion of the lower end of the side wall of the U-shaped trench; a first channel region with low impurity density provided near the surface of the side wall of the U-shaped trench; and the drain region. a second region sandwiched between the region and the source region and having a conductivity type different from that of the drain region and the source region.
a channel region, the impurity density is set so as to eliminate the current flowing through the second channel region, and the current flowing through the first channel region is
A notch type insulated gate static induction transistor characterized in that the transistor is controlled by an insulated gate provided in at least a portion of a shaped groove. 2. The notched insulated gate static induction transistor according to claim 1, wherein the first channel region is formed on the sidewall of the U-shaped groove by epitaxial growth. 3. The notched insulated gate static induction transistor according to claim 1 or 2, wherein the drain region and the source region are interchanged. 4. The notched insulated gate static induction transistor according to any one of claims 1 to 3, wherein the transistor constitutes at least a part of a component of a semiconductor integrated circuit.