JPH0376052B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction method capable of correcting errors with high error correction ability for both burst errors and random errors.

[Conventional technology]

The applicant of the present application has previously proposed a method called cross interleave as a data transmission method effective against burst errors. This generates a first check word sequence by supplying one word included in each of the PCM data sequences of a plurality of channels in a first arrangement state to a first error correction encoder. A second check word sequence is generated by putting one check word sequence and the PCM data sequence of multiple channels into a second arrangement state, and supplying one word included in each to a second error correction encoder. It performs double interleaving (arrangement rearrangement) even in word units. Interleaving is when the check words and PCM data included in a common error correction block are distributed and transmitted, and when they are returned to the original arrangement on the receiving side, the error word among the multiple words included in the common error correction block is The aim is to reduce the number. In other words, when a burst error occurs during transmission, this burst error can be dispersed. If such interleaving is performed twice, each of the first and second check words will constitute an error correction block, so even if an error cannot be corrected with one of the check words, the other one can be used to correct the error. Errors can be corrected, and the error correction capability can therefore be further improved.

[Problem that the invention seeks to solve]

By the way, if even one bit in one word is erroneous, the entire word is treated as erroneous, so when handling received data with relatively many random errors, it is not always necessary to have sufficient error correction capability. I can't say that.

[Means for Solving the Problems] In the present invention, an error correction encoder configured to form k check words for n input words based on a parity check matrix H shown below has a plurality of supplying words included in each of the PCM data series of the channels to form a first check word series; and at least words included in each of the PCM data series of the plurality of channels forming the first check word. A second check word sequence is formed by supplying words that do not completely match the words to be used for checking to the error correction encoder having the above configuration, and combining the PCM data sequences of the plurality of channels with the first and first check word sequences. 2
A check word series is transmitted, this transmitted data is received, and the received word is subjected to error correction processing based on the second check word, and a pointer indicating the presence or absence of an error is added to each word. is set, and the pointer indicating the presence or absence of an error is used to perform error correction processing based on the first check word.

H=1 α ¹ α ² 〓 〓 α ^k-1 1 α ² α ⁴ 〓 〓 α ^(k-1)2 1 α ³ α ⁶ 〓 〓 α ^(k-1)3 … … … … 1 α ^n-1 1 α ^2(n-1) 〓 〓 α ^(k-1)(n-1) 1 α ⁿ α ²ⁿ 〓 〓 α ^kn However, α is an irreducible polynomial on GF(2) as F(x) Sometimes, it is a root that satisfies (F(x)=0).

[Effect]

According to the above error correction code, it is possible to correct up to a 2-word error within one block, and when the error position is known, it is also possible to correct a 3-word error or a 4-word error. Since this error correction code is combined with multiple interleaving, sufficient error correction ability can be obtained even for received data with relatively many random errors.

Furthermore, the error correction code used in the present invention has the feature that when only one word error is to be corrected, the structure of the decoder can be greatly simplified.

〔Example〕

First, the error correction code used in this invention will be explained. When describing an error correction code, a vector representation or a cyclic group representation is used. First, consider an irreducible m-th degree polynomial F(x) on GF(2). A body GF that only has elements of “0” and “1”
On (2), the irreducible polynomial F(x) has no roots. Therefore, consider a virtual root α that satisfies (F(x)=0). At this time, 2 ^m different elements 0, α, α ² , α ³ . . . are expressed as powers of α including the zero element.
α ^m-1 constitutes the extended field GF(2 ^m ). GF (2 ^m )
is a polynomial ring modulo the m-th order irreducible polynomial F(x) over GF(2). The element of GF (2 ^m ) is 1, α=
It can be expressed as a linear combination of {x}, α ² ={x ² }, ..., α ^m-1 = {x ^m-1 }. That is, a ₀ + a ₁ {x} + a ₂ {x ² } +...+a _n-1 {x ^m-1 } = a ₀
+a ₁ α+a ₂ α ² +…+a _n-1 α ^m-1 or (a _n-1 , a _n-2 ,…, a ₂ , a ₁ , a ₀ ) where a ₀ , a ₁ ,…, a _n-1 ∈GF(p).

As an example, considering GF(2 ⁸ ), (mod.F
(x) = x ⁸ + x ⁴ + x ³ + x ² + 1), and all 8-bit data is a ₇ x ⁷ + a ₆ x ⁶ + a ₅ x ⁵ + a ₄ x ⁴ + a ₃ x ³ + a ₂ x ² + a ₁ x+
It is written as a ₀ or (a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ , a ₀ ), so for example, a ₇ is on the MSB side and a ₀ is on the MSB side.
Assign to LSB side. Since a _o belongs to GF(2),
0 or 1.

Further, the following (m×m) matrix T is derived from the polynomial F(x).

T=0 0...0 a ₀ 1 0...0 _{a 1} 0 1...0 a ₂ 〓 〓 〓 〓 〓 〓 〓 〓 0 0…1 a _n-1For other expressions, use the cyclic group. There was something there. This takes advantage of the fact that the 0 element is removed from GF(2 ^m ) and the remaining elements form a multiplicative group of order 2 ^m -1. When the elements of GF (2 ^m ) are expressed using a cyclic group, they become 0, 1 (=α ^2m-1 ), α, α ² , α ³ , ...α ^2m-2 .

Now, in this invention, when m bits are one word and n words constitute one block, k check words are generated based on the parity check matrix H below.

H=1 α ¹ α ² 〓 〓 α ^k-1 1 α ² α ⁴ 〓 〓 α ^(k-1)2 1 α ³ α ⁶ 〓 〓 α ^(k-1)3 …… …… …… 1 α ^n-1 α ^2(n-1) 〓 〓 α ^(k-1)(n-1) 1 α ⁿ α ²ⁿ 〓 〓 α ^kn Also, the parity check matrix H is expressed in the same way by the matrix T. be able to.

H=I T ¹ T ² 〓 〓 T ^k-1 I T ² T ⁴ 〓 〓 T ^(k-1)2 I T ³ T ⁶ 〓 〓 T ^(k-1)3 …… …… …… …… I T ^n-1 T ^2(n-1) 〓 〓 T ^(k-1)(n-1) 1 T ⁿ T ²ⁿ 〓 〓 〓 T ^knHowever , I is a (m×m) unit matrix.

All of the above expressions are essentially the same, and the first column is all 1 or I, and the (n-1)th column is
It may also be configured up to a row. Furthermore, 4 pieces (k=
The error correction code will be explained in detail using case 4) as an example. One block of received data is expressed as a column vector V=
(Assuming W ₁ , W ₂ , W ₃ , ...W _o , the four syndromes S ₁ , S ₂ , S ₃ , S ₄ that occur on the receiving side are S ₁ S ₂ S ₃ S ₄ = H・V ^T S ₁ = _o 〓 ⁱ⁼¹ W _i S ₂ = _o 〓 ⁱ⁼¹ T ⁱ W _i S ₃ = _o 〓 ⁱ⁼¹ T ²ⁱ W _i S ₄ = _o 〓 ⁱ⁼¹ T ³ⁱ W _i .

4 check words in 1 block (p=
W _o-3 , q=W _o-2 , r=W _o-1 , s=W _o ). This check word is obtained as follows.

However, Σ means _o-4 〓 ⁱ⁼¹ .

p+q+r+s=ΣW _i T ^n-3 p+T ^n-2 q+T ^n-1 r+T ⁿ s=ΣT ⁱ W _i T ^2n-6 p+T ^2n-4 q+T ^2n-2 r+T ²ⁿ s=ΣT ²ⁱ W _i T ^3n-9 p+T ^{3n -6} q+T ^3n-3 r+T ³ⁿ s=ΣT ³ⁱ W _i p+q+r+s=ΣW _i =a p+Tq+T ² r+T ³ s=ΣT ^i-n+3 W _i =b p+T ² q+T ⁴ r+T ⁶ s=ΣT ^{22(i-n +3)} W _i =c p+T ³ q+T ⁶ r+T ⁹ s=ΣT ^33(i-n+3) W _i =d The check word can be obtained by solving the above-mentioned simultaneous equations. The calculation for this purpose is the calculation defined in GF(2 ^m ), and its overdetermination is omitted and the result is shown below.

p=T ⁶ a+(T ³ +T ⁴ +T ⁵ )b+(T+T ² +T ³ )
c+d/(1+T)(1+ ^T2 )(1+ ^T3 ) q= ^T5 a+( ^T2 + ^T3 + ^T5 )b+(1+ ^T2 + ^T3 )
c+d/T ² (1+T ⁴ ) r=T ⁴ a+(T+T ³ +T ⁴ )b+(1+T+T ³ )
c+d/T ³ (1+T ⁴ ) s=T ³ a+(T+T ² +T ³ )b+(1+T+T ² )
c+d/T ³ (1+T) (1+T ² ) (1+T ³ ) p=[T ⁶ ΣW _i + (1+T+T ² ) {ΣT ^i-n+6 W _i +ΣT ^2(i-n+3)+1 W _i } +ΣT ^3(i-n+3) W _i ] ×(1+T) ^-1 (1+T ² ) ^-1 (1+T ³ ) ^-1 q=[T ⁵ ΣW _i +(1+T+T ³ )ΣT ^i-n+5 W _i +(1+T ² +T ³ )ΣT ^2(i-n+3) +W _i +ΣT ^3(i-n+3) W _i ]×T ^-2 (1+T ⁴ ) ^-1 r=[T ⁴ ΣW _i +(1 +T ² +T ³ )ΣT ^i-n+4 W _i +(1+T+T ³ )ΣT ^2(i-n+3) W _i +ΣT ^3(i-n+3) W _i 〕×T ^{- 3} (1+T ⁴ ) ^-1 s=[T ³ ΣW _i + (1+T+T ² ) {ΣT ^i-n+4 W _i +ΣT ^22(i-n+3) W _i } +ΣT ^{3(i-n+3 )} W _i ] ×T ^-3 (1+T) ^-1 (1-T ² ) ^-1 (1+T ³ ) ^-1 Next, if data containing the check word formed as described above is transmitted and received. This section explains error correction. It is assumed that a pointer indicating the error position is not used.

[1] When there is no error: S ₁ = S ₂ = S ₃ = S ₄ = 0 [2] When there is a 1-word error (error pattern is e _i ): S ₁ = e _i S ₂ = T ⁱ e _i S ₃ = T ²ⁱ e _i S ₄
= T ³ⁱ e _i Therefore, the relationships T ⁱ S ₁ = S ₂ T ⁱ S ₂ = S ₃ T ⁱ S ₃ = S ₄ are all established. The syndrome S ₁ at that time becomes the error pattern e _i itself.

[3] In case of 2-word error (e _i , e _j ) S ₁ = e _i + e _j S ₂ = T ⁱ e _i + T ^j e _j S ₃ = T ²ⁱ e _i +T ^2j e _j S ₄ = T ³ⁱ e _i +T ^3j e _{jTransforming} the above equation, T ^j S ₁ +S ₂ = (T ⁱ +T ^j )e _i T ^j S ₂ +S ₃ =T ⁱ (T ⁱ +T ^j )e _i T ^j S ₃ +S ₄ =T ²ⁱ (T ⁱ + T ^j ) e _i Therefore, if T ⁱ (T ^j S ₁ + S ₂ ) = T ^j S ₂ + S ₃ T ⁱ (T ^j S ₂ + S ₃ ) = T ^j S ₃ + S ₄ holds. , a 2-word error is determined, and the error pattern at that time is e _i =S ₁ +T ^-j S ₂ /1+T ^i+j e _j =S ₁ +T ^-i S ₂ /1+T ^j+i [4] 3-word error (e _i , e _j , e _k ) S ₁ = e _i +e _j +e _k S ₂ = T ⁱ e _i +T ^j e _j +T ^k e _k S ₃ =T ²ⁱ e _i +T ^2j e _j +T ^2k e _k S ₄ = T ³ⁱ e _i + T ^3j e _j + T ^3k e _kIf the above equation is transformed, T ^k S ₁ + S ₂ = (T ⁱ + T ^k ) e _i + (T ^j + T ^k ) e _j T ^k S ₂ + S ₃ =T ⁱ (T ⁱ +T ^k )e _i +T ^j (T ^j +T ^k )e _j T ^k S ₃ +S ₄ =T ²ⁱ (T ⁱ +T ^k )e _i +T ^2j (T ^j +T ^k )e _j T ^j (T ^k S ₁ + S ₂ ) + (T ^k S ₂ + S ₃ ) = (T ⁱ + T ^j ) (T ⁱ
+T ^k ) e _i T ^j (T ^k S ₂ + S ₃ ) + (T ^k S ₃ + S ₄ ) = T ⁱ (T ⁱ + T ^j )
(T ⁱ + T ^k ) e _i From the above formula, T ⁱ (T ^j (T ^k S ₁ + S ₂ ) + (T ^k S ₂ + S ₃ )) = T ^j (T ^k S ₂ + S ₃ )
If +(T ^k S ₃ +S ₄ ) is established, it can be determined that there is a 3-word error.
However, the condition is that (S ₁ ≠0, S ₂ ≠0, S ₃ ≠0). At that time, each error pattern is e _i = S ₁ + (T ^-j + T ^-k ) S ₂ + T ^-jk S ₃ / (1 + T ^ij ) (
1+T ^ik ) e _j =S ₁ +(T ^-k +T ^-i )S ₂ +T ^-ki S ₃ /(1+T ^ji )(
1 + T ^jk ) e _k = S ₁ + (T ^-i + T ^-j ) S ₂ + T ^-ij S ₃ / (1 + T ^ki ) (
1+T ^ki ).

In this way, all up to 2-word errors can be corrected without using pointers. Also,
Use a pointer to locate the error location (i, j, k,
If l) is known, the 4-word error can also be corrected.

Incidentally, if the number k of check words is further increased, the error correction ability is further improved.

Hereinafter, a specific example in which the present invention is applied to recording and reproducing audio PCM signals will be described with reference to the drawings. FIG. 1 shows the entirety of an error correction encoder provided in a recording system, and an audio PCM signal is supplied to its input side. audio
A PCM signal is formed by sampling each of the left and right stereo signals at a sampling frequency f _s (for example, 44.1 [kHz]) and converting one sample into one word (16 bits in two's complement code). ing. Therefore, for the left channel audio signal, PCM data with consecutive words (L ₀ , L ₁ , L ₂ ...) is obtained, and for the right channel audio signal, (R ₀ , R ₁ , R 2 ...) is obtained. ₂ ...
...) and PCM data in which each word is consecutive is obtained. This left and right channel PCM data is divided into 6 channels each, for a total of 12 channels.
A PCM data series is input. At a given timing, (L _6o , R _6o , L _6o+1 , R _6o+1 , L _6o+2 ,
Twelve words (R _6o+2 , L _6o+3 , R _6o+3 , L _6o+4 , R _6o+4 ) are input. In this example, one word is divided into upper 8 bits and lower 8 bits, and 12 channels are further processed as 24 channels. For simplicity, one word of PCM data is expressed as W _i ,
The upper 8 bits are distinguished by adding the suffixes W _i , _A and A, and the lower 8 bits are distinguished by adding the suffixes W _i,B and B. For example, L _6o will be divided into two, W _12o,A and W _12o,B .

These 24 channels of PCM data series are first supplied to the even-odd interleaver 1. (n=
0, 1, 2...), then L _6o (=W _12o,A ,
W _12o,B ), R _6o (=W _12o+1,A , W _12o+1,B ), L _6o+2 (=
W _12o+4,A , W _12o+4,B ), R _6o+2 (=W _12o+5,A ,
W _12o+5,B ), L _6o+4 (=W _12o+8,A , W _12o+8,B ), R _6o+4
(=W _12o+9,A , W _12o+9,B ) are even-numbered words, and the others are odd-numbered words.
Each of the PCM data series consisting of even-numbered words is transmitted to the 1-word delay circuits 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5 of the even-odd interleaver 1.
It is delayed by one word by B, 6A, 6B, 7A, and 7B. In addition, in the even-odd interleaver 1, 12 data sequences consisting of even-numbered words are
The 12 data sequences consisting of odd-numbered words occupy the 13th to 12th transmission channels.
Converted to occupy up to 24 transmission channels.

The even-odd interleaver 1 is provided to prevent errors in two or more consecutive words in each of the left and right stereo signals, and to prevent these errors from becoming uncorrectable. For example (L _i-1 , L _i , L _i+1 )
Considering three consecutive words, if L _i is wrong and this error is uncorrectable, then
It is desired that L _i-1 or L _i+1 is correct. it is,
When correcting erroneous data L _i , L _i is interpolated using the previous correct word L _i-1 (previous value hold), or L _i is corrected using the average value of L _i-1 and L _i+1 .
This is to interpolate. The delay circuits 2A, 2B to 7A, 7B of the even-odd interleaver 1 are provided to ensure that adjacent words are included in different error correction blocks. Also, the reason why transmission channels are grouped for each data series consisting of even-numbered words and data series consisting of odd-numbered words is that when interleaving is performed, the recording positions of adjacent even-numbered words and odd-numbered words are This is to make the distance between them as large as possible.

At the output of the even-odd interleaver 1, a PCM data sequence of 24 channels in the first arrangement state appears, one word is extracted from each of them and supplied to the encoder 8, and the first check word Q _12o ,
Q _12o+1 , Q _12o+2 , Q _12o+3 are formed. A correction block consists of (W _12o-12,A , W _12o-12,B , W _12o+1-12,A ,
W _12o+1-12,B , W _12o+4-12,A , W _12o+4-12,B ,
W _12o+5-12,A , W _12o+5-12,B , W _12o+8-12,A ,
W _12o+8-12,B , W _12o+9-12,A , W _12o+9-12,B , W _12o+2,A ,
W _12o+2,B , W _12o+3,A , W _12o+3,B , W _12o+6,A ,
W _12o+6,B , W _12o+7,A , W _12o+7,B , W _12o+10,A ,
W _12o+10,B , W _12o+11,A , W _12o+11,B , Q _12o , Q _12o+1 ,
Q _12o+2 , Q _12o+3 ). In the first encoder 8, the number of words in one block: (n=28) and the number of bits in one word: (n=
8), the number of check words: (k=4) is encoded.

These 24 PCM data sequences and 4 check word sequences are supplied to the interleaver 9. In the interleaver 9, the position of the transmission channel is changed so that a check word sequence is interposed between the PCM data sequence consisting of even-numbered words and the PCM data sequence consisting of odd-numbered words, and then a delay for interleaving is performed. Processing is in progress. This delay processing is performed for each of the other 27 transmission channels excluding the first transmission channel, 1D, 2D, 3D, 4D, ..., 26D, 27D.
This is accomplished by inserting a delay circuit with a delay amount of (D is a unit delay amount).

At the output of the interleaver 9, 28 data sequences in the second arrangement state appear, and one word is extracted from each data sequence and sent to the encoder 1.
0 and the second check word P _12o ,
P _12o+1 , P _12o+2 , P _12o+3 are formed. The error correction block consisting of 32 words including the second check word is as follows.

(W _12o-12,A , W _{12o-12(D+1),B} , W _{12o+1-12(2D+1),A} ,
W _{12o+1-12(3D+1),B} , W _{12o+4-12(4D+1),A} ,
W _{12o+4-12(5D+1),B} , W _{12o+5-12(6D+1),A} ,
W _{12o+5-12(7D+1),B} ,...Q _12o-12(12D) ,
Q _{12o+1-12(13D)} , Q _{12o+2-12(14D)} , Q _{12o+3-12(15D)} ,...
…
…W _{12o+10-12(24D),A} , W _{12o+10-12(25D),B} ,
W _{12o+11-12(26D),A} , W _{12o+11-12(27D),B} , P _12o , P _12o+1
,
P _12o+2 , P _12o+3 ) 32 including such first and second check words
An interleaver 11 in which a one-word delay circuit is inserted is provided for the even-numbered transmission channel among the data sequences, and inverters 12 and 1 are provided for the second check word sequence.
3, 14, and 15 are inserted. interleaver 1
1, it is possible to deal with the fact that an error in the number of words that crosses the boundary between blocks is likely to occur and cannot be corrected. In addition, inverters 12 to 15
This is provided to prevent a malfunction in which all data in one block becomes "0" due to dropout during transmission and the reproduction system determines this as correct data.

Then, each of the 32 words extracted from each of the 24 PCM data sequences and 8 check word sequences that are finally obtained is serialized, and as shown in Figure 2, 16-bit synchronization is placed at the beginning. A signal is added to form one transmission block and transmitted. In FIG. 2, one word extracted from the i-th transmission channel is shown as u _i for simplicity of illustration. Specific examples of transmission systems include magnetic recording/reproducing devices and rotating disk devices such as optical disks.

The encoder 8 described above is related to the error correction code as described above, (n=28, m=8, k=4)
and a similar encoder 10 has (n=32, m=8,
k=4).

The reproduced data is applied to the input of the error correction decoder shown in FIG. 3 every 32 words of one transmission block. Since this is playback data, it may contain errors. In the absence of errors, the 32 words applied to the input of this decoder will match the 32 words that appear at the output of the error correction encoder.
The error correction decoder performs deinterleaving processing corresponding to the interleaving processing in the encoder to restore the data order and then perform error correction.

First, a deinterleaver 1 in which a 1-word delay circuit is inserted for odd-numbered transmission channels.
6 are provided, and inverters 17, 18, 19, and 20 are inserted for the check word sequence, and the check word sequence is supplied to the first decoder 21. Decoder 21
Now, as shown in Figure 4, the parity check matrix
Syndromes S ₁₁ , S ₁₂ , S ₁₃ , and S ₁₄ are generated from H _C1 and the input 32 words (V ^T ), and the error correction described above is performed based on these syndromes. α is an element of GF(2 ⁸ ) of (F(x)=X ⁸ , X ⁴ , X ³ , X ² +1). 24 PCM data sequences and 4 check word sequences appear from the decoder 21, and a pointer (at least 1 bit) indicating the presence or absence of an error is added to each word of this data sequence.

The output data sequence of this decoder 21 is supplied to a deinterleaver 22. Deinterleaver 22
are for canceling the delay processing performed by the interleaver 9 in the error correction encoder, and are applied to each of the channels from the first transmission channel to the 27th transmission channel (27D, 26D, 25D,
...2D, 1D) and delay circuits with different delay amounts are inserted. The output of the deinterleaver 22 is supplied to a second decoder 23. In the decoder 23, as shown in _FIG.
and 28 words of input and from the syndrome S ₂₁ ,
S ₂₂ , S ₂₃ , and S ₂₄ are generated, and based on these, error correction as described above is performed. A pointer for a word whose error was corrected in the decoder 23 is cleared, and a pointer for a word containing an error that could not be corrected by the decoder 23 is not cleared.

The data sequence appearing at the output of the decoder 23 is supplied to an even-odd deinterleaver 24. In the even-odd deinterleaver 24, the PCM data series consisting of even-numbered words and the PCM data series consisting of odd-numbered words are returned so that they are located on different transmission channels, and the PCM data series consisting of odd-numbered words is A 1-word delay circuit is inserted for each series. At the output of this even-odd deinterleaver 24, a PCM data sequence is obtained having exactly the same arrangement and predetermined transmission channel as that supplied to the input of the error correction encoder. Although not shown in FIG. 3, a correction circuit is provided next to the even-odd deinterleaver 24, and performs correction such as average value interpolation to make errors that cannot be corrected by the decoders 21 and 23 less noticeable. It is done.

In the error correction decoder shown in FIG.
error correction using the check words P ₁₂ , P _12o+1 , P _12o+2 , P _12o+3 and the second check word Q _12o ,
Error correction using Q _12o+1 , Q _12o+2 , and Q _12o+3 is performed once each. If each of these error corrections is performed at least twice (actually, about twice), the error reduction can be utilized more than the corrected result, and the error correction ability can be further increased. can.

Note that in the above example, the delay amount is varied by D as the delay processing in the interleaver 9, but unlike this regular change in the delay amount, it may be irregular. Further, the second check word P _i is an error correction code that includes not only the PCM data but also the first check word Q _i . Similarly, it is also possible for the first check word Q _i to also include the second check word P _i . Specifically, the second check word P _i may be fed back to the encoder that forms the first check word.

〔Effect of the invention〕

As can be understood from the above description, according to the present invention, an error correction code that can correct, for example, a two-word error without using a pointer indicating an error position is used, and cross-interleaving is used. Since the burst errors are dispersed, effective error correction can be performed for both random errors and burst errors. In the error correction code according to the present invention, the decoding algorithm becomes more complicated as the number of correctable error words increases. If only one word error is to be corrected, a decoder with a very simple configuration can be used. Therefore, it is easy to prepare multiple grades of error correction decoders ranging from low to high correction capabilities, and this is suitable for use in cases such as rotary disk playback devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of an error correction encoder to which the present invention is applied, FIG. 2 is a block diagram showing an arrangement during transmission, FIG. 3 is a block diagram of an example of an error correction decoder, and FIGS. FIG. 5 is a diagram used to explain the operation of the decoder of the error correction decoder. 1, 9, 11 are interleavers, 8, 10 are encoders, 16, 22, 24 are deinterleavers, 2
1 and 23 are decoders.

Claims (1)

[Scope of Claims] 1. A first predetermined number of input words each consisting of words included in each of the PCM data series of a first predetermined number of channels in a first arrangement state, each word having m bits is supplied. When F(x) is an irreducible polynomial over the field GF(2), the extended field GF(2 ^m
a first check word, each word of which has m bits, for correcting errors in the first predetermined number of input words by operating each element in the first predetermined number of input words; A second check word sequence is formed by delaying the PCM data sequence of the first predetermined number of channels and the first check word sequence by different times for each channel.
By calculating the second predetermined number of words included in each of the data series in this second array state and each element in the expanded field GF(2 ^m ), forming a second check word sequence, each word of m bits, for correcting errors in the second predetermined number of words; A check word sequence is transmitted, the transmitted data is received, and errors in the received word are corrected, the method comprising: correcting a first error in the received word based on the second check word; At the same time, a pointer indicating the presence or absence of an error is set in the word, and using the pointer indicating the presence or absence of an error, the first
A second error correction process is performed based on the check word, and in the second error correction process, the pointer of the word whose error has been corrected is cleared, and the pointer of the word whose pointer is not cleared is corrected. Characteristic error correction method.