JPH0361380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction method that has high error correction ability for both burst errors and random errors, and that reduces the possibility of missing error detection or making erroneous corrections.

The applicant of the present application has previously proposed a method called cross interleave as a data transmission method effective against burst errors. This generates a first check word sequence by supplying one word included in each of the PCM data sequences of multiple channels in a first alignment state to a first error correction encoder; The check word series of 1 and the PCM data series of multiple channels are
array state, and one word contained in each is the second
the second error correction encoder by feeding
It generates a check word sequence, and performs double interleaving (arrangement rearrangement) on a word-by-word basis. Interleaving distributes and transmits check words and PCM data included in a common error correction block.
This is intended to reduce the number of error words among a plurality of words included in a common error correction block when the original arrangement is restored on the receiving side. In other words, when a burst error occurs during transmission, this burst error can be dispersed. If such interleaving is performed twice,
Since each of the first and second check words constitutes a separate error correction block, even if one of the check words cannot correct an error, the other can be used to correct the error. , Therefore, the error correction ability can be further improved. By the way, if even one bit in one word is erroneous, the entire word is treated as erroneous, so when handling received data with relatively many random errors, it is not always necessary to have sufficient error correction capability. I can't say that.

Therefore, it is possible to detect and correct up to a 2-word error in a predetermined word within one block (maximum number of errors that can be detected and corrected is 2 words), and when the error location is known, it is possible to correct, for example, a 4-word error (the maximum number of errors that can be corrected is 2 words). error correction code (adjacent (b-
(adjacent) code) is combined with the above-mentioned multiple interleaving. Also, this error correction code is
When only one word error is to be corrected, the structure of the decoder can be greatly simplified.

In addition, when decoding the first stage of the second error correction block, then returning to the first arrangement state, and performing the next stage decoding of the first error correction block, even if there is an error in the first stage decoding, If a 4-word error is detected as a 1-word error and an erroneous correction occurs, this error or erroneous correction may cause a new error to be detected in the next stage of decoding. , may cause erroneous corrections, and the risk of these malfunctions occurring as a whole increases.
Furthermore, as the number of error words to be corrected increases, the probability of the above-mentioned missed or erroneous corrections occurring generally increases.

In the present invention, for example, a maximum of 2
Even if word errors can be corrected, the correction is limited to one word error. Along with this, for example, when it is detected in the first stage decoding that two or more words are incorrect, a pointer indicating that there is an error is added, and the state of the pointer indicating this error in the next stage decoding. By determining, for example, up to a 2-word error, the possibility of oversight or erroneous correction in the next stage of decoding is prevented. In this way, the risk of oversight or incorrect correction during error detection and correction can be reduced, and problems such as abnormal noise caused by incorrect correction when transmitting audio PCM signals can be solved. There is. Furthermore, the configuration of the first-stage decoder can be simplified.

First, the error correction code used in the present invention will be explained. When describing an error correction code, a vector representation or a cyclic group representation is used. First, consider an irreducible m-th degree polynomial F(x) on GF(2). A body GF that only has elements of “0” and “1”
On (2), the irreducible polynomial F(x) has no roots. Therefore, consider a virtual root α that satisfies (F(x)=0). At this time, 2 ^m different elements 0, α, α ² , α ³ . . . are expressed as powers of α including the zero element.
α ^2m-1 constitutes the extended field GF(2 ^m ). GF (2 ^m )
is a polynomial ring modulo the m-th order irreducible polynomial F(x) over GF(2). The element of GF (2 ^m ) is 1, α=
It can be expressed as a linear combination of {x}, α ² = {x ² }, ..., α ^m-1 = {x ^m-1 }. That is, a ₀ +a ₁ {x}+a ₂ {x ² }+...+a _n-1 {x ^m-1 }=a ₀ +
a ₁ α + a ₂ α ² +…+a _n-1 α ^m-1 or (a _n-1 , a _n-2 ,…, a ₂ , a ₁ , a ₀ ) where a ₀ , a ₁ ,…, a _n-1 ∈GF(2).

As an example, considering GF(2 ⁸ ), (mod.F
(x) = x ⁸ + x ⁴ + x ³ + x ² + 1), and all 8-bit data is a ₇ x ⁷ + a ₆ x ⁶ + a ₅ x ⁵ + a ₄ x ⁴ + a ₃ x ³ + a ₂ x ² + a ₁ x + a ₀ Or it can be written as (a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ , a ₀ ), so for example, a ₇ is on the MSB side and a ₀ is on the LSB side.
Assign to the side. a _o belongs to GF(2), so 0
Or 1.

Further, the following (m×m) matrix T is derived from the polynomial F(x).

T=0 1 0 〓 0 0 0 1 〓 0 ... ... ... ... 0 0 0 〓 ₁ a 0 a ₁ a ₂ 〓 a _n-1 Another expression uses a cyclic group. This takes advantage of the fact that the 0 element is removed from GF(2 ^m ) and the remaining elements form a multiplicative group of order 2 ^m -1. When the elements of GF(2 ^m ) are expressed using a cyclic group, they become 0, 1 (=α ^2m-1 ), α, α ² , α ³ , . . . α ^2m-2 .

Now, in one example of the present invention, when m bits are one word and n words constitute one block, k check words are generated based on the parity check matrix H below.

H=1 α ^n-1 α ^2(n-1) 〓 α ^(k-1)(n-1) 1 α _o-2 α ^2(n-2) 〓 α ^(k-1)(n-2) … … … … 1 α α ² 〓 α ^k-1 1 1 1 〓 1 Furthermore, the parity check matrix H can be similarly expressed using the matrix T.

H=I T ^n-1 T ^2(n-1) 〓 T ^(k-1)(n-1) I T ^n-2 T ^2(n-2) 〓 T ^(k-1)(n-2) … … … … I T ¹ T ² 〓 T ^k-1 I I I 〓 I However, I is a (m×m) unit matrix.

As mentioned above, the expression using the root α and the generation matrix T
Expressions using are similar to each other.

For example, if we use four (k=4) check words, the parity check matrix H is H=1 α ^n-1 α ^2(n-1) α ^3(n-1) 1 α ^{n -2} α ^2(n-2) α ^3(n-2) … … … … 1 α α ² α ³ 1 1 1 1. One block of received data is expressed as a column vector V
= (W^ _o-1 , W^ _o-2 , ..., W^ ₁ , W^ ₀ ) (however, W^i=Wi
ei, ei: error pattern), the four syndromes S ₀ , S ₁ , S _{2 ,} and S ₃ that occur on the receiving side become S ₀ S ₁ S ₂ S ₃ =H· ^VT . This error correction code has the ability to correct errors up to 4 words. In other words, it is possible to detect and correct errors up to 2-word errors in one error correction block, and when the error location is known, it is possible to detect and correct errors up to 3-word errors or 4-word errors.
Word errors can be corrected.

4 check words in 1 block (p=
W ₃ , q=W ₂ , r=W ₁ , s=W ₀ ).
This check word is obtained as follows. However, Σ means _o-1 〓 ⁱ⁼⁴ .

p+q+r+s=ΣWi=a α ³ p+α ² q+αr+s=Σα ⁱ Wi=b α ⁶ p+α ⁴ q+α ² r+s=Σα ²ⁱ Wi=c α ⁹ p+α ⁶ q+α ³ r+s=Σα ³ⁱ Wi=d Omit the calculation process and only the result , p q r s=α ²¹² α ¹⁵³ α ¹⁵² α ²⁰⁹ α ¹⁵⁶ α ² α ¹³⁵ α ¹⁵² α ¹⁵⁸ α ¹³⁸ α ² α ¹⁵³ α ²¹⁸ α ¹⁵⁸ α ¹⁵⁶ α ²¹² a b c d . In this way, check words p, q,
The role of the encoder provided on the transmitting side is to form r and s.

Next, a basic algorithm for error correction when data containing check words formed as described above is transmitted and received will be described.

[1] When there is no error: S ₀ = S ₁ = S ₂ = S ₃ = 0 [2] When there is a 1-word error (error pattern is ei): S ₀ = ei S ₁ = α ⁱ ei S ₂ = α ²ⁱ ei S ₃ =
α ³ⁱ ei Therefore, α ⁱ S ₀ = S ₁ α ⁱ S ₁ = S ₂ α ⁱ S ₂ = S ₃ , and when i is changed sequentially, whether the above relationship holds or not is a one-word error. It is possible to determine whether Alternatively, S ₁ /S ₀ =S ₂ /S ₁ =S ₃ /S ₂ =α ⁱ , and the error location i can be found by referring to the conversion table previously stored in the ROM for the pattern of α ⁱ . The syndrome S ₀ at that time becomes the error pattern ei itself.

[3] In the case of two-word error (ei, ej) S ₀ = ei + ej S ₁ = α ⁱ ei + α ^j ej S ₂ = α ²ⁱ ei + α ^2j ej S ₃ = α ³ⁱ ei + α ^3j ej Transforming the above equation, α ^j S ₀ +S ₁ = (α ⁱ + α ^j )ei α ^j S ₁ +S ₂ = α ⁱ (α ⁱ +α ^j )ei α ^j S ₂ +S ₃ = α ²ⁱ (α ⁱ +α ^j )ei Therefore α ⁱ (α ^j If S ₀ +S ₁ )=α ^j S ₁ +S ₂ α ⁱ (α ^j S ₁ +S ₂ )=α ^j S ₂ +S ₃ holds, it is determined that there is a two-word error, and the error locations i and j are known. In other words, i
By changing the combination of and j, check whether the relationship in the above equation holds true. The error pattern at that time is ei=S ₀ +α ^-j S ₁ /1+α ^ij ej=S ₀ +α ^-i S ₁ /
1 + α ^ji [4] In case of 3 word error (ei, ej, ek) S ₀ = ei + ej + ek S ₁ = α ⁱ ei + α ^j ej + α ^k ek S ₂ = α ²ⁱ ei + α ^2j ej + α ^2k ek S ₃ = α ³ⁱ ei + α ^3j ej + α ^3k ek Transforming the above equation, α ^k S ₀ + S ₁ = (α ⁱ + α ^k ) ei + (α ^j + α ^k ) ej α ^k S ₁ + S ₂ = α ⁱ (α ⁱ + α ^k ) ei + α ^j (α ^j + α ^k ) ej α ^k S ₂ + S ₃ = α ²ⁱ (α ⁱ + α ^k )ei + α ^2j (α ^j + α ^k )e
j Therefore, α ^j (α ^k S ₀ + S ₁ ) + α ^k S ₁ + S ₂ ) = (α ⁱ + α ^j ) (α ⁱ + α ^k )ei α ^j (α ^k S ₁ + S ₂ ) + (α ^k S ₂ + S ₃ ) = α ⁱ (α ⁱ + α ^j ) (α ⁱ + α ^k ) ei From the above equation, α ⁱ (α ^j (α ^k S ₀ + S ₁ ) + (α ^k S ₁ + S ₂ )) = α ^j ( If α ^k S ₁ +S ₂ ) + (α ^k S ₂ +S ₃ ) holds true, it can be determined that there is a 3-word error.
However, the condition is that (S ₀ ≠0, S ₁ ≠0, S ₂ ≠0). At that time, each error pattern is ei=S ₀ +(α ^-j +α ^-k )S ₁ +α ^-jk S ₂ /(1+α ^ij
) (1+α ^ik ) ej=S ₀ + (α ^-k +α ^-i ) S ₁ +α ^-ki S ₂ / (1+α ^ji
) (1 + α ^jk ) ek = S ₀ + (α ^-i + α ^-j ) S ₁ + α ^-ij S ₂ / (1 + α ^ki
)(1+α ^ki ). In reality, the configuration for correcting a 3-word error becomes complicated, and the time required for the correction operation also increases. Therefore, it is practical to perform the error correction operation by combining the case where the error locations of i, j, k, and l are known by the pointer and using the above equation for checking at that time.

[5] In the case of 4-word error (ei, ej, ek, el): S ₀ = ei + ej + ek + el S ₁ = α ⁱ ei + α ^j ej + α ^k ek + α ^l el S ₂ = α ²ⁱ ei + α ^2j ej + α ^2k ek + α ^2l el S ₃ = α ³ⁱ ei＋α ^3j ej＋α ^3k ek＋α ^3l el Transforming the above equation, ei＝S ₀ + (α ^-j +α ^-k +α ^-l )S ₁ + (α ^-jk
+α ^-kl +α ^-lj )S ₂ +α ^-jkl S ₃ /(1+α ^ij )(
1 + α ^ik ) (1 + α ^il ) ej=S ₀ + (α ^-k + α ^-l + α ^-i ) S ₁ + (α ^-kl
+α ^-li +α ^-ik )S ₂ +α ^-kli S ₃ /(1+ ^αji )(
1 + α ^jk ) (1 + α ^jl ) ek = S ₀ + (α ^-l + α ^-i + α ^-j ) S ₁ + (α ^-li
+α ^-ij +α ^-jl )S ₂ +α ^-lij S ₃ /(1+α ^ki )(
1 + α ^kj ) (1 + α ^kl ) el=S ₀ + (α ^-i + α ^-j + α ^-k ) S ₁ + (α ^-ij
+α ^-jk +α ^-ki )S ₂ +α ^-ijk S ₃ /(1+α ^li )(
1+α ^lj ) (1+α ^lk ) pointer to the error location (i,
j, k, l) is known, error correction can be performed by the above-mentioned calculation.

The basic error correction algorithm described above uses syndromes S ₀ to _{S 3} to check for errors in the first step, check to see if there is a 1-word error in the second step, and check to see if there is a 2-word error in the third step. When trying to correct even a 2-word error, it takes a long time to complete all the steps, and this problem especially occurs when determining the error location of a 2-word error. arise. Therefore, a modified algorithm that does not cause such a problem and is effective when correcting a two-word error will be described below.

The formulas for the syndromes S ₀ , S ₁ , S ₂ , and S ₃ in the case of two-word errors (ei, ej) are as before: S ₀ = ei + ej S ₁ = α ⁱ ei + α ^j ej S ₂ = α ²ⁱ ei + α ^2j ej S ₃ = α ³ⁱ ei + α ^3j ej Transforming this equation (α ⁱ S ₀ + S ₁ ) (α ⁱ S ₂ + S ₃ ) = (α ⁱ S ₁ + S ₂ ) ^2Further transformation yields the error location polynomial below. seek.

(S ₀ S ₂ + S ₁ ² ) α ²ⁱ + (S ₁ S ₂ + S ₀ S ₃ ) α ⁱ + (S ₁ S ₃ + S ₂ ² )=0 Here, the coefficient of each equation is S ₀ S ₂ + S ₁ ² = A S ₁ S ₂ + S ₀ S ₃ = B S ₁ S ₃ + S ₂ ² = C. By using the coefficients A, B, and C in the above equation, the error location in the case of a two-word error can be determined.

[1] When there is no error: A=B=C=0, S ₀ =
0, S ₃ = 0 [2] In case of 1-word error: A 1-word error is determined when A=B=C=0, S ₀ ≠0, and S ₃ ≠0. (α ⁱ =
The error location i is found from S ₁ /S ₀ ), and error correction is performed using (ei = S ₀ ).

[3] In the case of a 2-word error: In the case of an error of 2 or more words, (A≠0,
B≠0, C≠0) holds, and the determination becomes extremely simple. Further, at this time, Aα ²ⁱ +Bα ⁱ +C=0 (where i=0 to (n-1)) holds true. Here, if we set (B/A=D, C/A=E), then D=α ⁱ +α ^j and E=α ⁱ ·α ^j , so that α ²ⁱ +Dα ⁱ +E=0. Here, if the difference between the two error locations is t, that is, (j=i+t), then it is transformed as D=α ⁱ (1+α ^t ) and E=α ^2i+t . Therefore, D ² /E=(1+α ^t ) ² /α ^t = α ^−t + α ^t . The value of (α ^{- t} + α ^t ) for each of (t = 1 to (n-1)) is written in advance in the ROM, and the value of (D ² /E) calculated from the ROM output and the received word is t can be found by detecting a match. If this matching relationship does not hold, there is an error of three or more words. Therefore, by setting X=1+α ^t Y=1+α ^−t =D ² /E+X, α ⁱ =D/X, α ^j =D/Y, and error locations i and j can be found. The error patterns ei and ej are calculated as ei=(α ^j S ₀ +S ₁ )/D=S ₀ /Y+S ₁ /D ej=(α ⁱ S ₀ +S ₁ )/D=S ₀ /X+S ₁ /D, Error correction can be performed.

The modified correction algorithm described above can significantly reduce the time required to determine the error location when correcting a two-word error, compared to the basic algorithm.

Incidentally, if the number k of check words is further increased, the error correction ability is further improved. For example, if (k=6), it has error correction capability of up to 6 words. That is, up to 3 word errors can be detected and corrected, and when the error location is known, up to 6 word errors can be corrected.

Hereinafter, a specific example in which the present invention is applied to recording and reproducing audio PCM signals will be described with reference to the drawings. FIG. 1 shows the entirety of an error correction encoder provided in a recording system, and an audio PCM signal is supplied to its input side. audio
The PCM signal is formed by sampling each of the left and right stereo signals at a sampling frequency f _s (for example, 44.1 [kHz]) and converting one sample into one word (16 bits in two's complement code). ing. Therefore, for the audio signal of the left channel, PCM data in which each word is continuous is obtained as (L ₀ , L ₁ , L ₂ ...), and for the audio signal of the right channel, it is also obtained as (R ₀ , R ₁ , R _{2 )} . …)
PCM data in which each word is consecutive is obtained.
This left and right channel PCM data is divided into 6 channels each, for a total of 12 channels.
A PCM data series is input. At a given timing, (L _6o , R _6o , L _6o+1 , R _6o+1 , L _6o+2 ,
R _6o+2 , L _6o+3 , R _6o+3 , L _6o+4 , R _6o+4 , L _6o+5 ,
12 words of R _6o+5 ) are input. In this example,
One word is divided into upper 8 bits and lower 8 bits, and 12 channels are further processed as 24 channels. For simplicity, one word of PCM data is expressed as Wi, and for the upper 8 bits,
The suffixes Wi, A and A are added, and the lower 8 bits are distinguished by the suffixes Wi, B and B added. For example, L _6o is divided into two parts, W _12o , A and W _12o , B.

These 24 channels of PCM data series are first supplied to the even-odd interleaver 1. (n=
0, 1, 2...), then L _6o (=W _12o,A ,
W _12o,B ), R _6o (=W _12o+1,A , W _12o+1,B ), L _6o+2 (=
W _12o+4,A , W _12o+4,B ), R _6o+2 (=W _12o+5,A ,
W _12o+5,B ), L _6o+4 (=W _12o+8,A , W _12o+8,B ), R _6o+4
(=W _12o+9,A , W _12o+9,B ) are even-numbered words, and the others are odd-numbered words.
Each of the PCM data series consisting of even-numbered words is transmitted to the 1-word delay circuits 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5 of the even-odd interleaver 1.
It is delayed by one word by B, 6A, 6B, 7A, and 7B. Of course, more than one word, for example eight words, may be delayed. Furthermore, in the even-odd interleaver 1, 12 data sequences consisting of even-numbered words occupy the first to 12th transmission channels, and 12 data sequences consisting of odd-numbered words occupy the first to twelfth transmission channels.
data series are converted to occupy the 13th to 24th transmission channels.

The even-odd interleaver 1 is provided to prevent errors in two or more consecutive words of each of the left and right stereo signals, and to prevent these errors from becoming uncorrectable. For example, considering three consecutive words (L _i-1 , L _i , L _i+1 ), L _i is incorrect,
However, if this error is uncorrectable, L _i-1 or
It is desired that L _i+1 is correct. When correcting erroneous data L _i , it is possible to interpolate L _i using the previous correct word L _i-1 (previous value hold), or use the average value of L _i-1 and L _i+1 . This is to interpolate L _i . The delay circuits 2A, 2B to 7A, 7B of the even-odd interleaver 1 are provided to ensure that adjacent words are included in different error correction blocks. Furthermore, the reason why transmission channels are grouped into data sequences consisting of even-numbered words and data sequences consisting of odd-numbered words is that when interleaving is performed, the records of adjacent even-numbered words and odd-numbered words are This is to make the distance between the positions as large as possible.

At the output of the even-odd interleaver 1, a PCM data sequence of 24 channels in the first arrangement state appears, one word is extracted from each of them and supplied to the encoder 8, and the first check word Q _12o ,
Q _12o+1 , Q _12o+2 , Q _12o+3 are formed. The first error correction block including the first check words is (W _12o-12,A , W _12o-12,B , W _12o+1-12,A ,
W _12o+1-12,B , W _12o+4-12,A , W _12o+4-12,B ,
W _12o+5-12,A , W _12o+5-12,B , W _12o+8-12,A ,
W _12o+8-12,B , W _12o+9-12,A , W _12o+9-12,B , W _12o+2,A ,
W _12o+2,B , W _12o+3,A , W _12o+3,B , W _12o+6,A ,
W _12o+6,B , W _12o+7,A , W _12o+7,B , W _12o+10,A ,
W _12o+10,B , W _12o+11,A , W _12o+11,B , Q _12o , Q _12o+1 ,
Q _12o+2 , Q _12o+3 ). In the first encoder 8, the number of words in one block: (n=28) and the number of bits in one word: (n=
8), the number of check words: (k=4) is encoded.

These 24 PCM data sequences and 4 check word sequences are supplied to the interleaver 9. In the interleaver 9, the position of the transmission channel is changed so that a check word sequence is interposed between the PCM data sequence consisting of even-numbered words and the PCM data sequence consisting of odd-numbered words, and then a delay for interleaving is performed. Processing is in progress. This delay processing is performed for each of the other 27 transmission channels excluding the first transmission channel, 1D, 2D, 3D, 4D, ..., 26D, 27D (where D is the unit delay amount, for example 4 This is done by inserting a delay circuit with a delay amount of (word).

At the output of the interleaver 9, 28 data sequences in the second arrangement state appear, and one word is extracted from each data sequence and sent to the encoder 1.
0 and the second check word P _12o ,
P _12o+1 , P _12o+2 , P _12o+3 are formed. The second error correction block consisting of 32 words including the second check word is as follows.

(W _12o-12,A , W _{12o-12(D+1),B} , W _{12o+1-12(2D+1),A} ,
W _{12o+1-12(3D+1),B} , W _{12o+4-12(4D+1),A} ,
W _{12o+4-12(5D+1),B} , W _{12o+5-12(6D+1),A} ,
W _{12o+5-12(7D+1),B} ,...Q _12o-12(12D) ,Q _{12o+1-12(13D)}
,
Q _{12o+2-12(14D)} , Q _{12o+3-12(15D)} ,...W _{12o+10-12(24D),
A} ,
W _{12o+10-12(25D),B} , W _{12o+11-12(26D),A} ,
32 _{including such} first and _{second check words}
An interleaver 11 in which a one-word delay circuit is inserted is provided for the even-numbered transmission channel among the data sequences, and inverters 12 and 1 are provided for the second check word sequence.
3, 14, and 15 are inserted. interleaver 1
1 takes care of the fact that an error that spans the boundary between blocks is likely to result in an error in the number of words that cannot be corrected. In addition, inverters 12 to 1
5 becomes 1 due to dropout during transmission.
This is provided to prevent a malfunction in which all data in the block becomes "0" and the reproduction system determines this as correct. For the same purpose, an inverter may also be inserted for the first check word series.

Then, each of the 32 words extracted from each of the 24 PCM data sequences and 8 check word sequences that are finally obtained is serialized, and as shown in Figure 2, 16-bit synchronization is placed at the beginning. A signal is added to form one transmission block and transmitted. In FIG. 2, one word extracted from the i-th transmission channel is shown as u _i for simplicity of illustration. Specific examples of transmission systems include magnetic recording and reproducing devices, rotating disk devices, and the like.

The encoder 8 described above is related to the error correction code as described above, (n=28, m=8, k=4)
and a similar encoder 10 has (n=32, m=8,
k=4).

The reproduced data is applied to the input of the error correction decoder shown in FIG. 3 every 32 words of one transmission block. Since this is playback data, it may contain errors. In the absence of errors, the 32 words applied to the input of this decoder will match the 32 words that appear at the output of the error correction encoder.
The error correction encoder performs deinterleaving processing corresponding to the interleaving processing in the encoder to restore the data order and then perform error correction.

First, a deinterleaver 1 in which a 1-word delay circuit is inserted for odd-numbered transmission channels.
Further, inverters 17, 18, 19, and 20 are inserted for the check word sequence, and the check word sequence is supplied to the first stage decoder 21. Decoder 21
Now, as shown in Figure 4, the parity check matrix
Syndromes S ₁₀ , S ₁₁ , S ₁₂ , and S ₁₃ are generated from H _c1 and the input 32 words (V ^T ), and error correction is performed based on these syndromes. α is (F(x)=x ⁸
+x ⁴ +x ³ +x ² +1) is the element of GF(2 ⁸ ). From the decoder 21, 24 PCM data sequences and 4 check word sequences appear, and for each word of this data sequence, at least a 1-bit pointer indicating the presence or absence of an error (if there is an error, it is set to "1"). , otherwise, "0") is added. In FIG. 4 and FIG. 5, which will be described later, as well as in the following explanation, one received word W^i is simply represented as Wi.

The output data sequence of this decoder 21 is supplied to a deinterleaver 22. Deinterleaver 22
are for canceling the delay processing performed by the interleaver 9 in the error correction encoder, and are applied to each of the channels from the first transmission channel to the 27th transmission channel (27D, 26D, 25D,
...2D, 1D) and delay circuits with different delay amounts are inserted. The output of the deinterleaver 22 is supplied to a decoder 23 at the next stage. In the decoder 23, as shown in _FIG.
and 28 words of input and from, syndrome S ₂₀ ,
S ₂₁ , S ₂₂ , and S ₂₃ are generated, and error correction is performed based on them.

The data sequence appearing at the output of the next-stage decoder 23 is supplied to an even-odd deinterleaver 24.
In the even-odd deinterleaver 24, the PCM data series consisting of even-numbered words and the PCM data series consisting of odd-numbered words are returned so that they are located on different transmission channels, and the PCM data series consisting of odd-numbered words is A 1-word delay circuit is inserted for each series. At the output of this even-odd deinterleaver 24, a PCM data sequence is obtained having exactly the same arrangement and predetermined transmission channel as that supplied to the input of the error correction encoder. Although not shown in FIG. 3, a correction circuit is provided next to the even-odd deinterleaver 24, and performs correction such as average value interpolation to make errors that cannot be corrected by the decoders 21 and 23 less noticeable. will be carried out.

In one example of the present invention, the first stage decoder 21 corrects up to one word error. Then, within one error correction block, 2
If it is detected that there is an error in more than one word, add at least a 1-bit pointer indicating that there is an error to all 32 words in this error correction block or 28 words excluding the check word. . For example, this pointer is set to "1" when there is an error, and "0" otherwise. Note that a pointer indicating that an error exists may be added even when the above-mentioned predetermined number of words is corrected during first-stage decoding. When one word is 8 bits, a pointer is added as one bit above the most significant bit, making one word 9 bits, processed by the deinterleaver 22, and supplied to the next stage decoder 23. Ru.

The next stage decoder 23 performs error correction using the number of error words or error location in the first error correction block indicated by this pointer. FIG. 6 shows an example of error correction in the next-stage decoder 23. In FIG. 6 and the following explanation, the number of error words caused by the pointer is expressed as N _p , and the error location caused by the pointer is expressed as E. Represented by _i . Also,
In FIG. 6, Y represents affirmation and N represents negation. Since the next-stage decoder 23 detects and corrects up to 2-word errors, a modified algorithm is preferable as the error correction algorithm. That is, at the beginning of the flowchart shown in FIG. 6, the above-mentioned error location polynomial (Aα ²ⁱ +Bα ⁱ +C=0) is calculated, and each coefficient A, B, C and syndromes S ₂₀ to _{S 23} are used to calculate the error location polynomial (Aα 2i +Bα i +C=0). Error correction will be performed. At the same time, the total number N _p of pointers indicating errors included in one block is counted. Of course, it is also possible to use a basic algorithm that uses syndromes to detect the absence of errors, detect 1-word errors, and detect 2-word errors step by step, as shown by the broken line in FIG.

(1) Check for errors. (A=B=
C=0, S ₂₀ =0, S ₂₃ =0), it is assumed that there is no error. In that case, check whether (N _p ≦z ₁ ). If (N _p ≦z ₁ ), it is determined that there is no error, and the pointer in the error correction block is cleared (“0”). If (N _p > z ₁ ), it is determined that the syndrome detection is incorrect, and either the pointer is left as is or the pointers of all words in the block are set to "1". As z ₁ , it is quite large, for example, 14.

(2) Check whether there is a one-word error. (A=B
= C = 0, S ₂₀ ≠ 0, S ₂₃ ≠ 0), it is tentatively determined to be a one-word error, and the error location i is determined from (S ₂₁ /S ₂₀ =α ⁱ ). It is detected whether this error location i corresponds to that by the pointer. If there are multiple error locations by pointers, it is checked to see if they match any of them. If (i=E _i ), then it is checked whether (N _p ≦z ₂ ).
z ₂ is, for example, 10. If (N _p ≦z ₂ ), then
It is determined that it is a one-word error, and error correction is performed using (e _i =S ₂₀ ). (i=E _i ), but
If (N _p > z ₂ ), the number of pointers is too large for a one-word error, so it is judged that it is dangerous to judge it as a one-word error.
Either leave the pointers as they are, or treat all words as errors and set each word's pointer to "1".

If (i≠E _i ), it is checked whether (N _p ≦z ₃ ). z ₃ is a fairly small number, for example 3
It is. When (N _p ≦z ₃ ) holds, the one-word error at error location i is corrected in the syndrome calculation.

In the case of (N _p > z ₃ ), it is further checked whether (N _p ≦z ₄ ). That is, (z ₃ <N _p ≦z ₄ )
When , it means that N _p is too small considering that the one-word error due to the syndrome is incorrectly determined, so the pointers of all words in that block are set to "1". On the contrary (N _p > z ₄ )
If so, leave the pointer as is.

(3) Check whether there is a 2-word error. If it is a two-word error, the error location (i, j) is detected by calculation. (A≠0,
When B≠0, C≠0), it is determined that there is a two-word error, and the error location (i, j) is determined by (α ⁱ =D/X, α ^j =D/Y). A match between the error locations i, j and the error locations Ei, Ej by pointers is detected. When (i=Ei, j=Ej), the number of pointers indicating an error is compared with a predetermined value _z5 .
If (Np≦z ₅ ), error location i,
The two word error for j is corrected. This correction is performed by finding the error patterns ei and ej as described above. When (Np>z ₅ ),
For example, since there is a high possibility that an error of three or more words is mistakenly detected as a two-word error, no correction is made and the pointer is left as is, or all words in the block are marked as errors.

When checking the error location, (i=Ei, J≠Ej) or (i≠Ei, j=Ej)
When any of the relationships holds true, (Np≦z ₆ )
It can be checked whether When (Np≦z ₆ ),
A two-word error regarding error locations i and j is corrected. When (Np>z ₆ ),
It can be checked whether (Np≦z ₇ ). This is to check the number of pointers indicating an error when the error location relationship is partially established. If (Np≦z ₇ ), the number of pointers indicating an error is small. It is determined that the block is too large, and the pointers of all words in that block are set to "1". When (Np>z ₇ ), the reliability of the pointer is considered to be high, so the pointer is left as is.

When (i≠Ei, j≠Ej), it is checked whether (Np≦z ₈ ). When Np is quite small, the result obtained using the error location polynomial is given more weight than the pointer, and two-word errors regarding i and j are corrected. Here, z ₈ is naturally smaller than z ₅ . When (Np>z ₈ ), it is further checked whether (Np≦z ₉ ). this is,
As in the case of (Np≦z ₇ ), this is a check to see whether to leave the pointer of the block as it is or to set the pointers of all words to "1".

(4) If none of the above cases (1), (2), or (3) apply, that is, if there is an error exceeding 2 words, no error correction is performed. Then, it is checked whether (Np≦z ₁₀ ). If (Np≦z ₁₀ ), then
It is determined that the reliability of the pointer is low, and the pointers of all words are set to "1". If (Np>z ₁₀ ), leave the pointer as is.

(5) In the case where there is not a 2-word error, for example, a 3-word error may be corrected using the error location by a pointer, as shown by the * mark. In other words, if (Np=3), the error location (i,
Correct the 3-word error for j, k). When (Np≠3), the pointers are left as they are, or the pointers of all words are set to "1".

Note that the value z _i compared with the total number Np of pointers indicating errors in one block is the probability of incorrect detection of the error correction code (in the above example, if there are 5 or more word errors, this is determined as no error). In addition, if there is a 4-word error or more, there is a risk that it will be determined as a 1-word error, or a 2-word error of 3 or more words). It can be done.

In the error correction decoder shown in FIG. 3 described above, the first check words Q _12o , Q _12o+1 , Q _12o+2 ,
Error correction using Q _12o+3 and error correction using second check words P _12o , P _12o+1 , P _12o+2 , and P _12o+3 are performed once each. If each error correction is performed at least twice (actually, about twice), the error reduction resulting from the correction can be utilized to further increase the error correction ability. can. In this way, when a decoder is provided at a later stage, the decoders 21 and 2
It is also necessary to correct the check word in step 3.

Note that in the above example, the delay amount is varied by D as the delay processing in the interleaver 9, but unlike this regular change in the delay amount, it may be irregular. Further, the second check word P _i is an error correction code that includes not only the PCM data but also the first check word Q _i . Similarly, it is also possible for the first check word Q _i to also include the second check word P _i . Specifically, the second check word P _i may be fed back to the encoder that forms the first check word. Such a feedback type configuration is effective when the number of times of decoding is three or more as described above.

As can be understood from the above description, according to the present invention, in the first stage decoding, the maximum number of detectable and correctable errors determined corresponding to the second check word (error detection and correction is possible without using a pointer). In addition to correcting errors up to a predetermined number that does not reach the maximum number of errors that can be performed, if it is detected that there are at least more than the predetermined number of errors, the existence of errors is detected for all words in the block to be corrected. In the next stage of decoding, if the number of detected errors exceeds 1 and can be corrected using the error location obtained from the error syndrome,
The first error location obtained from the error syndrome generated using the first check word is compared with the second error location based on the above pointer, and it is confirmed that the locations match and the error is detected. Since the error is corrected, detection or correction of erroneous errors can be prevented. Furthermore, even if the first and second error locations do not match, the error location determined from the error syndrome is used only when the number of pointers in the block to be corrected is within a preset value. By using this method to correct errors, error correction efficiency can be improved.

Furthermore, in the first stage decoding, errors up to a predetermined number that does not reach the maximum number of detectable and correctable errors are corrected, so that error correction can be performed using a very simple circuit.

Note that even when a one-word error is corrected in the first stage decoding, if the pointer of each word in the block that includes this corrected word is set to "1", there is a further risk of incorrect error detection and incorrect correction. can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of an error correction encoder to which the present invention is applied, FIG. 2 is a block diagram showing an arrangement during transmission, FIG. 3 is a block diagram of an example of an error correction decoder, and FIGS. 5 and 6 are diagrams used to explain the operation of the decoder of the error correction decoder. 1, 9, 11 are interleavers, 8, 10 are encoders, 16, 22, 24 are deinterleavers, 2
1 and 23 are decoders.

Claims (1)

[Claims] 1. A plurality of channels in a first arrangement state
A first check word consisting of one word included in each PCM data series and a first check word for this word.
An error correction block is formed, and the PCM data sequences of the plurality of channels and the first check word sequence are brought into a second arrangement state by delaying each channel by a different time.
Receive data transmitted as a second error correction block consisting of one word included in each of the PCM data series of the plurality of channels and the first check word series in the arrangement state, and a second check word corresponding thereto. Then, the first stage decoding of the second error correction block is performed using the second check word, and then the PCM data series of multiple channels in the second arrangement state and the first check word series are channel-coded. a first arrangement state by delaying each time for a different time;
This is an error correction method in which the first check word is then used to perform the next stage of decoding for the first error correction block, and in the first stage decoding, the maximum detection value determined corresponding to the second check word is determined. In addition to correcting errors up to a predetermined number that does not reach the number of correctable errors, at least when it is detected that there are more than the predetermined number of errors, the existence of errors is detected for all words in the block to be corrected. In the latter stage decoding, if a one-word error is detected based on the error syndrome, the number of pointers set in the previous stage decoding in the error correction target block is set. performs error correction processing according to the error location determined from the error syndrome when the number is equal to or less than a first preset value, and the number of errors detected based on the error syndrome exceeds 1, and If error correction is possible using the error location obtained from the error syndrome, compare the first error location obtained from the error syndrome with the second error location indicated by the pointer. However, when the first error location matches the second error location, the number of pointers set during the previous stage decoding in the block to be corrected is the second pointer set in advance. If the value is below, correct the error using the first error syndrome,
Even if they do not match, only when the number of pointers set during the previous stage decoding in the error correction target block is within a third value set in advance to be smaller than the second value. , an error correction method characterized in that an error is corrected using an error location determined from the error syndrome.