JPH0353816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction method that has high error correction ability for both burst errors and random errors, and that reduces the possibility of missing error detection or making erroneous corrections.

The applicant of the present application has previously proposed a method called cross interleave as a data transmission method effective against burst errors. This generates a first check word sequence by supplying one word included in each of the PCM data sequences of multiple channels in a first alignment state to a first error correction encoder; The check word series of 1 and the PCM data series of multiple channels are
array state, and one word contained in each is the second
the second error correction encoder by feeding
It generates a check word sequence, and performs double interleaving (arrangement rearrangement) on a word-by-word basis. Interleaving distributes and transmits check words and PCM data included in a common error correction block.
This is intended to reduce the number of error words among a plurality of words included in a common error correction block when the original arrangement is restored on the receiving side. In other words, when a burst error occurs during transmission, this burst error can be dispersed. If such interleaving is performed twice,
Since each of the first and second check words constitutes a separate error correction block, even if one of the check words cannot correct an error, the other can be used to correct the error. , Therefore, the error correction ability can be further improved. By the way, if even one bit in one word is erroneous, the entire word is treated as erroneous, so when handling received data with relatively many random errors, it is not always necessary to have sufficient error correction capability. I can't say that.

Therefore, it is possible to detect and correct up to a 2-word error in a predetermined word within one block (maximum number of errors that can be detected and corrected is 2 words), and when the error location is known, it is also possible to correct 3-word errors or 4-word errors. An error correction code (a type of B-adjacent code) with high correction ability (maximum number of correctable errors: 4 words) is combined with the above-mentioned multiple interleave. Moreover, this error correction code has a feature that the structure of the decoder can be made extremely simple when only one word error is to be corrected.

In addition, when performing first-stage decoding for the second error correction block, then returning to the first arrangement state, and then performing next-stage decoding for the first error correction block, incorrect error detection ( When a detection error (detection error) or erroneous correction occurs, this detection error or erroneous correction becomes a cause of a new detection error or erroneous correction in the next stage of decoding, and the risk of these erroneous operations occurring as a whole increases. Furthermore, as the number of error words to be corrected increases, the probability of the above-mentioned detection errors and erroneous corrections occurring generally increases.

In the present invention, for example, a maximum of 2
Even if word errors can be corrected, the correction is limited to one word error. At the same time, when the first stage decoding detects that two or more words are incorrect, a pointer indicating the error is added, and the next stage decoding determines the state of this pointer. This prevents the risk of detection errors and erroneous corrections during step decoding. In this way, the risk of detection errors and erroneous corrections during error detection and correction is reduced, and problems such as abnormal noises caused by erroneous corrections when transmitting audio PCM signals are solved. are doing. Furthermore, the configuration of the first-stage decoder can be simplified.

First, the error correction code used in the present invention will be explained. When describing an error correction code, a vector representation or a cyclic group representation is used. First, consider an irreducible m-th degree polynomial F(x) on GF(2). A body GF that only has elements of “0” and “1”
On (2), the irreducible polynomial F(x) has no roots. Therefore, consider a virtual root α that satisfies (F(x)=0). At this time, 2 ^m different elements 0, α, α ² , α ³ . . . are expressed as powers of α including the zero element.
...α ^2m-1 constitutes the extended field GF(2 ^m ). GF (2 ^m )
is a polynomial ring modulo the m-th order irreducible polynomial F(x) over GF(2). The element of GF (2 ^m ) is 1, α=
It can be expressed as a linear combination of {x}, α ² = {x ² }...α ^m-1 = {x ^m-1 }. That is, a ₀ +a ₁ {x}+a ₂ {x ² }+...+a _n-1 {x ^m-1 } = a ₀ +a ₁ α+a ₂ α ² +...+a _n-1 α ^m-1 or (a _{n -1} , a _n-2 …a ₂ , a ₁ , a ₀ ) where,
a ₀ , a ₁ ...a _n-1 ∈GF(2).

As an example, considering GF(2 ⁸ ), (mod.F
(x) = x ⁸ + x ⁴ + x ³ + x ² + 1), and all 8-bit data is a ₇ x ⁷ + a ₆ x ⁶ + a ₅ x ⁵ + a ₄ x ⁴ + a ₃ x ³ + a ₂ x ² + a ₁ x+
It is written as a ₀ or (a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ , a ₀ ), so for example, a ₇ is on the MSB side and a ₀ is on the MSB side.
Assign to LSB side. Since a _o belongs to GF(2),
0 or 1.

Further, the following (m×m) matrix T is derived from the polynomial F(x).

T=0 0 ... 0 a ₀ 1 0 ... 0 a ₁ 0 1 ... 0 a ₂ 〓 〓 〓 〓 0 0 ... 1 a _n-1 Another expression uses a cyclic group. This takes advantage of the fact that the 0 element is removed from GF(2 ^m ) and the remaining elements form a multiplicative group of order 2 ^m -1. When expressed using the original cyclic group of GF (2 ^m ), it becomes 0, 1 (=α ^2m −1), α, α ² , α ³ . . . α ^2m −2.

Now, in one example of the present invention, when m bits are one word and n words constitute one block, k check words are generated based on the parity check matrix H below.

H=1 α ^n-1 α ^2(n-1) 〓 α ^(k-1)(n-1) 1 α ^n-2 α ^2(n-2) 〓 α ^(k-1)(n-2) … … …1 α α ² 〓 α ^k-1 1 1 1 〓 1 Furthermore, the validity check matrix H can be similarly expressed using the matrix T.

H= T ^n-1 T ^2(n-1) 〓 T ^(k-1)(n-1) I T ^n-2 T ^2(n-2) 〓 T ^(k-1)(n-2) … … …I T ¹ T ² 〓 T ^k-1 I I I 〓 I However, is an (m×m) unit matrix.

As mentioned above, the expression using the root α and the generation matrix T
Expressions using are similar to each other.

For example, if we use four (k=4) check words, the validity check matrix H is H=1 α ^n-1 α ^2(n-1) α ^3(n-1) 1 α ^{n -2} α ^2(n-2) α ^3(n-2) … … …1 α α ² α ³ 1 1 1 1. One block of received data is expressed as a column vector V
= (W^ _o-1 , W^ _o-2 ...W^ ₁ , W^ ₀ ) (However, W^ _i = Wi + e _i ,
e _i : error pattern), 4 occurs on the receiving side
The syndromes S ₀ , S ₁ , S ₂ , and S ₃ become S ₀ S ₁ S ₂ S ₃ =H· ^VT . This error correction code has the ability to correct errors up to 4 words. In other words, it is possible to detect and correct errors up to 2-word errors in one error correction block, and when the error location is known, it is possible to detect and correct errors up to 3-word errors or 4-word errors.
Word errors can be corrected.

4 check words in 1 block (p=
W ₃ , q=W ₂ , r=W ₁ , s=W ₀ ).
This check word can be obtained by solving the following four-dimensional simultaneous equations. However, Σ means _o-1 〓 ⁱ⁼⁴ .

p+q+r+s=ΣW _i =a α ³ p+α ² q+αr+s=Σα ⁱ W _i =b α ⁶ p+α ⁴ q+α ² r+s=Σα ²ⁱ W _i =c α ⁹ p+α ⁶ q+α ³ r+s=Σα ³ⁱ W _i =d Skip the calculation process However, if only the results are shown, p q r s=α ²¹² α ¹⁵³ α ¹⁵² α ²⁰⁹ α ¹⁵⁶ α ² α ¹³⁵ α ¹⁵² α ¹⁵⁸ α ¹³⁸ α ² α ¹⁵³ α ²¹⁸ α ^{158 α 156 α 212 a} b c d . In this way, check words p, q,
The role of the encoder provided on the transmitting side is to form r and s.

Next, a basic algorithm for error correction when data containing check words formed as described above is transmitted and received will be described.

[1] When there is no error: S ₀ = S ₁ = S ₂ = S ₃ = 0 [2] When there is a 1-word error (the error pattern at error location i is e _i ): S ₀
= e _i S ₁ = α ⁱ e _i S ₂ = α ²ⁱ e _i S ₃ = α ³ⁱ e _i Therefore, α ⁱ S ₀ = S ₁ α ⁱ S ₁ = S ₂ α ⁱ S ₂ = S ₃ , When i is sequentially changed, it can be determined whether a one-word error has occurred based on whether this relationship holds. Alternatively, S ₁ /S ₀ =S ₂ /S ₁ =S ₃ /S ₂ =α ⁱ , and the error location i can be found by referring to the conversion table previously stored in the ROM for the pattern of α ⁱ . The syndrome S ₀ at that time becomes the error pattern e _i itself.

[3] In the case of two-word error (e _i , e _j ) S ₀ = e _i + e _j S ₁ = α ⁱ e _i + α ^j e _j S ₂ = α ²ⁱ e _i + α ^2j e _j S ₃ = α ³ⁱ e _i +α ^3j e _{jTransforming} the above equation, α ^j S ₀ +S ₁ = (α ⁱ + α ^j )e _i α ^j S ₁ +S ₂ = α ⁱ (α ⁱ +α ^j )e _i α ^j S ₂ +S ₃ = α ²ⁱ (α ⁱ + α ^j ) e _i Therefore, if α ⁱ (α ^j S ₀ + S ₁ ) = α ^j S ₁ + S ₂ α ⁱ (α ^j S ₁ + S ₂ ) = α ^j S ₂ + S ₃ holds. , it is determined that there is a 2-word error, and the error locations i and j are known. In other words, i
By changing the combination of and j, check whether the above relationship holds. The error pattern at that time is e _i = S ₀ + α ^-j S ₁ /1 + α ^ij e _j = S ₀ + α ^-i S
₁ / 1 + α ^ji [4] In the case of 3-word error (e _i , e _j , e _k ): S ₀ = e _i , e _j , e _k S ₁ = α ⁱ e _i + α ^j e _j + α ^k e _k S ₂ = α ²ⁱ e _i + α ^2j e _j + α ^2k e _k S ₃ = α ³ⁱ e _i + α ^3j e _j + α ^3k e _k Transforming the above equation, α ^k S ₀ + S ₁ = (α ⁱ + α ^k ) e _i + (α _j + α ^k ) e _j α ^k S ₁ + S ₂ = α ⁱ (α ⁱ + α ^k ) e _i + α ^j (α ^j + α ^k ) e _j α ^k S ₂ + S ₃ = α ²ⁱ (α ⁱ + α ^k ) e _i + α ^2j (α ^j + α ^k ) e _j Therefore, α ^j (α ^k S ₀ + S ₁ ) + (α ^k S ₁ + S ₂ ) = (α ⁱ + α ^j ) (α ⁱ + α ^k ) e _i α ^j (α ^k S ₁ + S ₂ ) + (α ^k S ₂ + S ₃ ) = α ⁱ (α ⁱ + α ^j ) (α ⁱ + α ^k ) e _{iFrom the} above equation, α ⁱ α ^j (α ^k S ₀ + S ₁ ) + (α ^k S ₁ + S ₂ )) = α ^j (α _k S ₁ + S ₂ ) + (α ^k S ₂ + S ₃ ), it can be determined that there is a 3-word error.
However, the condition is that (S ₀ ≠0, S ₁ ≠0, S ₂ ≠0). At that time, each error pattern is e _i = S ₀ + (α ^-j + α ^-k ) S ₁ + α ^-jk S ₂ / (1 + α ^ij
)(1+α ^ik ) e _j =S ₀ +(α ^-k +α ^-i )S ₁ +α ^-ki S ₂ /(1+α ^ji
) (1 + α ^jk ) e _k = S ₀ + (α ^-i + α ^-j ) S ₁ + α ^-ij S ₂ / (1 + α ^ki
)(1+α ^ki ). In reality, the configuration for correcting a 3-word error becomes complicated, and the time required for the correction operation also increases. Therefore, it is practical to combine this with the case where the error locations of i, j, k, and l are known by pointers, and use the above equation for checking at that time to perform error correction calculations.

[5] In the case of 4-word error (e _i , e _j , e _k , e _l ): S ₀ = e _i + e _j + e _k + e _l S ₁ = α ⁱ e _i + α ^j e _j + α ^k e _k + α ^l e _l S ₂ = α ²ⁱ e _i + α ^2j e _j + α ^2k e _k + α ^2l e _l S ₃ = α ³ⁱ e _i + α ^3j e _j + α ^3k e _k + α ^3l e lTransforming _the above equation gives e _i = S ₀ +(α ^-j +α ^-k +α ^-l )S ₁ +(α ^-jk
+α ^-kl +α ^-lj )S ₂ +α ^-jkl S ₃ /(1+α ^ij )(
1 + α ^ik ) (1 + α ^il ) e _j = S ₀ + (α ^-k + α ^-l + α ^-i ) S ₁ + (α ^-kl
+α ^-li +α ^-ik )S ₂ +α ^-kli S ₃ /(1+ ^αji )(
1 + α ^jk ) (1 + α ^jl ) e _k = S ₀ + (α ^-l + α ^-i + α ^-j ) S ₁ + (α ^-li
+α ^-ij +α ^-jl )S ₂ +α ^-lij S ₃ /(1+α ^ki )(
1 + α ^kj ) (1 + α ^kl ) e _l = S ₀ + (α ^-i + α ^-j + α ^-k ) S ₁ + (α ^-ij
+α ^-jk +α ^-ki )S ₂ +α ^-ijk S ₃ /(1+α ^li )(
1+α ^lj ) (1+α ^lk ) pointer to the error location (i,
j, k, l) is known, error correction can be performed by the above-mentioned calculation.

Incidentally, if the number k of check words is further increased, the error correction ability is further improved. For example, if (k=6), it has error correction capability of up to 6 words. That is, up to 3 word errors can be detected and corrected, and when the error location is known, up to 6 word errors can be corrected.

Hereinafter, a specific example in which the present invention is applied to recording and reproducing audio PCM signals will be described with reference to the drawings. FIG. 1 shows the entirety of an error correction encoder provided in a recording system, and an audio PCM signal is supplied to its input side. audio
The PCM signal is formed by sampling each of the left and right stereo signals at a sampling frequency f _s (for example, 44.1 [kHz]) and converting one sample into one word (16 bits in two's complement code). ing. Therefore, for the audio signal of the left channel, PCM data in which each word is continuous is obtained as (L ₀ , L ₁ , L ₂ ...), and for the audio signal of the right channel, it is also obtained as (R ₀ , R ₁ , R _{2 )} . …)
PCM data in which each word is consecutive is obtained.
This left and right channel PCM data is divided into 6 channels each, for a total of 12 channels.
A PCM data series is input. At a given timing, (L _6o , R _6o , L _6o+1 , R _6o+1 , L _6o+2 ,
L _6o+2 , L _6o+3 , R _6o+3 , L _6o+4 , R _6o+4 , L _6o+5 ,
12 words of R _6o+5 ) are input. In this example,
One word is divided into upper 8 bits and lower 8 bits, and 12 channels are further processed as 24 channels. For simplicity, one word of PCM data is expressed as W _i , and for the upper 8 bits,
W _i , A and A suffixes are added, and the lower 8 bits are distinguished by adding W _i,B and B suffixes. For example, L _6o is W _12o , _A and
It will be divided into two parts: W _{12o and B.}

These 24 channels of PCM data series are first supplied to the even-odd interleaver 1. (n=
0, 1, 2...), then L _6o (=W _12o,A ,
W _12o,B ), R _6o (=W _12o+1,A , W _12o+1,B ), L _6o+2 (=
W _12o+4,A , W _12o+4,B ), R _6o+2 (=W _12o+5,A ,
W _12o+5,B ), L _6o+4 (=W _12o+8,A , W _12o+8,B ), R _6o+4
(=W _12o+9,A , W _12o+9,B ) are even-numbered words, and the others are odd-numbered words.
Each of the PCM data series consisting of even-numbered words is transmitted to the 1-word delay circuits 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5 of the even-odd interleaver 1.
It is delayed by one word by B, 6A, 6B, 7A, and 7B. Of course, more than one word, for example eight words, may be delayed. Furthermore, in the even-odd interleaver 1, 12 data sequences consisting of even-numbered words occupy the first to 12th transmission channels, and 12 data sequences consisting of odd-numbered words occupy the first to twelfth transmission channels.
data series are converted to occupy the 13th to 24th transmission channels.

The even-odd interleaver 1 is provided to prevent errors in two or more consecutive words of each of the left and right stereo signals, and to prevent these errors from becoming uncorrectable. For example, considering three consecutive words (L _i-1 , L _i , L _i+1 ), L _i is incorrect,
However, if this error is uncorrectable, L _i-1 or
It is desired that L _i+1 is correct. When correcting erroneous data L _i , it is possible to interpolate L _i using the previous correct word L _i-1 (previous value hold), or use the average value of L _i-1 and L _i+1 . This is to interpolate L _i . The delay circuits 2A, 2B to 7A, 7B of the even-odd interleaver 1 are provided to ensure that adjacent words are included in different error correction blocks. Furthermore, the reason why transmission channels are grouped into data sequences consisting of even-numbered words and data sequences consisting of odd-numbered words is that when interleaving is performed, the records of adjacent even-numbered words and odd-numbered words are This is to make the distance between the positions as large as possible.

At the output of the even-odd interleaver 1, a PCM data sequence of 24 channels in the first arrangement state appears, one word is extracted from each of them and supplied to the encoder 8, and the first check word Q _12o ,
Q _12o+1 , Q _12o+2 , Q _12o+3 are formed. The first error correction block including the first check words is (W _12o-12,A , W _12o-12,B , W _12o+1-12,A ,
W _12o+1-12,B , W _12o+4-12,A , W _12o+4-12,B ,
W _12o+5-12,A , W _12o+5-12,B , W _12o+8-12,A ,
W _12o+8-12,B , W _12o+9-12,A , W _12o+9-12,B , W _12o+2,A ,
W _12o+2,B , W _12o+3,A , W _12o+3,B , W _12o+6,A ,
W _12o+6,B , W _12o+7,A , W _12o+7,B , W _12o+10,A ,
W _12o+10,B , W _12o+11,A , W _12o+11,B , Q _12o , Q _12o+1 ,
Q _12o+2 , Q _12o+3 ). In the first encoder 8, the number of words in one block: (n=28) and the number of bits in one word: (n=
8), the number of check words: (k=4) is encoded.

These 24 PCM data sequences and 4 check word sequences are supplied to the interleaver 9. In the interleaver 9, the position of the transmission channel is changed so that a check word sequence is interposed between the PCM data sequence consisting of even-numbered words and the PCM data sequence consisting of odd-numbered words, and then a delay for interleaving is performed. Processing is in progress. This delay processing is performed for each of the other 27 transmission channels excluding the first transmission channel, 1D, 2D, 3D, 4D...26D, 27D (however,
D is achieved by inserting a delay circuit with a unit delay of, for example, 4 words.

At the output of the interleaver 9, 28 data sequences in the second arrangement state appear, and one word is extracted from each data sequence and sent to the encoder 1.
0 and the second check word P _12o ,
P _12o+1 , P _12o+2 , P _12o+3 are formed. The second error correction block consisting of 32 words including the second check word is as follows.

(W _12o-12,A , W _{12o-12(D+1),B} , W _{12o+1-12(2D+1),A} ,
W _{12o+1-12(3D+1),B} , W _{12o+4-12(4D+1),A} ,
W _{12o+4-12(5D+1),B} , W _{12o+5-12(6D+1),A} ,
W _{12o+5-12(7D+1),B} ,...Q _12o-12(12D) ,Q _{12o+1-12(13D)}
,
Q _{12o+2-12(14D)} , Q _{12o+3-12(15D)} ,...W _{12o+10-12(24D),
A} ,
W _{12o+10-12(25D),B} , W _{12o+11-12(26D),A} ,
W _{12o+11-12(27D),B} , P _12o , P _12o+1 , P _12o+2 , P _12o+3 )
Of the 32 data sequences including the first and second check words, an interleaver 11 in which a one-word delay circuit is inserted is provided for even-numbered transmission channels, and the second Inverter 12,1 for check word series
3, 14, and 15 are inserted. interleaver 1
1 takes care of the fact that an error that spans the boundary between blocks is likely to result in an error in the number of words that cannot be corrected. In addition, inverters 12 to 1
5 becomes 1 due to dropout during transmission.
This is provided to prevent a malfunction in which all data in the block becomes "0" and the reproduction system determines this as correct. For the same purpose, an inverter may also be inserted for the first check word series.

Then, each of the 32 words extracted from each of the 24 PCM data sequences and 8 check word sequences that are finally obtained is serialized, and as shown in Figure 2, 16-bit synchronization is placed at the beginning. A signal is added to form one transmission block and transmitted. In FIG. 2, one word extracted from the i-th transmission channel is shown as u _i for simplicity of illustration. Specific examples of transmission systems include magnetic recording and reproducing devices, rotating disk devices, and the like.

The encoder 8 described above is related to the error correction code as described above, (n=28, m=8, k=4)
and a similar encoder 10 has (n=32, m=8,
k=4).

The reproduced data is applied to the input of the error correction decoder shown in FIG. 3 every 32 words of one transmission block. Since this is playback data, it may contain errors. In the absence of errors, the 32 words applied to the input of this decoder will match the 32 words that appear at the output of the error correction encoder.
The error correction decoder performs deinterleaving processing corresponding to the interleaving processing in the encoder to restore the data order and then perform error correction.

First, a deinterleaver 1 in which a 1-word delay circuit is inserted for odd-numbered transmission channels.
Further, inverters 17, 18, 19, and 20 are inserted for the check word sequence, and the check word sequence is supplied to the first stage decoder 21. Decoder 21
Now, as shown in Figure 4, the parity check matrix
Syndromes S ₁₀ , S ₁₁ , S ₁₂ , and S ₁₃ are generated from H _C1 and the input 32 words (V ^T ), and error correction is performed based on these syndromes. α is (F(x)=x ⁸
+x ⁴ +x ³ +x ² +1) is the element of GF(2 ⁸ ). From the decoder 21, 24 PCM data sequences and 4 check word sequences appear, and for each word of this data sequence, at least a 1-bit pointer indicating the presence or absence of an error (“1” when an error is included) is provided. , otherwise, "0") is added. In FIG. 4 and FIG. 5, which will be described later, and in the following description, one received word ^W _i is simply represented as W _i .

The output data sequence of this decoder 21 is supplied to a deinterleaver 22. Deinterleaver 22
are for canceling the delay processing performed by the interleaver 9 in the error correction encoder, and are applied to each of the channels from the first transmission channel to the 27th transmission channel (27D, 26D, 25D).
...2D, 1D) and delay circuits with different delay amounts are inserted. The output of the deinterleaver 22 is supplied to a decoder 23 at the next stage. In the decoder 23, as shown in _FIG.
and 28 words of input and from, syndrome S ₂₀ ,
S ₂₁ , S ₂₂ , and S ₂₃ are generated, and error correction is performed based on them.

The data sequence appearing at the output of the next-stage decoder 23 is supplied to an even-odd deinterleaver 24.
In the even-odd deinterleaver 24, the PCM data series consisting of even-numbered words and the PCM data series consisting of odd-numbered words are returned so that they are located on different transmission channels, and the PCM data series consisting of odd-numbered words is A 1-word delay circuit is inserted for each series. At the output of this even-odd deinterleaver 24, a PCM data sequence is obtained having exactly the same arrangement and predetermined transmission channel as that supplied to the input of the error correction encoder. Although not shown in FIG. 3, a correction circuit is provided next to the even-odd deinterleaver 24, and performs correction such as average value interpolation to make errors that cannot be corrected by the decoders 21 and 23 less noticeable. will be carried out.

In one example of the present invention, the first stage decoder 21 corrects up to one word error. Then, within one error correction block, 2
If it is detected that there is an error in more than one word, a pointer of at least 1 bit indicating that there is an error is added to all 32 words in this error correction block or 28 words excluding the check word. do. For example, this pointer is set to "1" when there is an error, and "0" otherwise. Note that a pointer indicating that an error exists may be added even when the above-mentioned predetermined number of words is corrected during first-stage decoding. When one word is 8 bits, a pointer is added as one bit above the most significant bit, making one word 9 bits, processed by the deinterleaver 22, and supplied to the next stage decoder 23. Ru.

The next stage decoder 23 performs error correction using the number of error words or error locations in the first error correction block indicated by this pointer. FIG. 6 shows an example of error correction in the next-stage decoder 23. In FIG. 6 and the following explanation, the number of error words caused by the pointer is expressed as N _p , and the error location E _i It is expressed as Also, the 6th
In the figure, Y represents affirmation and N represents negation.

(1) Check for errors using syndromes S ₂₀ to _{S 23} . When (S ₂₀ =S ₂₁ =S ₂₂ =S ₂₃ =0), it is assumed that there is no error. In that case (N _p ≦z ₁ )
Find out if. If (N _p ≦z ₁ ), it is determined that there is no error, and the pointer in the error correction block is cleared (“0”). (N _p >
z ₁ ), it is assumed that the detection by the syndrome is incorrect and the pointer is left as is, or the pointers of all words in that block are set to "1". As z ₁ , it is quite large, for example, 14.

(2) If there is an error, check whether it is a one-word error by calculating the syndrome. In the case of a one-word error, find the error location i. It is detected whether the error location i determined by the syndrome calculation matches the error location i determined by the pointer. If there are multiple error locations using pointers,
It is checked whether it matches any of them.
If (i=E _i ), then it is checked whether (N _p ≦z ₂ ). z ₂ is, for example, 10. (N _p ≦
z ₂ ), this is determined to be a 1-word error, and the 1-word error is corrected. (N _p >
z ₂ ), it is dangerous to determine that it is a one-word error, so either the pointers are left as they are, or all words are regarded as errors and each pointer is set to "1".

If (i≠E _i ), it is checked whether (N _p ≦z ₃ ). z ₃ is a fairly small number, for example 3
It is. When (N _p ≦z ₃ ) holds, the one-word error at error location i is corrected in the syndrome calculation.

In the case of (N _p > z ₃ ), it is further checked whether (N _p ≦z ₄ ). That is, (z ₃ <N _p ≦z ₄ )
When , it means that N _p is too small considering that the one-word error due to the syndrome is incorrectly determined, so the pointers of all words in that block are set to "1". On the contrary (N _p > z ₄ )
If so, leave the pointer as is. For example, z ₄ is 5.

(3) In the case where there is not even a single word error, (N _p ≦
z ₅ ), and if (N _p ≦z ₅ ), the reliability of the pointer is poor, so the pointers of all words are set to "1". When (N _p > z ₅ ), leave the pointer as is.

(4) As shown by the broken line in FIG. 6, it is also possible to correct up to M words using the error location using a pointer. For example, it is possible to correct up to 4 word errors. In this case, the error is corrected based on the error location indicated by the pointer. If (N _p ≠ M), leave the pointer as is, or
Or change all word pointers to indicate an error.

The specific numerical values of the comparison values z ₁ to _{z 5} for the number N _p of pointers indicating errors in one block are as follows:
This is just an example. With the error correction code in the example above, if there are 5 or more word errors, there is a risk that it will be judged as no error, and if there are 4 or more word errors, there is a risk that it will be judged as a 1-word error, so this The comparison value can be set to an appropriate value by taking into consideration the probability that such oversight or erroneous correction will occur.

In the error correction decoder shown in FIG.
Check words Q _12o , Q _12o+1 , Q _12o+2 , Q _12o+3
Error correction using and second check word
Error correction using P _12o , P _12o+1 , P _12o+2 , and P _12o+3 is performed once each. If each error correction is performed at least twice (actually, about twice), the error reduction resulting from the correction can be utilized to further increase the error correction ability. can. In this way, when a decoder is provided at a later stage, the decoders 21 and 23
It is also necessary to correct the check words in advance.

Note that in the above example, the delay amount is varied by D as the delay processing in the interleaver 9, but unlike this regular change in the delay amount, it may be irregular. Further, the second check word P _i is an error correction code that includes not only the PCM data but also the first check word Q _i . Similarly, it is also possible for the first check word Q _i to also include the second check word P _i . Specifically, the second check word P _i may be fed back to the encoder that forms the first check word.

As can be understood from the above description, according to the present invention, in the first stage decoding, the maximum number of detectable and correctable errors determined corresponding to the second check word (error detection and correction is possible without using a pointer). In addition to correcting errors up to a predetermined number that does not reach the maximum number of errors that can be performed, if it is detected that there are at least more than the predetermined number of errors, the existence of errors is detected for all words in the block to be corrected. A pointing pointer is set, and in the next stage of decoding, the first error location obtained from the error syndrome generated using the first check word is compared with the second error location based on the pointer. Since the error is corrected after confirming that the locations match, it is possible to prevent erroneous error detection or correction. Furthermore, only when the number of pointers in the block to be corrected is within a preset value, the error pointed to by the matched error location is corrected, thereby making it possible to detect or correct an erroneous error. Corrections can be further prevented and the reliability of decoded data can be improved.

Furthermore, in the first stage decoding, errors up to a predetermined number that does not reach the maximum number of detectable and correctable errors are corrected, so that error correction can be performed using a very simple circuit.

Note that even when a one-word error is corrected in the first-stage decoder 21, if the pointers of all words in the error correction block that includes this corrected one word are set to "1", detection errors and errors are further reduced. It is possible to prevent the possibility of making a wrong correction.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of an error correction encoder to which the present invention is applied, FIG. 2 is a block diagram showing an arrangement during transmission, FIG. 3 is a block diagram of an example of an error correction decoder, and FIGS. 5 and 6 are diagrams used to explain the operation of the decoder of the error correction decoder. 1, 9, 11 are interleavers, 8, 10 are encoders, 16, 22, 24 are deinterleavers, 2
1 and 23 are decoders.

Claims (1)

[Claims] 1. A plurality of channels in a first arrangement state
A first check word consisting of one word included in each PCM data series and a first check word for this word.
An error correction block is formed, and the PCM data sequences of the plurality of channels and the first check word sequence are brought into a second arrangement state by delaying each channel by a different time.
Receive data transmitted as a second error correction block consisting of one word included in each of the PCM data series of the plurality of channels and the first check word series in the arrangement state, and a second check word corresponding thereto. Then, the first stage decoding of the second error correction block is performed using the second check word, and then the PCM data series of the plurality of channels in the second arrangement state and the first check word series are decoded. A first alignment state is achieved by delaying each channel by a different time, and then a first alignment state is achieved using a first check word.
An error correction method that performs next-stage decoding for an error correction block, wherein in the first-stage decoding, errors up to a predetermined number that do not reach the maximum number of detectable and correctable errors determined corresponding to the second check word are detected. At the same time, when it is detected that at least the number of errors exceeds the predetermined number, a pointer indicating the existence of an error is set for all words of the error correction target block, and in the subsequent decoding described above. is, when a one-word error is detected based on the error syndrome generated using the first check word, the first error location found from the error syndrome and the error correction target block. The second error location according to the pointer set during the decoding of the previous stage is compared, and if the first and second error locations match, the error location of the previous stage in the block to be corrected is determined. When the number of pointers set during decoding is within a preset value, the error indicated by the matched error location is corrected using the first error location. error correction method.