JPH047848B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention has a high error correction ability for both burst errors and random errors, and reduces the possibility of error detection being missed or erroneous correction occurring. related to error correction methods.

[Summary of the Invention] In this invention, the error location polynomial used in error correction is determined assuming that there are two words of error in the received n-word data: Aα ²ⁱ +Bα ⁱ +C=0, where i is This uses the error location, and the coefficients A, B,
The number of errors, error locations, and error values can be obtained using C, and the error correction process can be simplified.

[Conventional technology]

The applicant of the present application has previously proposed a method called cross interleave as a data transmission method effective against burst errors. This generates a first check word sequence by supplying one word included in each of the PCM data sequences of multiple channels in a first alignment state to a first error correction encoder; The check word series of 1 and the PCM data series of multiple channels are
array state, and one word contained in each is the second
the second error correction encoder by feeding
It generates a check word sequence, and performs double interleaving (arrangement rearrangement) on a word-by-word basis. Interleaving distributes and transmits check words and PCM data included in a common error correction block.
This is intended to reduce the number of error words among a plurality of words included in a common error correction block when the original arrangement is restored on the receiving side. In other words, when a burst error occurs during transmission, this burst error can be dispersed. If such interleaving is performed twice,
Since each of the first and second check words constitutes a separate error correction block, even if one of the check words cannot correct an error, the other can be used to correct the error. , Therefore, the error correction ability can be further improved.

By the way, if even one bit in one word is erroneous, the entire word is treated as erroneous, so when handling received data with relatively many random errors, it is not always necessary to have sufficient error correction ability. I can't say that.

This is a highly capable error correction system that can detect and correct up to a 2-word error in a predetermined word, for example, within one block, and if the error location is known, it can also correct more than 3-word errors or 4-word errors. sign (adjacent (b
-adjacent) code) can be improved by combining it with the above-mentioned multiple interleaving.

Moreover, this error correction code has a feature that the structure of the decoder can be made extremely simple when only one word error is to be corrected.

This type of error correction code will be explained below.

When describing an error correction code, a vector representation or a cyclic group representation is used. First, GF
(2) In the above, consider an irreducible m-th degree polynomial F(x).
On the field GF(2) in which only elements "0" and "1" exist, the irreducible polynomial F(x) has no roots. Therefore, consider a virtual root α that satisfies (F(x)=0). At this time, 2 ^m different elements 0, α, α ² , α ³ ……α ^2m-1 expressed as powers of α including zero elements
constitutes an extended field GF (2 ^m ). GF (2 ^m ) is
It is a polynomial ring modulo the m-th order irreducible polynomial F(x) over GF(2). The element of GF (2 ^m ) is 1, α=
It can be expressed as a linear combination of {x}, α ² = {x ² }...α ^m-1 = {x ^m-1 }. That is, a ₀ +a ₁ {x}+a ₂ {x ² }+…+a _n-1 {x ^m-1 } =a ₀ +a ₁ α+a ₂ α ² +…+a _n-1 α ^m-1 or (a _{n -1} , a _n-2 …a ₂ , a ₁ , a ₀ ) where,
a ₀ , a ₁ ...a _n-1 ∈GF(2).

As an example, considering GF(2 ⁸ ), (mod.F
(x) = x ⁸ + x ⁴ + x ³ + x ² + 1), and all 8-bit data is a ₇ x ⁷ + a ₆ x ⁶ + a ₅ x ⁵ + a ₄ x ⁴ + a ₃ x ³ + a ₂ x ² + a ₁ x+
It can be written as a ₀ or (a ₇ , a ₆ , a ₅ , a _{4 , a 3 ,} a ₂ , a ₁ , a ₀ ), so for example, a ₇ is on the MSB side and a ₀ is on the MSB side.
Assign to LSB side. Since a _o belongs to GF(2),
0 or 1.

Further, the following (m×m) matrix T is derived from the polynomial F(x).

T=0 0 ... 0 a ₀ 1 0 ... 0 a ₁ 0 1 ... 0 a ₂ 〓 〓 〓 〓 0 0 ... 1 a _n-1 Another expression uses a cyclic group. This takes advantage of the fact that the 0 element is removed from GF(2 ^m ) and the remaining elements form a multiplicative group of order 2 ^m-1 . When expressed using the original cyclic group of GF (2 ^m ), it becomes 0, 1 (=α ^2m-1 ), α, α ² , α ³ ...α ^2m-2 .

Now, in one example of this invention, when m bits are one word and n words constitute one block,
k check words are generated based on the parity check matrix H below.

H=1 α ^n-1 α ^2(n-1) 〓 α ^(K-1)(n-1) 1 α ^n-2 α ^2(n-2) 〓 α ^(K-1)(n-1) … … … … 1 α α ² 〓 α ^K-1 1 1 1 〓 1 Furthermore, the parity check matrix H can be similarly expressed using the matrix T.

H=I T ^n-1 T ^2(n-1) 〓 T ^(k-1)(n-1) I T ^n-2 T ^2(n-2) 〓 T ^(k-1)(n-2) … … … … I T T ² 〓 T ^k-1 I I I 〓 I However, I is a (m×m) unit matrix.

As mentioned above, the expression using the root α and the generation matrix T
Expressions using are similar to each other.

For example, if we use four (k=4) check words, the parity check matrix H is H=1 α ^n-1 α ^2(n-1) α ^3(n-1) 1 α ^{n -2} α ^2(n-2) α ^3(n-2) … … … … 1 α α ² α ³ 1 1 1 1. One block of received data is expressed as a column vector V
= (W^ ^n-1 , W^ ^n-2 ...W^ ₁ , W^ ₀ ) (However, W^ _i = W _i + e _i ,
e _i : error pattern), 4 occurs on the receiving side
The syndromes S ₀ , S ₁ , S ₂ , and S ₃ become S ₀ S ₁ S ₂ S ₃ =H· ^VT . This error correction code has the ability to correct errors up to 4 words. In other words, it is possible to detect and correct errors up to 2-word errors in one error correction block, and when the error location is known, it is possible to detect and correct errors up to 3-word errors or 4-word errors.
Word errors can be corrected.

4 check words in 1 block (p=
W ₃ , q=W ₂ , r=W ₁ , s=W ₀ ).
This check word can be obtained by solving the following four-dimensional simultaneous equations. However, Σ means Σ.

p+q+r+s=ΣW _i =a α ³ p+α ² q+αr+s=Σα ⁱ W _i =b α ⁶ p+α ⁴ q+α ² r+s=Σα ²ⁱ W _i =c α ⁹ p+α ⁶ q+α ³ r+s=Σα ³ⁱ W _i =d Skip the calculation process However, to show only the results, p q r s=α ²¹² α ¹⁵³ α ¹⁵² α ²⁰⁹ α ¹⁵⁶ α ² α ¹³⁵ α ¹⁵² α ¹⁵⁸ α ¹³⁸ α ² α ¹⁵³ α ²¹⁸ α 158 α ^{156 α 212 a} b c d Become. In this way, check words p, q,
The role of the encoder provided on the transmitting side is to form r and s.

Next, a basic algorithm for error correction when data containing check words formed as described above is transmitted and received will be described.

[1] When there is no error: S ₀ = S ₁ = S ₂ = S ₃ = 0 [2] When there is a 1-word error (the error pattern at error location i is e _i ): S ₀
= e _i , S ₁ = α ⁱ e _i , S ₂ = α ²ⁱ e _i , S ₃ = α ³ⁱ e _i Therefore α ⁱ S ₀ = S ₁ α ⁱ S ₁ = S ₂ α ⁱ S ₂ = S ₃ , and it is possible to determine whether a one-word error has occurred by checking whether this relationship holds when i is successively changed. Alternatively, S ₁ /S ₀ =S ₂ /S ₁ =S ₃ /S ₂ =α ⁱ , and the error location i can be found by referring to the conversion table stored in advance in the ROM for the pattern of α ⁱ . The syndrome S ₀ at that time becomes the error pattern e _i itself.

[3] In the case of two-word error (e _i , e _j ) S ₀ = e _i + e _j S ₁ = α ⁱ e _i + α ^j e _j S ₂ = α ²ⁱ e _i + α ^2j e _j S ₃ = α ³ⁱ e _i +α ^3j e _{jTransforming} the above equation, α ^j S ₀ +S ₁ = (α ⁱ + α ^j )e _i α ^j S ₁ +S ₂ = α ⁱ (α ⁱ +α ^j )e _i α ^j S ₂ +S ₃ = α ²ⁱ (α ⁱ + α ^j ) e _i Therefore, if α ⁱ (α ^j S ₀ + S ₁ ) = α ^j S ₁ + S ₂ α ⁱ (α ^j S ₁ + S ₂ ) = α ^j S ₂ + S ₃ holds. , it is determined that there is a 2-word error, and the error locations i and j are known. In other words, i
By changing the combination of and j, check whether the above relationship holds. The error pattern at that time is e _i = S ₀ + α ^-j S ₁ /1 + α ^ij e _j = S ₀ + α ^-i S ₁ /1 + α ^ji [4] In case of 3-word error (e _i , e _j , e _k ) : S ₀ = e _i + e _j + e _k S ₁ = α ⁱ e _i + α ^j e _j + α ^k e _k S ₂ = α ²ⁱ e _i + α ^2j e _j + α ^2k e _k S ₃ = α ³ⁱ e _i + α ^3j e _j + α ^3k e kTransforming the above _equation , α ^k S ₀ + S ₁ = (α ⁱ + α ^k ) e _i + ( ^j + α ^k ) e _j α ^k S ₁ + S ₂ = α ⁱ (α ⁱ + α ^k ) e _i +α ^j (α ^j +α ^k ) e _j α ^k S ₂ + S ₃ = α ²ⁱ (α ⁱ + α ^k ) e _i + α ^2j (α ^j + α ^k )e _j Therefore α ^j (α ^k S ₀ + S ₁ ) + (α ^k S ₁ + S ₂ ) = (α ⁱ + α ^j ) (α ⁱ + α ^k ) e _i α ^j (α ^k S ₁ + S ₂ ) + (α ^k S ₂ + S ₃ ) = α ⁱ (α ⁱ + α ^j ) (α ⁱ + α ^k )e _i From the above formula, α ⁱ (α ^j (α ^k S ₀ + S ₁ ) + (α ^k S ₁ + S ₂ )) = α ^j (α ^k S ₁ + S ₂ ) + (α If ^k S ₂ + S ₃ ) is established, it can be determined that there is a 3-word error.
At that time, each error pattern is e _i = S ₀ + (α ^-j + α ^-k ) S ₁ + α ^-jk S ₂ / (1 + α ^ij
(1+α ^ik ) e _j =S ₀ +(α ^-k +α ^-i )S ₁ +α ^-ki S ₂ /(1+α ^ji
) (1 + α ^jk ) e _k = S ₀ + (α ^-i + α ^-j ) S ₁ + α ^-ij S ₂ / (1 + α ^ki
)(1+α ^kj ). In reality, the configuration for correcting a 3-word error becomes complicated, and the time required for the correction operation also increases. Therefore, it is practical to combine this with the case where the error locations of i, j, k, and l are known by the pointer, and use the above equation for checking at that time to perform error correction calculations.

[5] In case of 4-word error (e _i , e _j , e _k , e _l ): S ₀ = e _i + e _j + e _k + e _l S ₁ = α ⁱ e _i + α ^j e _j + α ^k e _k + α ^l e _l S ₂ = α ²ⁱ e _i + α ^2j e _j + α ^2k e _k + α ^2l e _l S ₃ = α ³ⁱ e _i + α ^3j e _j + α ^3k e _k + α ^3l e lTransforming _the above equation gives e _i = S ₀ +(α ^-j +α ^-k +α ^-l )S ₁ +(α ^-jk +α ^-k
-l +α ^-lj )S ₂ +α ^-jkl S ₃ /(1+α ^ij )(1+α ^i
-k ) (1 + α ^il ) e _j = S ₀ + (α ^-k + α ^-l + α ^-i ) S ₁ + (α ^-kl + α ^-l
-i +α ^-ik )S ₂ +α ^-kli S ₃ /(1+α ^ji )(1+α ^j
-k ) (1 + α ^jl ) e _k = S ₀ + (α ^-l + α ^-i + α ^-j ) S ₁ + (α ^-li + α ^-i
-j +α ^-jl )S ₂ +α ^-lij S ₃ /(1+α ^ki )(1+α ^k
-j ) (1 + α ^kl ) e _l = S ₀ + (α ^-i + α ^-j + α ^-k ) S ₁ + (α ^-ij + α ^-j
-k +α ^-ki )S ₂ +α ^-ijk S ₃ /(1+α ^li )(1+α ^l
-j ) (1+α ^lk ) pointer to the error location (i,
j, k, l) is known, error correction can be performed by the above-mentioned calculation.

Furthermore, Japanese Patent Publication No. 56-20575 describes the following error correction method.

In other words, for the code word of the Reed-Solomon code, σ(x)=x ^e +σ ₁ x ^e-1 +...+σ _e (e is the number of errors)
Find the error location polynomial expressed by
The error is corrected by calculating its root, and consists of the following steps.

A plurality of syndromes S _i are generated from the code word.

By performing the operations (i) to (v) below and checking the number of errors e, an equation S _i+ showing the relationship between the syndrome S _i and the coefficients σ ₁ to σ _e of the error location polynomial is obtained. _e ＋
The coefficients σ ₁ to σ _e are calculated by solving σ ₁ S _i+e-1 +...+σ e _-1 S i+1 + _{σ e} S _i =0.

(i) If all syndromes S _i are 0, e=
Set to 0.

(ii) Calculate σ=S ₁ /S ₀ when S ₀ ≠ 0, and if S ₂ +σS ₁ =S ₃ =σS ₂ =0, then e
=1.

(iii) When S ₀ =0 and S ₁ ≠0 or in (ii) S ₀
≠0 and S ₂ +σS ₂ ≠0, σ ₁ = (S ₁ S ₂ + S ₀ S ₃ )/(S ₁ ² +S ₀ S ₂ ), σ ₂ = (S ₁ S ₃ +S ₂ ² )/ (S ₁ ² +S ₀ S ₂ ) and D=S ₄ +σ ₁ S ₃ +σ ₂ S ₂ and if D=0, e=2.

(iv) When S ₃ +σS ₂ ≠0 in (ii), when D≠0 in (iii), or when S ₀ =S ₁ =0 and S ² ≠0
When , e=3.

(v) If S ₀ =S ₁ =S ₂ =0 and S _i ≠0 for a certain i of 3i5, then e>3.

Calculate the roots of the error location polynomial to calculate the error location and error value,
This error location and error value are used to correct errors in the codeword.

[Problem that the invention seeks to solve]

The basic error correction algorithm of the prior art described above uses syndromes S ₀ to _{S 3} to check in the first step whether there is an error, in the second step to check whether there is a one-word error, and in the third step to check whether there is an error. It checks whether there is a 2-word error, and when trying to correct even a 2-word error, it takes a long time to complete all steps, and this is especially true when determining the error location of a 2-word error. A problem arises.

Furthermore, after the number of error words is known, it is necessary to calculate the root of the error location polynomial to calculate the error location and error value, which requires many correction processing steps, and this also increases the correction processing time. It has the disadvantage of being long.

[Means for solving problems]

In the present invention, for example, in an error correction method using an error correction code such as the former example of the prior art, an error location equation Aα ²ⁱ is obtained assuming that there are 2 word errors in received n word data. +Bα ⁱ +C=0 However, i is the coefficient A, B, C of each term of error location calculated from the above respective syndromes, and if this coefficient satisfies the relationship A=B=C=0, there is no error or 1 word error. If the above relationship is not satisfied, it is determined that there is an error of 2 or more words, and when it is determined that a 1-word error exists, this 1-word error is corrected, and the error of 2 or more words is determined. If it is determined that the error exists, the two-word error is corrected using the coefficients A, B, and C, and the existence of more errors is detected.

[Effect]

Find the coefficients A, B, and C, and this coefficient is A=B=C
The number of error words is checked to see if it satisfies =0. This coefficient is also used to determine the error location and error value.

Therefore, the error correction processing work is simplified and shortened.

〔Example〕

An example of the error correction method according to the present invention will be described in the case where it is applied to a code word of the former error correction code of the prior art.

This is effective when applied when assuming correction of two-word errors, and two-word errors (e _i , e _j )
The _formula for _the ^syndromes S _{0 ,} ^S ₁ , _{S 2 , and} S ₃ ⁱⁿ _{the case} of ^2j e _j S ₃ = α ³ⁱ e _i + α ^3j e _jIf we transform this equation, we get (α ⁱ S ₀ + S ₁ ) (α ⁱ S ₂ + S ₃ ) = (α ⁱ S ₁ + S ₂ ) ^2Further transformation, we get the following Find the error location equation for .

(S ₀ S ₂ + S ₁ ² ) α ²ⁱ + (S ₁ S ₂ + S ₀ S ₃ ) α ⁱ + (S ₁ S ₃ + S ₂ ² )=0 Here, the coefficient of each equation is S ₀ S ₂ + S ₁ ² = A S ₁ S ₂ + S ₀ S ₃ = B S ₁ S ₃ + S ₂ ² = C. By using the coefficients A, B, and C in the above equation, the error location in the case of a two-word error can be determined.

[1] When there is no error: It is determined that there is no error when A=B=C=0, S ₀ =0, and S ₃ =0.

[2] In the case of a 1-word error: A 1-word error is determined when A=B=C=0, S ₀ ≠0, and S ₃ ≠0. (α ⁱ =
The error location i is found from S ₁ /S ₀ ), and error correction is performed using (e _i =S ₀ ).

[3] In the case of a 2-word error, in the case of an error of 2 or more words, (A≠0,
B≠0, C≠0) holds, and the determination becomes extremely simple. Further, at this time, Aα ²ⁱ +Bα ⁱ +C=0 (where i=0 to (n-1)) holds true. Here, if we set (B/A=D, C/A=E), then D=α ⁱ +α ^j and E=α ⁱ ·α ^j , so that α ²ⁱ +Dα ⁱ +E=0. Here, if the difference between the two error locations is t, that is, (j=i+t), then it is transformed as D=α ⁱ (1+α ^t ) and E=α ^2i+t . Therefore, D ² /E=(1+α ^t ) ² /α ^t = α ^−t + α ^t . The value of (α ^{- t} + α ^t ) for each of (t = 1 to (n-1)) is written in advance in the ROM,
t is determined by detecting a match between the output of the ROM and the value of (D ² /E) calculated from the received word. If this matching relationship does not hold, there is an error of three or more words. Therefore, by setting X=1+α ^t Y=1+α ^−t =D ² /E+X, α ⁱ =D/X, α ^j =D/Y, and error locations i and j can be found. The error patterns e _i and e _j are e _i =(α ^j S ₀ +S ₁ )/D=S ₀ /Y+S ₁ /D e _j =(α ⁱ S ₀ +S ₁ )/D=S ₀ /X+S ₁ /D This allows error correction to be performed.

The above-described correction algorithm can significantly reduce the time required to find the error location when correcting a two-word error, compared to the basic algorithm.

Incidentally, if the number k of check words is further increased, the error correction ability is further improved. For example, (k
=6), it has the ability to correct errors up to 6 words. That is, up to 3 word errors can be detected and corrected, and when the error location is known, up to 6 word errors can be corrected.

Next, a specific example in which the present invention is applied to recording and reproducing audio PCM signals will be described with reference to the drawings.

FIG. 1 shows the entirety of an error correction encoder provided in a recording system, and an audio PCM signal is supplied to its input side. Audio PCM
The signal is formed by sampling each of the left and right stereo signals at a sampling frequency _s (for example, 44.1 [kHz]) and converting one sample into one word (16 bits in two's complement code). . Therefore, for the audio signal of the left channel, PCM data in which each word is continuous is obtained as (L ₀ , L ₁ , L ₂ ...), and for the audio signal of the right channel, it is obtained as (R ₀ , R ₁ , R 2 ...). ₂ ...)
PCM data in which each word is consecutive is obtained.
This left and right channel PCM data is divided into 6 channels each, for a total of 12 channels.
A PCM data series is input. At a given timing, (L _6o , R _6o , L _6o+1 , R _6o+1 , L _6o+2 ,
Twelve words (R _6o+2 , L _6o+3 , R _6o+3 , L _6o+4 , R _6o+4 ) are input. In this example, one word is divided into upper 8 bits and lower bits, and 12 channels are further divided into
Processed as 24 channels. For simplicity, one word of PCM data is expressed as W _i ,
For the upper 8 bits, W _i , A and the suffix A are added, and for the lower 8 bits, W _i , A and the suffix A are added.
They are distinguished by adding the suffixes B and B.
For example, L _6o is divided into two parts, W _12o ,A and W _12o ,B.

These 24 channels of PCM data sequences are first supplied to the even-odd interleaver (1). (n=
0, 1, 2...), L _6o (=W _12o , A,
W _12o , B), R _6o (=W _12o+1 , A, W _12o+1 , B),
L _6o+2 (=W _12o+4 , A, W _12o+4 , B), R _6o+2 (=
W _12o+5 , A, W _12o+5 B), L _6o+4 (=W _12o+8 , A,
W _12o+8 , B), R _6o+4 (=W _12o+9 , A, W _12o+9 , B)
are even-numbered words, and the others are odd-numbered words. Each of the PCM data series consisting of even-numbered words is transmitted to the 1-word delay circuits 2A, 2B, 3A, 3B of the even-odd interleaver 1,
4A, 4B, 5A, 5B, 6A, 6B, 7A, 7
Delayed by one word by B. Of course, more than one word, for example eight words, may be delayed. In addition, in the even-odd interleaver 1, 12 data sequences consisting of even-numbered words are
The 12 data sequences consisting of odd-numbered words occupy the 13th to 12th transmission channels.
Converted to occupy up to 24 transmission channels.

The even-odd interleaver 1 is provided to prevent errors in two or more consecutive words of each of the left and right stereo signals, and to prevent these errors from becoming uncorrectable. For example, considering three consecutive words (L _i-1 , L _i , L _i+1 ), L _i is incorrect,
However, if this error is uncorrectable, L _i-1 or
It is desired that L _i+1 is correct. When correcting erroneous data L _i , it is possible to interpolate L _i using the previous correct word L _i-1 (previous value hold), or use the average value of L _i-1 and L _i+1 . This is to interpolate L _i . The delay circuits 2A, 2B to 7A, 7B of the even-odd interleaver 1 are provided to ensure that adjacent words are included in different error correction blocks. Furthermore, the reason why transmission channels are grouped into data sequences consisting of even-numbered words and data sequences consisting of odd-numbered words is that when interleaving is performed, adjacent even-numbered words and odd-numbered words are This is to make the distance between recording positions as large as possible.

At the output of the even-odd interleaver 1, a PCM data sequence of 24 channels in the first arrangement state appears, one word is taken out from each of them and supplied to the encoder 8, and the first check word Q _12o ,
Q _12o+1 , Q _12o+2 , Q _12o+3 are formed. The first error correction block including the first check word is (W _12o-12 , A, W _12o-12 , B, W _12o+1-12 , A,
W _12o+1-12 , B, W _12o+4-12 , A, W _12o+4-12 , B,
W _12o+5-12 , A, W _12o+5-12 , B, W _12o+8-12 , A,
W _12o+8-12 , B, W _12o+9-12 , A, W _12o+9-12 , B,
W _12o+2 , A, W _12o+2 , B, W _12o+3 , A, W _12o+3 ,
B, W _12o+6 , A, W _12o+6 , B, W _12o+7 , A,
W _12o+7 , B, W _12o+10 , A, W _12o+10 , B,
W _12o+11 , A, W _12o+11 , B, Q _12o , Q _12o+1 ,
Q _12o+2 , Q _12o+3 ). In the first encoder 8, the number of words in one block: (n=28), the number of bits in one word: (m=
8), the number of check words: (k=4) is encoded.

These 24 PCM data sequences and 4 check word sequences are supplied to the interleaver 9. In the interleaver 9, the position of the transmission channel is changed so that a check word sequence is interposed between the PCM data sequence consisting of even-numbered words and the PCM data sequence consisting of odd-numbered words, and then a delay for interleaving is performed. Processing is in progress. This delay processing is performed for each of the other 27 transmission channels excluding the first transmission channel, 1D, 2D, 3D, 4D...26D, 27D (however,
D is achieved by inserting a delay circuit with a unit delay of, for example, 4 words.

At the output of the interleaver 9, 28 data sequences in the second arrangement state appear, and one word is extracted from each data sequence and sent to the encoder 1.
0 and the second check word P _12o ,
P _12o+1 , P _12o+2 , P _12o+3 are formed. The second error correction block consisting of 32 words including the second check word is as follows.

(W _12o-12 , A, W _12o-12(D+1) , B,
W _{12o+1-12(2D+1)} , A, W _{12o+1-12(3D-1)} , B,
W _{12o+4-12(4D+1)} , A, W _{12o+4-12(5D+1)} , B,
W _{12o+5-12(6D+1)} , A, W _{12o+5-12(7D+1)} , B...
Q _12o-12(12D) , Q _{12o+1-12(13D)} , Q _{12o+2-12(14D)} ,
Q _{12o+3-12(15D)} ,...W _{12o+10-12(24D)} ,A,
W _{12o+10-12(25D)} , B, W _{12+11-12(26D)} , A,
W _{12o+11-12(27D)} , BP _12o , P _12o+1 , P _12o+2 , P _12o+3 ) Among the 32 data system examples including the first and second check words, an even number An interleaver 11 in which a one-word delay circuit is inserted is provided for the second transmission channel, and inverters 12 and 1 are provided for the second check word series.
3, 14, and 15 are inserted. interleaver 1
1 takes care of the fact that an error that spans the boundary between blocks is likely to result in an error in the number of words that cannot be corrected. In addition, inverters 12 to 1
5 becomes 1 due to dropout during transmission.
This is provided to prevent a malfunction in which all data in the block becomes "0" and the reproduction system determines this as correct. For the same purpose, an inverter may also be inserted for the first check word series.

Then, each of the 32 words extracted from each of the 24 PCM data sequences and 8 check word sequences that are finally obtained is serialized, and as shown in Figure 2, 16-bit synchronization is placed at the beginning. A signal is added to form one transmission block and transmitted. In FIG. 2, one word extracted from the i-th transmission channel is shown as u _i for simplicity of illustration. Specific examples of transmission systems include magnetic recording and reproducing devices, rotating disk devices, and the like.

The encoder 8 described above is related to the error correction code as described above, (n=28, m=8, k=4)
and a similar encoder 10 has (n=32, m=8,
k=4).

The reproduced data is applied to the input of the error correction decoder shown in FIG. 3 every 32 words of one transmission block. Since this is playback data, it may contain errors. In the absence of errors, the 32 words applied to the input of this decoder will match the 32 words that appear at the output of the error correction encoder.
The error correction decoder performs deinterleaving processing corresponding to the interleaving processing in the encoder to restore the data order and then perform error correction.

First, a deinterleaver 1 in which a 1-word delay circuit is inserted for odd-numbered transmission channels.
6 is provided, and inverters 17, 18, 19, and 20 are inserted for the check word sequence, and the check word sequence is supplied to the decoder 21 at the first stage. Decoder 21
Now, as shown in Figure 4, the parity check matrix
Syndromes S ₁₀ , S ₁₁ , S ₁₂ , and S ₁₃ are generated from H _c1 and the input 32 words (V ^T ), and error correction is performed based on these syndromes. α is (F(x)=x ⁸ +
x ⁴ + x ³ + x ² + 1) is the element of GF (2 ⁸ ). From the decoder 21, 24 PCM data sequences and 4 check word sequences appear, and one of these data sequences
At least a 1-bit pointer (“1” if an error is included, “0” otherwise) indicating the presence or absence of an error is added to each word. In FIG. 4 and FIG. 5, which will be described later, and in the following explanation, one received word W^ _i is expressed as W _i .

The output data sequence of this decoder 21 is supplied to a deinterleaver 22. Deinterleaver 22
are for canceling the delay processing performed by the interleaver 9 in the error correction encoder, and are applied to each of the channels from the first transmission channel to the 27th transmission channel (27D, 26D, 25D).
...2D, 1D) and delay circuits with different delay amounts are inserted. The output of the deinterleaver 22 is supplied to a decoder 23 at the next stage. In the decoder 23, as shown in _FIG.
and from the input 28 words, the syndrome S ₂₀ ,
S ₂₁ , S ₂₂ , and S ₂₃ are generated, and error correction is performed based on them.

The data sequence appearing at the output of the next-stage decoder 23 is supplied to an even-odd deinterleaver 24.
In the even-odd deinterleaver 24, the PCM data series consisting of even-numbered words and the PCM data series consisting of odd-numbered words are returned so that they are located on different transmission channels, and the PCM data series consisting of odd-numbered words is A 1-word delay circuit is inserted for each series. At the output of this even-odd deinterleaver 24, a PCM data sequence is obtained having exactly the same arrangement and predetermined transmission channel as that supplied to the input of the error correction encoder. Although not shown in FIG. 3, a correction circuit is provided next to the even-odd deinterleaver 24, and performs correction such as average value interpolation to make errors that cannot be corrected by the decoders 21 and 23 less noticeable. will be carried out.

In one example of the present invention, the first-stage decoder 21 corrects up to one word error.
If it is detected that there is an error in two or more words in one error correction block, it is determined that there is an error in all 32 words or 28 words excluding the check word in this error correction block. Add at least a 1-bit pointer indicating the . For example, this pointer is set to "1" when there is an error, and "0" otherwise. Note that a pointer indicating that an error exists may be added even when the above-mentioned predetermined number of words is corrected during first-stage decoding.

When one word is 8 bits, a pointer is added as one bit above the most significant bit, making one word 9 bits, processed by the deinterleaver 22, and supplied to the next stage decoder 23. Ru.

The next stage decoder 23 performs error correction using the number of error words or error locations in the first error correction block indicated by this pointer. FIG. 6 shows an example of error correction in the next-stage decoder 23. In FIG. 6 and the following explanation, the number of error words caused by the pointer is expressed as N _p , and the error location caused by the pointer is expressed as E. Represented by _i . Further, in FIG. 6, Y represents affirmation and N represents negation.

(1) Check for errors using syndromes S ₂₀ to _{S 23} . When (S ₂₀ =S ₂₁ =S ₂₂ =S ₂₃ =0), it is determined that there is no error. In that case, (N _p ≦z ₁ )
Find out if. If (N _p ≦z ₁ ), it is determined that there is no error, and the pointer in the error correction block is cleared (“0”). (N _p >
z ₁ ), it is assumed that the syndrome detection is incorrect and the pointer is left as is, or the pointers of all words in that block are set to "1". Let z ₁ be quite large, for example 14.

(2) If there is an error, check whether it is a one-word error by calculating the syndrome. In the case of a one-word error, find the error location i. It is detected whether the error location i determined by the syndrome calculation matches the error location i determined by the pointer. If there are multiple error locations using pointers,
It is checked whether it matches any of them.
If (i=E _i ), then it is checked whether (N _p ≦z ₂ ). z ₂ is, for example, 10. (N _p ≦
z ₂ ), this is determined to be a 1-word error, and the 1-word error is corrected. (N _p >
z ₂ ), it is dangerous to determine that it is a one-word error, so either the pointers are left as they are, or all words are regarded as errors and each pointer is set to "1".

If (i≠E _i ), it is checked whether (N _p ≦z ₃ ). z ₃ is a fairly small number, for example 3
It is. When (N _p ≦z ₃ ) holds, the one-word error at error location i is corrected in the syndrome calculation.

In the case of (N _p > z ₃ ), it is further checked whether (N _p ≦z ₄ ). That is, (z ₃ <N _p ≦z ₄ )
When , it means that N _p is too small considering that the one-word error due to the syndrome is incorrectly determined, so the pointers of all words in that block are set to "1". On the contrary (N _p > z ₄ )
If so, leave the pointer as is. For example, z ₄ is 5.

(3) In the case where there is not even a single word error, (N _p ≦
z ₅ ), and if (N _p ≦z ₅ ), the reliability of the pointer is poor, so the pointers of all words are set to "1". When (N _p > z ₅ ), leave the pointer as is.

(4) As shown by the broken line in FIG. 6, it is also possible to correct up to M words using the error location using a pointer. For example, it is possible to correct up to 4 word errors. In this case, the error is corrected based on the error location indicated by the pointer. If (N _p ≠ M), leave the pointer as is, or
Or change all word pointers to indicate an error.

The specific numerical values of the comparison values z ₁ to _{z 5} for the number N _p of pointers indicating errors in one block are as follows:
This is just an example. The error correction code in the above example may determine that there is no error if there are 5 or more word errors, and may determine that it is a 1-word error if there are 4 or more word errors. The comparison value can be set to an appropriate value in consideration of the probability that such oversight or erroneous correction will occur.

In the error correction decoder shown in FIG.
Check word Q _12o , Q _12o+1 , Q _12o+2 , Q _12o+3
error correction and second check word using
Error correction using P _12o , P _12o+1 , P _12o+2 , and P _12o+3 is performed once each. If each error correction is performed at least twice (actually, about twice), the error reduction resulting from the correction can be utilized to further increase the error correction ability. can. In this way, when a decoder is provided at a later stage, the decoders 21 and 23
It is also necessary to correct the check words in advance.

Note that in the above example, the delay amount is varied by D as the delay processing in the interleaver 9, but unlike this regular change in the delay amount, it may be irregular. Further, the second check word P _i is an error correction code that includes not only the PCM data but also the first check word Q _i . Similarly, it is also possible for the first check word Q _i to also include the second check word P _i . Specifically, the second check word P _i may be fed back to the encoder that forms the first check word.

Note that even when a one-word error is corrected in the first-stage decoder 21, if the pointers of all words in the error correction block that includes this corrected one word are set to "1", detection errors and errors are further reduced. It is possible to prevent the possibility of making a wrong correction.

〔Effect of the invention〕

According to this invention, the coefficients A ^{, B} of this equation are You can easily check the number of errors using C. The coefficients A, B, and C are also used in calculations for determining error locations and error values. Therefore, error correction work is simplified and
Processing time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of an error correction encoder to which the present invention is applied, FIG. 2 is a block diagram showing an arrangement during transmission, FIG. 3 is a block diagram of an example of an error correction decoder, and FIGS. 5 and 6 are diagrams used to explain the operation of the decoder of the error correction decoder. 1, 9, 11 are interleavers, 8, 10 are encoders, 16, 22, 24 are deinterleavers, 2
1 and 23 are decoders.

Claims (1)

[Claims] One block is composed of 1 n words, and the parity matrix H is expressed as H=1 α ^n-1 α ^2(n-1) α ^3(n-1) 1 α ^n-2 α ^{2( n-2)} α ^3(n-2) … … … … 1 α α ² α ³ 1 1 1 1 However, α is F(x) when F(x) is an irreducible polynomial on GF(2) It is a root that satisfies =0. When expressed as, from one block of received data V ^T consisting of n words and the above parity check matrix H, four syndromes S are calculated by calculating H・V ^T = S ₀ S ₁ S ₂ S ₃ . ₀ , _S1 , _S2 ,
In the method of calculating S ₃ and correcting errors based on this syndrome, the error location equation is calculated assuming that there are 2 word errors in the received n word data.Aα ²ⁱ +Bα ⁱ +C=0 where i is The coefficients A, B, and C of each term of the error location are found from the above respective syndromes, and when these coefficients satisfy the relationship A=B=C=0, the above syndrome is used to determine whether there is no error or 1.
It is determined whether a word error exists, and when it is determined that a 1-word error exists, this 1-word error is corrected using the above syndrome, and when the coefficients of each term above do not satisfy the above relationship, each of the above The coefficients of the terms are used to determine whether a 2-word error exists or more errors exist, and when it is determined that a 2-word error exists, the 2-word errors are corrected using the coefficients of each of the above terms. An error correction method characterized in that: 2 The error location polynomial is α ²ⁱ +Dα ⁱ +E=0, where i is the error location. Find the coefficients D, E, and D ² /E of each term using the coefficients A, B, and C above, and calculate this D The error correction method according to claim 1, wherein when the relational expression between ² /E and the error location difference t when a two-word error exists is satisfied, it is determined that a two-word error exists. . 3. An error correction method in which the relational expression between D ² /E and the error location difference t in claim 2 is D ² /E = α ^{- t} + α ^t . 4. The error correction method according to claim 2, wherein each error location is determined based on the error location difference t and the coefficient D, and the error indicated by this error location is corrected. 5. Claim 4 states that when the respective error locations are i and j, the error locations i and j are determined from α ⁱ =D/1+α ^t α ^j =D/1+α ^-t How to correct errors. 6 A patent for calculating error patterns e i and e _j using a coefficient D, where the respective error locations are _i and j when a two-word error exists, and performing error correction based on this error pattern. Error correction method according to claim 2. 7 The error pattern e _i is determined by α ^j S ₀ +S ₁ /D or using the error location difference t as S ₀ /Y+S ₁ /D, where Y=1+α ^-t , and the error pattern e _i is α 7. The error correction method according to claim 6, wherein ⁱ S ₀ +S ₁ /D or using the error location difference t, S ₀ /X+S ₁ /D where X=1+α ^t .