JPS63158918A - Error correction method - Google Patents

Abstract

PURPOSE:To simplify a correction processing work, by finding the number, the positions, and the values of errors by using a prescribed coefficient of error location polynomial found by recognizing that the errors of two words exist in the information of a received n-words. CONSTITUTION:Four syndromes S0-S3 are found from the parity matrix H of a block of n-words including a root (alpha) which satisfies an irreducible polynomial F(x)=0 on a GF(2) and the information VT by the arithmetic calculation of H.VT, and error correction is performed based on the syndromes. At this time, it is assumed that the errors of two words exist in the information of n-words, and Aalpha<2i>+Balpha<i>+C=0 is found as an error location. Coefficients A, B, and C are found from respective syndrome. lt is decided that no error exists, or the error of one word exists if all of the coefficients are 0s, and when the relation is not satisfied, it is decided that the errors of two or more words exist. The error of one word is corrected when it is decided that the error of one word exists, and the errors of two words are corrected when it is decided that the errors of two or more words exist by using the coefficients A-C, and existence more than that is detected. By such constitution, it is possible to easily and exactly correct the error.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention has a high error correction ability for both burst errors and random errors (although there is a possibility that error detection may be missed or incorrect correction may occur). This invention relates to a reduced error correction method.

[Summary of the invention]

The present invention uses the error location polynomial used in error correction, which is Aα''+Bα'+C, which is obtained assuming that there are two words of error in the received n-word data.
= 0 However, i is used to use the error location, and the coefficients A and B in the above equation.

The number of errors, error location, and error value can be obtained using C, and the error correction process can be simplified.

[Conventional technology]

The applicant of the present application has previously proposed a method called cross interleave as a data transmission method effective against burst errors. This generates a first check word sequence by supplying one word included in each of the PCM data sequences of a plurality of channels in a first arrangement state to a first error correction encoder; The check word series and the PCM data series of multiple channels are
A second check word sequence is generated by supplying one word contained in each to a second error correction encoder, and double interleaving (arrangement rearrangement) is performed in word units. This is what we do. Interleaving involves distributing the check words and PCM data included in a common error correction block, transmitting them, and then returning them to the receiving side to return to the original arrangement. This is an attempt to reduce the number of error words.

In other words, when a burst error occurs during transmission, this burst error can be dispersed.

If such interleaving is performed twice, the first and second
Since each of the check words constitutes a separate error correction block, even if one of the check words cannot correct an error, the other can be used to correct the error, thus reducing the error correction ability. can be further improved.

By the way, if even one bit in one word is incorrect, the entire word is treated as incorrect, so when handling received data with relatively many random errors, the error correction ability is not necessarily sufficient. I can't say that there is.

This is an error correction system with high correction ability that can detect and correct up to a predetermined word error, for example, a 2-word error, within one block, and when the error location is known, it can also correct more than 3-word errors or 4-word errors. (a type of b-adjacent code) can be improved by combining the above-mentioned multiple interleaving.

Moreover, this error correction code has a feature that the structure of the decoder can be made extremely simple when only one word error is to be corrected.

This type of error correction code will be explained below.

When describing an error correction code, a vector representation or a cyclic group representation is used. First, on GF(2),
Consider an irreducible m-th degree polynomial F (X).

The irreducible polynomial F (X) has no roots on the field G F (2) in which there are only elements 0'' and 1'. Consider the root α.

At this time, 2" different elements 0.α, α2.α3...α2"-" expressed as powers of α including zero elements are:
Constructs an extended field GF (2'''). GF (2'')
is the m-th order irreducible polynomial F (
is a polynomial ring modulo X). GF (2”)
The elements are l, α= (x), a”= (X”)...
α'''-1== (z It can be expressed as a linear combination of m-13. That is, ao+a, (X) +a2 (x')+...+a
+a+, (X a-1)=ilo+a, a tena2 α"+-...'+'a, -, α"-' or (aa-1n am-2"" a2+ al+
aO) Here, ao, a, ... am-+EGF (2
).

- As an example, consider GF(2'), (mod, F
(x) = x"+ x'+ x3+ x"+l), and all 8-bit data are a, X' + a, ! '+asX'+a,X' +a
,,x'+a2X'' +a,X +a.

or (at+ a8+ ass a4+ a3h at
, aL ao), so for example, a is assigned to the MSB side and aO to the LVB side. a7 is GF
Since it belongs to (2), it is 0 or 1.

Also, the following matrix T from polynomial F (X) to (mxm)
is guided.

Another representation uses cyclic groups.

This utilizes the fact that the 0 element is removed from GF(2''') and the remaining elements form a multiplicative group of order 2'''-1. The elements of G F (2') can be expressed using a cyclic group as 0, H=αr-+), α, α2. α3 ・・・α
It becomes 2-2.

Now, in one example of this invention, m bits are one word,
When one block is composed of n words, check words are generated based on the parity check matrix H below.

Furthermore, the parity check matrix H can be similarly expressed by the matrix T.

However, I is a unit matrix of (m×m).

As described above, the expression using the root α and the expression using the generator matrix T are similar to each other.

For example, in the case of using four (k=4) check words, the parity check matrix H is as follows. One block of received data is expressed as a column vector V = (W, , W, 2
・・・・−W,,wo) (However, Wt=W1+e1,
el: error slam), four syndromes occur on the receiving side: So, Sl, S2. Sl becomes. This error correction code has the ability to correct errors up to 4 words. In other words, it is possible to detect and correct errors up to 2 words within one error correction block, and when the error location is known,
Correction of 3-word errors or 4-word errors is possible.

4 Chetsuno words in 1 block (p = Ws.

q = W2. r = W, s = We). This checkword can be obtained by solving the following four-dimensional simultaneous equations. However, Σ means Σ.

If we omit the calculation process and only show the results, we get: In this way, check words p, q.

The role of the encoder provided on the transmitting side is to form r and s.

Next, a basic algorithm for error correction when data including a check word formed as described above is transmitted and received will be described.

[1) When there is no error: 5o=S+=S2=S3=
0(2) In case of 1 word error (error pattern at error location i is eI): 5o=et
St=α'et 5t=(2”es Ss=α3
Jm Therefore, when i is changed sequentially, it can be determined whether or not there is a one-word error based on whether this relationship holds. Alternatively, the error location i can be found by referring to the conversion table αl(D pattern stored in advance in the ROM).

The syndrome So at that time is the error pattern eI
Become that.

[3] In the case of 2-word error (ei, ej) If the above equation is transformed and the following holds true, it is determined that there is a 2-word error, and the error locations l and J are known. That is, by changing the combination of i and j, it is checked whether the relationship in the above equation holds true. The error pattern at that time is (4) 37-do error (et ej em) (D case: Transforming the above equation, therefore, from the above equation, α' (ej (α'5 ansυ ten (α'S, +52)) =
If αj(α”S, +S2)+(αkS2.53) holds true, it can be determined that there is a 3-word error.However, (Se2−
0.514-0, S2+0). Each error pattern at that time can be found by In reality, the configuration for correcting a 3-word error becomes complicated, and the time required for the correction operation also increases. Therefore, it is practical to combine this with the case where the error locations of i, j, k, and 1 are known by pointers, and to perform error correction calculations using the above equation for checking at that time.

[5] 4'7-doerer (et, ej, eh,
et): [S°=e□+e・+e□+e・If the above equation is transformed, the error location (l) is determined by the point.

If j, k, f) are known, error correction can be performed by the calculations described above.

Furthermore, Japanese Patent Publication No. 56-20575 describes the following error correction method.

In other words, for the code word of the Reed-Solomon code, σ(x) = x @+σ, xt1+...+σ, (
The error is corrected by finding an error location polynomial (e is the number of errors) and calculating its root, and consists of the following steps.

(2) Generate multiple syndromes Sl from the above code word.

■ By performing the operations (i) to (V) below and checking the number of errors described above, the syndrome SI
and the coefficients 01 to σ of the error location polynomial. Equation S4. .

+σ1S1+*-1+...+σm-15I01+σ
. The coefficients σ to σ are calculated by solving S+=0.

(i) If all syndromes S+ are 0, e=0
shall be.

(ii) When Se2O3, calculate σ=S, /S,
At this time, if S, +σS, = S3 + σ52 = 0, then e
=1.

(iii) When So=0 and 81 km or in (ii) when S, ~0 and S2+σS240, σr=
(SIS2+5O33)/(Sl'+511S2),
σ2= (SIS3+522)/(Sl”+5O32)
and D=S, +σ133+σ2S2, and D=
If it is 0, let e=2.

(iv) When 53+eS240 in (ii), when D'lFO in (iii), or 5o=
When St=0 and S2-0, e=3.

(V) If So''5t=Sa=0 and for i such that 3≦i<5, Si~0, then e>3.

(2) Calculate the root of the error location polynomial to calculate the error location and error value, and use the error location and error value to correct the error in the code word.

[Problem that the invention seeks to solve]

The basic algorithm for error correction in the prior art described above is:
Using Syndrome 80-S, the first step checks for an error, the second step checks for a one-word error, and the third step checks for a two-word error. When trying to correct even the error, the time required to complete all steps increases, and this problem arises especially when determining the error location of a two-word error.

Furthermore, after the number of error words is known, it is also necessary to calculate the root of the error location polynomial to calculate the error location and error value, which requires a large number of correction processing steps, which also increases the correction processing time. There are drawbacks.

[Means for solving problems]

In this invention, for example, in an error correction method using an error correction code as in the former example of the prior art, an error location polynomial % expression % is obtained assuming that there are 2 word errors in received n word data. However, i calculates the coefficients A, B, and C of each term of the error location from the above respective syndromes, and when these coefficients satisfy the relationship A=B=C=0, it is determined that an error or one-word error exists. However, if the above relationship is not satisfied, it is determined that there is an error of 2 or more words, and when it is determined that an l-word error exists, this 1-word error is corrected, and an error of 2 or more words is determined. When it is determined that this is the case, the two-word error is corrected using the coefficients A, B, and C, and the existence of more errors is detected.

[Effect]

Coefficients A, B, and C are determined, and the number of error words is checked by determining whether these coefficients satisfy A=B=C=0. Also,
This coefficient is used to determine the error location and error value.

Therefore, the error correction processing work is simplified and shortened.

〔Example〕

An example of the error correction method according to the present invention will be explained by taking as an example a case where it is applied to a code word of the former error correction code of the prior art.

This is effective when applied when assuming the correction of a two-word error, and the formula for the syndrome So, St, Sa, 33 in the case of a two-word error (e+, ej) is, as above, this formula. When transformed, (αiS0+31) (αt 32+ 33) = (α'
SI+32)" Further transformation is performed to obtain the following error location polynomial.

(SO52+S,')α"+ (sls2+sosriα
' + (SISs +S2') -〇Here, let the coefficients of each equation be set. By using the coefficients A, B, and C in the above equation, 2
The error location in case of a word error can be determined.

(1) If there is no error: A=B=C=0.5o=0. S*=0 It is determined that there is no error when .

[2] (1) In case of word error: When A=B=C=O, So~0,3340, it is determined that there is a 1 word error. (α1 = □)
We know the error location i from S.

Error correction is performed using (e+=so).

[3] In the case of a 2-word error, in the case of an error of 2 words or more, (A~0°BJIF
O, C-! IFD) holds, and the determination becomes extremely simple. Also, at this time, A tX" + B a' 0C=Q (however, i =
0~(n -1)), D=α1+αJ, E=α1・α'', and α21+pα'+E=0. Here, if the difference between the two error locations is t, that is, (j=i+t), then D=α'(1+α
), E=α2′″1. Therefore, it becomes.The value of (α−1+αL) for each of (t=1 to (n −1)) is written in advance in the ROM, and R
t is determined by detecting a match between the output of OM and the value of (□) calculated from the received word. If this matching relationship is not established, it is an error of 3 or more words. Therefore, by setting X=1+α1, error locations i and j can be found. The error pattern e+, e'' is determined and error correction can be performed.

The above-described correction algorithm can significantly reduce the time required to find the error location when correcting a two-word error, compared to the basic algorithm.

On the other hand, if the number k of check words is further increased, the error correction ability is further improved. For example, if (k=6), it has error correction capability of up to 6 words. That is,
It can detect and correct up to 3 word errors, and when the error location is known, it can correct up to 6 word errors.

Next, a specific example in which the present invention is applied to recording and reproducing audio PCM signals will be described with reference to the drawings.

FIG. 1 shows the entirety of an error correction encoder provided in a recording system, and an audio PCM signal is supplied to its input side. The audio PCM signal has a sampling frequency f, (for example, 44
．． 1 (k)Iz) ),
It is formed by converting one sample into one word (16 bits in two's complement code). Therefore, for the left channel audio signal, (Lo,
Ll, L2...) and each word is consecutive PCM
Data is obtained, and PC'M data in which each word (Ro, R1, R2, . . . ) is consecutive is also obtained for the audio signal of the right channel. The PCM data of the left and right channels are divided into 6 channels each, and a total of 12 channels of PCM data series are manually generated. At a predetermined timing, (Lsl, , Rg, ,
Le,. H, R@ 11-11L ai+2+ R61
1+21 LensL Rahman Lens<,
R6+n+4) 12 words are input manually. In this example, the 17-bit is divided into the upper 8 bits and the lower 8 bits.
The 2 channels are further processed as 24 channels.

For simplicity, one word of PCM data is expressed as WI, and the upper 8 bits are suffixed with Wl, A, and the lower 8 bits are W,, B.
and B suffixes are added to distinguish them. For example, L
6. , is divided into two parts, Wlz-,A and W12h,B.

This 24-channel PCM data sequence is first supplied to an even-odd interleaver (1). (n=0, 1
．． 2...), then L6ゎ(=W, 2h, A
.

'VV12. ．． B), R6n (=W12-.1.
A, Wla,, +, B), L 6h+2 (
= W12+1+4+ A + W12n+4+ B
), RIIR02(= Wl2.1.s, A,
WlzlNths, B), L8n◆4(=W12+a
+11 meeting A, Wlz-4, B), Rl! 1104
(= Wl 2114111 AI Wl 2n+fJ
mB) are even-numbered words, and the others are odd-numbered words. PC consisting of even-numbered words
Each of the M data series is an even-odd interleaver (1) 1-word delay circuit (2A) (2B) (3A) (3B)
(4A) (4B) (5A) (513> (6A)
(6B) (7A) (7B> delays one word.Of course, it is also possible to delay more than one word, for example, eight words.Also, in the even-odd interleaver (1), even-numbered words 12 data sequences occupy the first to twelfth transmission channels,
The 12 data series consisting of odd-numbered words are the 13th
~24th transmission channel.

The even-odd interleaver (1) is provided to prevent errors in two or more consecutive words of each of the left and right stereo signals and to prevent these errors from becoming uncorrectable. For example, considering three consecutive words (LL-+, Lt, LL.,), if Ll is incorrect and this error cannot be corrected, then Li-+ or LL. , is desired to be correct. That is incorrect data L1
In the case of correcting the previous correct word, -3
However, if you interpolate (hold the previous value),
1 and LL. This is to interpolate LL using the average value of 8. Even-odd interleaver (1) delay circuit (2A)
(2B) to (7A) (7B) is provided to ensure that adjacent words are included in different error correction blocks. Also, the reason why transmission channels are grouped for each data series consisting of even-numbered words and data series consisting of odd-numbered words is that when interleaving is performed, the recording of adjacent even-numbered words and odd-numbered words This is to make the distance between the positions as large as possible.

At the output of the even-odd interleaver (1), a PCM data sequence of 24 channels in the first arrangement state appears, and one word is extracted from each of them and supplied to the encoder (8), where it is checked by the first checker. Word Q1□,.

Q I 2 n. I+ Q+2n+2+ Q12h+3
is formed. The first error correction block including the first check word is (Wl2, 1-121 As W12n-12+ 8
1W! 211+1-121 AS Wl211.1-1
2.8%W12re+cold-121AS W12n+4-1
2+ E3. V/+2n+5-12. A1 W1
21103-12. B%WI2h+tr-I2h As
WBM+1l-12e E3. WB+s+9-Us
/! lk, W121%09-121 BsW, 2I
,,・ AS W122+421 BS
W121103・AS W12h+:b
BsW12fi+6・A\WH+146. BNW+2
Re-7・AS'k12h*), BlW, 2. . to,
AS W121110+ E3. W1211゜I
II, A, W12n+lI+ BNQ,. ,,,
Q12r+vl, Q, 2. ,,
Q12h+3). In the first encoder (8), number of words in one block: (n=28), number of bits in one word: (n=8), number of check words:
(K=4> encoding is performed.

These 24 PCM data sequences and 4 checkword sequences are supplied to an interleaver (9).

The interleaver (9) changes the position of the transmission channel so that a check word sequence is interposed between the PCM data sequence consisting of even-numbered words and the PCM data sequence consisting of odd-numbered words, and then performs interleaving for interleaving. Delay processing is being performed. This delay processing
(for each of the other 27 transmission channels, ID, 2D, 3D, 4D...2
This is done by inserting a delay circuit with a delay amount of 6D, 27D (where D is a unit delay amount, for example, 4 words).

At the output of the interleaver (9), 28 data sequences in a second arrangement state appear, from which one word is taken out from each data sequence and fed to the encoder (10). Check word P12111P1□Il+-
1+ P l 211+-2+ P l 2 n *
3 is formed. The second error correction block consisting of 32 words including the second check word is:
It will be as below.

(WI 211-12AW+ 211-12 <no
+> 1B31V12a* l+ 12 (211°+
>kW+sa*+-+ztso-+), Bsw, 2. +
l-12 (4D-11+ to R2+1-4-+2 (Si
l) IByJ12n+5-12 (@l)*l), A,
WI2R0s-nno*o+BQ+2n-+it+ho
>, Q+zn*+-+2 (1, o>, Q+zh+z-+
B+4o), QHh*3-H(+5111,'vV+2
M1o-12(2*o)lAwlzn +o-+ 1<
xso>, B'JJ city h+ +-12 (2801shi\,
M/+znmu-+ztzto++BP 12. ,,
P 12h. 8, P12n. 2.P.
I211-3) An interleaver (11) in which an l-word delay circuit is inserted is provided for even-numbered transmission channels among the 32 data sequences including the first and second check words. and inverters (12) (13)(
14) (15) is inserted. Interleaver (11)
) to deal with the fact that an error that spans the boundary between blocks is likely to result in an error in the number of words that cannot be corrected. Inverters (12) to (15) are provided to prevent malfunctions in which all data in one block becomes "0'" due to dropout during transmission, and the reproduction system determines this as correct data. It is being An inverter may also be inserted for the first checkword series for the same purpose.

Then, 3
Each two words are serialized, and as shown in FIG. 2, a 16-pit synchronization signal is added to the beginning of the data to form one transmission block and then transmitted. In FIG. 2, one word taken out from the first transmission channel is indicated as "U" for ease of illustration. Specific examples of transmission systems include magnetic recording and reproducing devices, rotating disk devices, and the like.

The above encoder (8) relates to the error correction code as described above, where (n=28.m=8.=4),
A similar encoder (10) has (n = 32. m = 8.
k==4).

The reproduced data is applied to the input of the error correction decoder shown in FIG. 3 every 32 words of one transmission block. Since this is playback data, it may contain errors. If there were no errors, the 32 words added to the input of this decoder would result in 32 words appearing at the output of the error correction encoder.
Matches the word.

The error correction decoder performs a dinterleave process corresponding to the interleave process in the encoder to restore the data order and then perform error correction.

First, a dinterleaver (16) in which a 1-word delay circuit is inserted is provided for the odd-numbered transmission channel, and an inverter (16) is provided for the check word series.
7) (1g) (19) (20) are inserted and supplied to the first stage decoder (21). In the decoder (21),
As shown in FIG. 4, from the parity check matrix Hcl and the input 32 words (V”), the syndrome SIO+
S IIs S 12+S 13 are generated and error correction is performed based on this. α is (F(X)
=x''+x'+x'+x''+l) is an element of G F (2'). From the decoder (21), 24 PCM data sequences and 4 check word sequences appear, and each word of this data sequence has at least one check word sequence indicating the presence or absence of an error.
A bit pointer (“1” if an error is included, “0′” otherwise) is added. In FIG. 4 and FIG. 5, which will be described later, and in the following explanation, one received word W1 is expressed as WI.

The output data sequence of this decoder (21) is supplied to a dinterleaver (22). The dinterleaver (22) is for canceling the delay processing performed by the interleaver (9) in the error correction encoder.
From the first transmission channel to the 27th transmission channel (27D, 26D, 25D...2D,
A delay circuit with a delay amount different from that of the LD) is inserted. The output of the dinter leaver (22) is sent to the next stage decoder (
23). In the decoder (23), as shown in FIG. 5, a syndrome S2o is generated from the parity check matrix HC2 and the input 28 words.

521, S2□, and S23 are generated, and error correction is performed based on these.

The data sequence appearing at the output of the next-stage decoder (23) is supplied to an even-odd interleaver (24).

The even-odd dinter leaver (24) returns the PCM data series consisting of even-numbered words and the PCM data series consisting of odd-numbered words so that they are located on different transmission channels, and also returns the PCM data series consisting of odd-numbered words to different transmission channels. A one-word delay circuit is inserted for the PCM data series. At the output of this even-odd interleaver (24) there is a
M data series will be obtained. Although not shown in FIG. 3, a correction circuit is provided next to the even-odd dinterleaver (24) to make errors that cannot be corrected by the decoders (21) and (23) less noticeable. Corrections, such as average value interpolation, are performed.

In an example of the present invention, in the first stage decoder (21), 1
I even try to correct word errors.

If it is detected that there are 27 words or more errors in one error correction block, the error is detected for all words in this error correction block except for 32 words or check words <28 words. At least a 1-bit pointer is added to indicate that there is. For example, this pointer is set to "1" when there is an error, and "0" otherwise. Note that during the first stage decoding, even when the above-mentioned predetermined number of words is corrected, a dinter indicating that an error exists may be added.

If the l word is 8 bits, a pointer is added as 1 bit higher than the most significant bit, and 1 word is 9 bits.
The signals are converted into bits, processed by a dinterleaver (22), and supplied to the next stage decoder (23).

The next stage decoder (23) performs error correction using the number of error words or error locations in the first error correction block indicated by this pointer. FIG. 6 shows an example of error correction in the next-stage decoder (23). In FIG. 6 and the following explanation, the number of error words by the pointer is represented by Np, and the error location by the pointer is represented by Ei. It is expressed as Further, in FIG. 6, Y represents affirmation and N represents negation.

(1) Syndrome S2゜~S23 to check if there is an error
Find out by. (S2o= 521= 522= 5
When zs=0), it is assumed that there is no error. In that case,
Check whether (N p≦2+). (N p≦2+)
If so, it is determined that there is no error, and the pointer in that error correction block is cleared (“0”).

If (Np>z+), leave the pointer as it is, assuming that the syndrome detection is incorrect, or
Set the pointers of all words in the block to "1". Let zl be quite large, for example 14.

(2) If there is an error, check whether it is a one-word error by calculating the syndrome. In case of l word error, find the error location i. It is detected whether the error location l determined by this syndrome calculation matches the location determined by the pointer.

If there are multiple error locations by pointers, it is checked to see if it matches any of them.

If (S=Ei), then it is checked whether (Np≦zz). For example, 22 is 10. (Np≦22>
If so, this is determined to be a 1-word error, and the 1-word error is corrected. If (Np>22), it is dangerous to judge that it is a one-word error, so either the pointers are left as they are, or all words are regarded as errors and each pointer is set to 1''.

In the case of (l~Ei), it is checked whether (Np≦zi). z3 is a fairly small number, for example 3.

When (N p≦23) holds, the one-word error at error location l is corrected by syndrome calculation.

In the case of (Np>Zs), it is further checked whether (Np≦24). In other words, when (zs<Np≦24), it means that Np is too small even though the judgment of a one-word error due to the syndrome is incorrect, so the pointers of all words in that block are set to "1". do. Conversely, if (Np>z4), the pointer is left as is.

For example, z4 is 5.

(3) In the case where there is no single word error, (Np≦zs
), and if (Np≦ZS), the reliability of the pointer is poor, so the pointers of all words are set to "1". When (Np>z,), the pointer is left as is.

(4) As shown by the broken line in FIG. 6, it is also possible to correct up to M words using the error location using a pointer. For example, it is possible to correct up to 4 word errors. In this case, the error is corrected based on the error location indicated by the pointer. (Nj
) to M), leave the pointers as they are or change the pointers of all words to indicate an error.

Note that the number of pointers indicating errors in one block is Np.
The specific numerical values of comparison values z1 to z are only −
This is an example. The error correction code in the above example may determine that there is no error if there are 5 or more word errors, and it may determine that it is a 1 word error if there are 4 or more word errors. Therefore, the comparison value can be set to an appropriate value in consideration of the probability of such oversight or erroneous correction.

In the error correction decoder shown in FIG. 3, the first check word Q12111 Q1211411 Q+211
$21 Error correction and second check word P12111P +2h + P l 2 using Q12h+3
Error correction using R+2w P l 211+3 is performed once each. If each error correction is performed at least twice (actually, about twice), the error reduction resulting from the correction can be utilized to further increase the error correction ability. can.

In this way, when a decoder is provided at a later stage, it is necessary to also correct the check word in the decoder (21) (23).

In addition, in the above example, the delay amount is varied by D as the delay processing in the interleaver (9), but unlike this regular change in the delay amount, it may be irregular. . Also, the second check word P+
is an error correction code that includes not only PCM data but also the first check word Q1. Similarly, it is also possible for the first check word QI to also include the second check word P1. Specifically, the second check word P may be fed back and supplied to the encoder that forms the first check word.

Note that even when a one-word error is corrected in the first-stage decoder (21), the pointers of all words in the error correction block containing this corrected one word are
”, it is possible to further prevent detection errors and incorrect corrections.

〔Effect of the invention〕

According to the present invention, by using Aα21+13α'+C=Q, which is obtained assuming that there is a two-word error in the data received as an error location polynomial, the coefficient A of this equation.

You can easily check the number of errors using B and C. The coefficients A, B, and C are also used in calculations for determining error locations and error values.

Therefore, error correction work is simplified and processing time can be shortened.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of an example of an error correction encoder to which the present invention is applied, Fig. 2 is a block diagram showing an arrangement during transmission, and Fig. 3 is a block diagram of an example of an error correction decoder. , FIG. 4, FIG. 5, and FIG. 6 are diagrams used to explain the operation of the decoder of the error correction decoder.

(1) (9) (11) is an interleaver, (8) (
10) is an encoder, (16) (22) (24) is a dinterleaver, and (21) (23) is a decoder.

Claims (1)

[Claims] One block consists of 1.n words, and the parity matrix H is: ▲There are mathematical formulas, chemical formulas, tables, etc.▼ However, α is an irreducible polynomial on GF(2) as F(X). It is a root that satisfies F(X)=0 when When expressed as, 1 block of data V^r consisting of received n words
From the above parity check matrix H, ▲ There are mathematical formulas, chemical formulas, tables, etc. ▼ By calculating the four syndromes S_0, S_1, S
In the method of calculating _2S_3 and correcting errors based on this syndrome, the error location polynomial Aα^2^1+Bα^1+C=0 is obtained assuming that there is a 2-word error in the received n-word data, where i is an error. The coefficients A, B, and C of each term of location are calculated from the above respective syndromes, and this coefficient is A=B=
When the relationship C=0 is satisfied, it is determined that there is no error or a 1-word error exists, and when the above relationship is not satisfied, it is determined that there is an error of 2 or more words, and it is determined that a 1-word error exists. Sometimes this 1-word error is corrected, and when it is determined that there is an error of 2 or more words, the 2-word error is corrected using each of the above coefficients A, B, and C, and the existence of more errors is detected. error correction method. 2. The error correction method according to claim 1, wherein the absence of an error or a one-word error is determined by checking whether the syndrome is zero together with the relationship A=B=C=0. 3. The error location polynomial is α^2^i+Dα^i+E=0, where i is the coefficient D of each term when the error location is taken as
, E and D^2/E are obtained using the above coefficients A, B, and C, and when the relational expression between D^2/E and the error location difference t when a 2-word error exists is satisfied. The error correction method according to claim 1, wherein it is determined that a two-word error exists. 4. An error correction method in claim 3, wherein the relational expression between D^2/E and the error location difference t is D_2/E=α^-^t+α^t. 5. The error correction method according to claim 3, wherein each error location is determined based on the error location difference t and the coefficient D, and the error indicated by this error location is corrected. 6. When the respective error locations are i and j, the error locations i and j are α^i=D/(1+α^
t) The error correction method according to claim 5, wherein the error correction method is determined from α^j=D/(1+α^-^t). 7. Let the respective error locations be i and j when there is a 2-word error, and the respective error patterns e
4. The error correction method according to claim 3, wherein _i and e_j are determined using a coefficient D, and error correction is performed based on this error pattern. 8. The error pattern e_i is (α^jS_0+S_1)/D or S_0/Y using the error location difference t.
+S_1/D However, it is determined by Y=1+α^-^t, and the error pattern e_i is (α^iS_0+S_1)/
D Or using the error location difference t, S_0/X
+S_1/D, where X=1+α^t. The error correction method according to claim 7.