JPS5830612B2 - Erroneous track priority instruction correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a plurality of error detection circuits that determine the presence or absence of an error track by detecting different contents, and a predetermined number of The present invention relates to an improvement in an information transfer system having an error information correcting means capable of correcting error information about a track, and an error track pointer indicating a track to be corrected for an error to the correcting means based on the output of each detection circuit.

For example, in a system that transfers information on a plurality of tracks in parallel, such as a magnetic recording/reproducing device, it has conventionally been possible to modify information up to a predetermined number of tracks by calculating a generator polynomial.

In this case, the track to be corrected is indicated to the correction circuit as error track pointer information, but conventionally, error track pointer information has been provided in the form of the sum of the following four types of error contents:

■ Invalid (1NVALiD) track: When data other than the specified data pattern is read,
It is determined that the data for that track is completely incorrect.

2. DEAD track: If an error of a certain length or more occurs on a certain track, that track is considered unreliable, so it is forced to 1NV.
ALiD) into a rack.

3. Collection (C?5RRECTioN)) rack: This is the track on which corrections have been made, and subsequent data may also contain errors.

4. Phase error (PHASE-ERRoR) track: If an excessive phase shift occurs in the read data interval, there is a possibility of erroneous data discrimination.

Since the correction ability is determined by the number of redundant bits, the less redundant bits there are, the more reliably the error track needs to be provided.

This is because it is easy to see that if error tracks exceeding the correcting ability are provided unnecessarily, the correcting operation cannot be performed normally.

Currently, all error tracks detected by each error detection circuit are provided in the form of a sum as error track pointer information, so the number of tracks instructed from the error track pointer to the error correction circuit is corrected. The number of tracks that can be corrected by the circuit (correction ability) is likely to exceed.

In this way, when the number of error tracks exceeds the correction capability, it is treated as an uncorrectable error.

However, it cannot be said with certainty that the uncorrectable condition at this time is uncorrectable.

This is because the error track pointer information contains C stone R.
RECtion track, PHASE・ERRoR
This is because uncertain error elements such as tracks are included.

The present invention has been made to solve the above problems,
The purpose is to reduce the probability that an error correction circuit becomes uncorrectable.

In order to achieve this object, the present invention gives priority to a plurality of error detection means that determine the presence or absence of an error from different viewpoints according to the importance of the error, and these error detection means and A correction target selection means is interposed between the error track pointer and the error track pointer, and when the number of error tracks detected by the highest priority detection means exceeds the correction ability of the error correction means, it is treated as uncorrectable, and the range of correction ability is When the error track pointer is within the range, the error track pointer is controlled so that the error tracks detected by the lower detecting means are sequentially added to the correction target.

For example, the priority is i NV where the data is completely wrong.
The AL i D track and the DEAD track are given first priority, and when the number of these error tracks exceeds the correction ability of the error correction means, they are treated as uncorrectable.

As the second priority error track Import the CoRRECTioN track.

In this track, since correction processing has been performed on the data one disk before, there is a high possibility that the next data will also be incorrect.

The third priority error track is PHASE・ERR
Import the oR track.

This track shows that because there are variations in the intervals of the read data, there is a possibility of erroneously determining whether the data is 1'N011.

In the present invention, error tracks and
When adding second and third priority error tracks to the pointer, if the number of tracks to be corrected exceeds the ability of the correction means, the error tracks with lower priority at that point
The truck excludes the modification and executes the modification action.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Reference numeral 14 denotes a pass line that transfers data for nine tracks in parallel, for example. Data on this pass line is checked for data intervals by a phase error detector 1 and stored in a skew buffer 2.

When a predetermined number of bytes of data are stored in the skew buffer 2, they are outputted to the pass line 15 in units of correction units, one data group at a time, and stored in the group buffer 4.

At this time, the data pattern checker 5 connected to the pass line 15 checks whether each track in the data group has a pattern other than the predetermined data pattern.

Now, if there is incorrect data on one of the tracks.
When a pattern is detected, information indicating the track is sent out from the pass line 16 as 1NVALiD track information.

Reference numeral 10 denotes an error track pointer, which sends out information indicating the error track to the pass line 17 when an error is indicated for several data groups in the same track consecutively.

This content and the skew error information 18 output from the skew error detector 32 are taken into the DEAD rack detector 3 and sent to the pass line 19 as DEAD track information.

DEAD) rack information is added to the data pattern checker 5 and output to the bus line 16 as 1NVALiDh rack information.

The data taken into the group buffer 4 is also input to the generation arithmetic unit 20 along the way, and it is determined whether or not there is an error in the data by performing an operation according to a well-known generation polynomial.

If there is an error, a corrective action start signal is output on line 21.

As a result, the first priority gate 7 opens and 1NVALi
D) Rack information 16 is error track pointer 1
sent to 0.

At this time, the error track counter 12 determines that the sum of the number of tracks in the error track pointer information 23 and the number of tracks in the correction track information 31 output from the correction track latch 30 is a predetermined value (the number of correctable tracks). ) is determined.

If the sum of the number of tracks in the error track pointer information 23 and the correction information 31, 25, is within the correction ability,
The second priority gate 9 is opened by the control signal outputted from the line 24, and the correction track information is also error-free.
captured in a pointer.

Conversely, when the error track counter 12 detects the number of error tracks that exceeds the correction capability, a correction operation is started with the second priority gate 9 closed.

The error track pointer information at this time is 1NVA.
Only LiD track will be available.

Similarly, when the number of tracks is 25 within the correction ability, this value and P
The number of tracks in the HASE/error information 26 is added up by the error track counter 13, and the PHA which is the third priority is added.
A determination is made whether there is room to correct the SE error trunk.

If the above added value is within the correction capability, the third priority gate 8 is opened by the control signal output to the line 2γ, and the PHA
SE error track information is also entered into the error track pointer 10.

If the above-mentioned added value exceeds the correction capability, the third priority gate 8 enters the correction operation while remaining closed.

The error track pointer information at this time is 1NVA.
(LiD) Rack and collection track information only.

It is easy to understand that when the second priority gate 9 is closed, the third priority gate 8 is always closed.

Through the above operations, the information taken into the circuit 10 is input as the error track pointer information 23 together with the generator polynomial operation information 22 to the error bit detection device 11, whereby the error information location is detected and the bus The result is output on line 28.

The correction device 6 corrects the data based on the data in the group buffer 4 and the information on the pass line 28, and transfers the correct data to the upper level.

At this time, the corrected track information is placed on the pass line 29 and stored in the correction track latch 30 for each data group.

You can repeat the same action below.

According to the present invention, when correction is impossible, it is determined based on the number of first priority error track pointers, so that correction is definitely impossible.

This is because the first priority 1NVALiD track has a data pattern other than the prescribed data pattern, and its data is definitely incorrect.

In addition, in the case of the DEAD rack, data is forcibly converted into a predetermined data pattern and stored in the group buffer, so this is also mistaken as the original data as described above.

In addition, within the correctable range, as much as possible elements with a possibility of errors are taken into the error track pointer to assist in corrective actions with high reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Phase error detector, 2...
- Skew buffer, 3...Dead track discriminator, 4...Group buffer, 5...
...Data pattern checker, 6...
・Correction device, γ...First priority gate, 8...
...Third priority gate, 9...Second priority gate, 10...Error track pointer, 11
...Error bit detector, 12, 13...
...Error track counter, 20...
Generator polynomial calculator, 30... Correction track latch, 32... Skew error detector.

Claims (1)

[Claims] 1. On an information transfer path that transfers information from multiple tracks in parallel, a plurality of error detection means each determine the presence or absence of an error track by detecting different contents, and error information capable of correcting error information for a predetermined number of tracks. correction means, and
and an error track pointer means for instructing the correcting means to track an error to be corrected based on the output of the detecting means, wherein each of the detecting means is given priority according to the importance of the error. At the same time, correction target selection means is interposed between the detection means and the error track and pointer means, and the selection means determines that the number of error tracks detected by the highest priority detection means is within the correction capability range of the correction means. The error track priority instruction correction method is characterized in that, when the error track pointer is input to the error track pointer, the error track detected by the lower detecting means is added to the correction target.