JPS6345924A - Error correction method - Google Patents

Abstract

PURPOSE:To contrive to improve error correction capability by applying the error correction processing of a reception word based on a 2nd check word and setting a pointer representing the presence of an error to each word and utilizing the pointer so as to apply error correction processing based on a 1st check word. CONSTITUTION:Syndromes S11, S12, S13, S14 are generated from a parity check matrix Hc1 and an inputted 32-word VT in a decoder 21 and the error correction is applied based on them. From the decoder 21, 24-set of PCM data series and 4 check word series appear and the pointer representing the presence of the error is added at each word of the data series. The output data series of the decoder 21 is fed to a de-interleaver 22 cancelling the delay processing executed by the interleaver. The output of the deinterleaver 22 is fed to the 2nd decoder 23 to generate the syndromes S21, S22, S23, S24. Error correction is applied based on them. The pointer relating to the word whose error is corrected is cleared in the decoder 23.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an error correction method capable of correcting errors with high error correction ability for both burst errors and random errors.

[Conventional technology]

The applicant of the present application has previously proposed a method called cross interleave as a data transmission method effective against burst errors. This generates a first check word sequence by supplying one word included in each of the PCM data sequences of a plurality of channels in a first arrangement state to a first error correction encoder. A second check word sequence is generated by putting the check word sequence and the PCM data sequence of multiple channels into a second arrangement state, and supplying one word included in each to a second error correction encoder. Double interleaving (arrangement rearrangement) is performed in units.

Interleaving distributes and transmits check words and PCM data included in a common error correction block,
This is intended to reduce the number of error words among a plurality of words included in a common error correction block when the original arrangement is restored on the receiving side. In other words, when a burst error occurs during transmission, this burst error can be dispersed. If such interleaving is performed twice, each of the first and second check words will constitute an error correction block, so even if an error cannot be corrected with one of the check words, the other one can be used to correct the error. Errors can be corrected, and the error correction capability can therefore be further improved.

[Problem that the invention seeks to solve]

By the way, ■If even one bit in a word is incorrect, the entire word is treated as incorrect, so when handling received data with relatively many random errors, the error correction ability is not necessarily sufficient. I can't say that there is.

[Means for solving problems]

In the present invention, an error correction encoder configured to form check words for n input words based on a parity check matrix H shown below includes a and at least a word included in each of the plurality of channels of PC platform data series that is completely identical to the word provided to form the first check word. A second check word sequence is formed by supplying words that do not match to the error correction encoder configured as described above, and the PCM data sequence of the plurality of channels and the first and second check word sequences are transmitted. , receives this transmitted data, performs error correction processing on the received word based on the second check word, and sets a pointer indicating the presence or absence of each word error to indicate the presence or absence of the above-mentioned error. The pointer is used to perform error correction processing based on the first check word.

Or, however, α is the irreducible polynomial on G F f21
When it is +, it is a root that satisfies Kini, (FMXl=0).

[For production]

According to the above-mentioned error correction code, it is possible to correct up to a 2-word error within the 1st pro/2nd line, and when the error position is known, it is also possible to correct a 3-word error or a 4-word error. Since this error correction code is combined with multiple interleaving, sufficient error correction ability can be obtained even for received data with relatively many random errors.

Furthermore, the error correction code used in the present invention has the feature that when only one word' error is to be corrected, the structure of the decoder can be greatly simplified.

(Example) First, an error correction code used in the present invention will be explained. When describing an error correction code, a vector expression or a cyclic group expression is used. First, G F (on 2+, irreducible m-order Consider the polynomial F (Xl. “0”
On the field G F T21 in which there is only an element of "1", the irreducible polynomial F (Xl has no roots. Therefore, (
Consider a virtual root α that satisfies F(Xl=o). At this time, 2'' different elements 0, α, α2, α3α angle −1 expressed as powers of α including the zero element are the extension field GF (2
”). GF (2t′) constitutes II (2
It is a polynomial ring modulo F(x), an irreducible polynomial of degree m over +. The elements of GF(2') are 1. ct= (×)
.

α2・(X") l '----1 α'"-1=(×
−1) can be expressed as a linear combination of That is, ao+a+ (x) + 82 (x2) + -・
+ am-1(x”-’)” ao+al α+ a
2α” ””-””-””-”--+ a, -, c
x ”-1 or (all-1+ am-□, '-'
-'+ a2. at, ao) where ao= all
-------+ am-I GF+pl.

- As an example, considering GF(2”), (II+od
, F fx) =x'+ x'+ x3+ x2+
In 1), all 8-bit data is a7x'+86
X″'+ 85X'+ a4χ'+ a3X3+
a2x”+a, x+a.

or (a?+ abIas+ a4+ a3+ all
all ao), so for example, an is assigned to the MSB side and ao is assigned to the LSB side. a,,,G
F (belongs to 21, so it is 0 or 1.

Also, the following matrix T of polynomial F (Xl to (mXm)
is guided.

Another representation uses cyclic groups.

This utilizes the fact that the 0 element is removed from GF (2'') and the remaining elements form a multiplicative group of order 2'''-1. When the element of GF(2') is expressed using a cyclic group, it is 0.1
(-α2m-+), α, α2. α3, α2I″
-2.

Now, in this invention, when one word is made up of m bits and one block is made up of n words, check words are generated based on the following parity check matrix H.

Furthermore, the parity check matrix 11 can be similarly expressed by the matrix T.

However, I is a unit matrix of (m×m).

All of the above expressions are essentially the same, and the first column may be all l or I, and the configuration up to the (n-1)th column may be adopted. Furthermore, the error correction code will be described in detail using an example of four (k=4) error correction codes.

One block of received data is expressed as a column vector V-(W, .

W2. W3. ---W, ,>, then four syndromes S +, S z, S 3. occur on the receiving side. S
a becomes.

4 check words in 1 block <p=W11-3
1 Q = WM-21r = Wn-I+ S =
Wn) is included. This check word is obtained as follows. However, Σ means Σ.

A check word can be obtained by solving the above-mentioned simultaneous equations. The calculation for this is GF (2”
), the process is omitted,
The results are shown below.

Next, error correction when data including a check word formed as described above is transmitted and received will be described. The apron is that a pointer indicating the error location is not used.

(1) When there is no error: S+ =S2=S3=
S4" 0 [2] In case of 1 word error (error pattern is el) '5I=ei 5z=T'ez
S3=T" e (5a=T" e = Therefore, all of the following relationships hold true. At that time, the syndrome S
1 is the error pattern e1 itself.

[3] In the case of a 2-word error (et+e,) If the above equation is transformed and the following holds true, it is determined that it is a 2-word error, and the error pattern at that time is S++T-'Sz S++T
-is.

[4] 3 word error (ei + ej +
ek) Therefore, from the above formula, T'(Tj(TkS++h)+(TI'Sz+33))
- If T'(T'Sz+33)+(TkS3+Sa) is established, it can be determined that there is a 3-word error. However, (S,
≠0. S2≠0. The condition is that S3≠0). Each error pattern at that time can be corrected up to all 2-word errors without using a pointer, such as 1. Furthermore, if the error position (i, j, 1) is known using a pointer, a 4-word error can also be corrected.

Note that if the number k of check words is further increased, the error correction ability is further improved.

Hereinafter, a specific example in which the present invention is applied to recording and reproducing audio PCM signals will be described with reference to the drawings. FIG. 1 shows the entirety of an error correction encoder provided in a recording system, and an audio PCM signal is supplied to its input side. The audio PCM signal has a sampling frequency of f, (for example, 44.1
(k)Iz) ) and converting one sample into one word (16 bits in 2's complement code). Therefore, for the left channel audio signal, (L O+ L l,
PCM data in which each word is consecutive is obtained as L 2------), and for the right channel audio signal also (
PCM data in which each word is consecutive is obtained as RO+R1+Rz, -). The PCM data of the left and right channels are divided into 6 channels each, and a total of 12 channels of PCM data series are input. At a predetermined timing, (L6-, R6, , L6., .I+ R
6n. 1゜L6n+z+ Rbn+t+ L6a+
3+ R6n+3+ L6n14+ Rhnk<
) are input. In this example, one word is divided into upper 8 bits and lower 8 bits, and 12 channels are further processed as 24 channels.

For simplicity, one word of PCM data is represented as a beast, and for the upper 8 bits, a suffix of ``Wi+A'' is added, and for the lower 8 bits, a suffix of ``Wi+I'' is added.
and B suffixes are added to distinguish them. For example, L
6. , is divided into two parts, -1°n+A and -1□n+B.

This 24-channel PCM data sequence is first supplied to the even-odd interleaver fll. (n=0°1.
2--), then L6-(=IL□n+Asl'l
+□Il+l+), R6ga (= H+ z n + I
+ a-en12n・1,6)・L6n・2("lQ+z
n・4・＾・$1121144111) % Ran+
z(=l'l1gn+s+as W+zn+5+B)
%Lan+4(=W+zn+s+As WI2n+ll
+B), Rbn+a (=W+za+q+a, -1°11
+9+l) are even-numbered words, and the other words are odd-numbered words. Each of the data sequences (PC)'l consisting of even-numbered words is an even-odd interleaver fl.
1 word delay circuit (2A) (2B) (3A)
(3B) (4^) (4B) (5A) (5B) (
6A) (6B) (7A) (7B) delays by one word. Also, in the even-odd interleaver (1),
The 12 data series consisting of even-numbered words are the first to
It occupies up to the 12th transmission channel, and the 12 data sequences consisting of odd-numbered words are converted so as to occupy the 13th to 24th transmission channels.

The even-odd interleaver (1) is used to prevent errors in two or more consecutive words of each of the left and right stereo signals, and to prevent this error from becoming uncorrectable. For example, considering three consecutive words (L+-+, L;, Li++), if L is incorrect and this error cannot be corrected, then -1 or -1. It is hoped that 1 is correct. It is useful when correcting incorrect data, by interpolating (previous value hold) with the previous correct word Li-1, or by interpolating (previous value hold) Ll-1 and Ll. This is to interpolate with an average value of 1.

Even-odd interleaver (1) delay circuit (2A) (2B
) to (78) (7B) are provided to ensure that adjacent words are included in different error correction blocks. Furthermore, the reason why transmission channels are grouped for each data series consisting of even-numbered words and data series consisting of odd-numbered words is that when interleaving is performed, the recording positions of adjacent even-numbered words and odd-numbered words are This is to make the distance between them as large as possible.

At the output of the even-odd interleaver (1), a PCM data sequence of 24 channels in the first arrangement state appears, and one word is extracted from each of them and supplied to the encoder (8), where it is checked by the first checker. Word Q1□7゜QI2h+l
+ QIZn+2+ Q+zn+s is formed. 1st
The error correction block composed of check words is (W, □I, -1□, A% Wlgm-+□13, 1
゜1, -1□57.1□7.1-1□, 8.1□□4
-1□, W1□□4-1□18, W1□, l+1-1
□, W1□, 5-1□, 8, W1□Be1l-12+
A% L□n+8-1□, 8% W+zn+q-+□
11, parable, □1゜, -1□,.

Wlzn+z, as Lzn+z+++X
W+z+++z1n, ' l N * + 3
+B %W12n+6. As Wl. nib,
8% Wl□ll+7.11% l'l+
□1147.8%W1211+IO+A, l'112
n+IO+8. , WIZn+Il+As W12n+
Il+BsQ12n, Q+zn++,
'126+2, b, 2□3, ). In the first encoder (8), the number of words in one block is:
(n-28), number of bits per word: (n=8), and number of check words: (k=4).

These 24 PCM data sequences and 4 checkword sequences are supplied to an interleaver (9).

The interleaver (9) changes the position of the transmission channel so that a check word sequence is interposed between the PCM data sequence consisting of even-numbered words and the PCM data sequence consisting of odd-numbered words, and then performs interleaving for interleaving. Delay processing is being performed.

This delay processing is performed for each of the other 27 transmission channels excluding the first transmission channel.
31), 4D, ----, 26D, 27D
This is achieved by inserting a delay circuit with a delay amount of (D is the unit delay amount).

At the output of the interleaver (9) there appear 28 data sequences in a second constellation, from each of which one word is taken out and fed to the encoder OI,
Second check word P1□n+ P+zn++.

P12n. 2. P1□,. 3 is formed. The error correction block consisting of 32 words including the second check word is as follows.

(-1□1l-121A% I'll□n-1□+
Il++. 18% W+□n+l-Hf2111+
A, -1□□1-1□131+Il+18, W+znn
-+zf4o+o, ^, Fn+4-12 +SD+11
, 8% W+ 21145-12 f60+Il
A% 1'1121145-1217De11. B
%QIZn-1211! DJ, Q+zn++-
+z++:+D), QIffin+2-12 f
14o), B12n+3-H11501, W12
n+l0-12(taD), A%WI2n+Il+-1
2+2SDl+B, W+zn+++-+z(g6p),
a, W12n+11-+2 (170), B, Pl□,
, P1□. . I, PI! n+2, P1
2nya3) Among the 32 data sequences including the first and second check words, an interleaver 0υ in which a 1-word delay circuit is inserted is provided for even-numbered transmission channels, Furthermore, an inverter @01αa051 is inserted for the second check word series. The interleaver αD deals with the fact that an error that spans the boundary between blocks is likely to become an error in the number of words that cannot be corrected.

Inverter tap 09 is provided to prevent a malfunction in which all data in one block becomes 0'' due to dropout during transmission, and the reproduction system determines this as correct.

Then, 3
Each two words are serialized, and as shown in FIG. 2, a 16-bit synchronizing signal is added to the beginning of each word to form one transmission block and then transmitted. In FIG. 2, one word taken out from the first transmission channel is indicated as U for simplicity of illustration. Specific examples of the transmission system include magnetic recording and reproducing devices, rotating disk devices such as optical disks, and the like.

The above encoder (8) relates to the error correction code as described above, where (n=28.m=8.=4),
A similar encoder α0 is (n=32. m=8°k=4)
It is.

The reproduced data is applied to the input of the error correction decoder shown in FIG. 3 every 32 words of one transmission block. Since this is playback data, it may contain errors. If there were no errors, the 32 words added to the input of this decoder would result in 32 words appearing at the output of the error correction encoder.
Matches the word.

The error correction decoder performs deinterleaving processing corresponding to the interleaving processing in the encoder,
Error correction is performed after restoring the data order.

First, a deinterleaver αe in which a one-word delay circuit is inserted is provided for odd-numbered transmission channels,
Also, for the checkword series, the inverter 0η(I
I Ql 0111 is inserted and the first decoder (21)
supplied to In the decoder (21), as shown in FIG. 4, the parity check matrix Hc and the input 32 words (V''
) From, Schiff F Low L' S+ ++S+z
+S+3+S+a is generated, and the error correction described above is performed based on this. α is (F(x)=x”+
GF (2B)) of x'+ x3+ A pointer (at least l bits) indicating the presence or absence of an error is added to.

The output data sequence of this decoder (21) is supplied to a deinterleaver (22). The deinterleaver (22) is for canceling the delay processing performed by the interleaver (9) in the error correction encoder.
Delay circuits with different delay amounts (27D, 26D, 25D, --1111--20,1n) are inserted from the th transmission channel to the 27th transmission channel. The output of the deinterleaver (22) is fed to a second decoder (23). Decoder (23)
Now, as shown in FIG. 5, the parity check matrix 11c2
and the input 28 words, the syndrome Sz+, S
t□.

SZ3+S24 is generated, and based on this, error correction as described above is performed. Pointers related to words whose errors were corrected in the decoder (23) are cleared, and pointers related to words containing errors that could not be corrected by the decoder (23) are not cleared.

The data sequence appearing at the output of the decoder (23) is supplied to an even-odd deinterleaver (24). In the even-odd deinterleaver (24), the PC consisting of even-numbered words is
The M data series and the PCM data series consisting of odd-numbered words are returned to positions on different transmission channels, and a one-word delay circuit is inserted for the PCM data series consisting of odd-numbered words. ing. At the output of this even-odd deinterleaver (24), a PCM data sequence is obtained having exactly the same arrangement and predetermined number of transmission channels as that supplied to the input of the error correction encoder. Although not shown in FIG. 3, a correction circuit is provided next to the even-odd deinterleaver circuit 4) to make errors that could not be completely corrected by the decoders (21) and (23) less noticeable. Corrections, such as average value interpolation, are performed.

In the error correction decoder shown in Figure 3 of Jin, the first check word PI2+ PI2□1+ P1211+2+
Error correction using PIRh+3 and second check word (1+zi.

Error correction using Q1□n+I+ Ql□n+zl and □0° is performed once each. If each of these error corrections is performed at least twice (actually, about twice), the error reduction can be utilized more than the corrected result, and the error correction ability can be further increased. can.

FIGS. 6 and 7 show other second configurations of the error correction encoder and error correction decoder, respectively, which are commonly used in the present invention. The difference between the configuration in Figure 1 and the configuration in Figure 6 is:
There are 2 delay trenches installed in the interleaver (25).
word-by-word, the encoder (8) is located between the two groups of code channels, the interleaver (26) consists only of delay circuits, and all check words are In addition, the way the channels are transposed in the interleaver (25) is also different from that in FIG. In other words, the 24 human-powered channels are divided into three groups of eight channels each, and are grouped into two channels, with the first and second channels in each group.

The third and fourth two channels are arranged in order. Further, the configuration of the decoder shown in FIG. 7 corresponds to the encoder shown in FIG. 6.

FIGS. 8 and 9 show still another third configuration of an error correction encoder and an error correction decoder to which the present invention is applied. The configuration of FIG. 8 differs from the configuration of FIG. 6 in the configuration of the interleaver (29). In this interleaver (29), the input side is divided into groups of 6 channels, the first 6 channels and the third group of 6 channels are delayed by 2 words for each channel, and the other 2nd and 4th channels are delayed by 2 words for each channel. Groups of 6 channels are prevented from being delayed. Along with this, the method of transposing channels is also different. In other words, it is grouped every 2 channels, and with a cycle of 12 channels,
Two channel sets are arranged in order.

The error correction decoder shown in FIG. 9 corresponds to the configuration shown in FIG. 8.

FIG. 1n and FIG. 11 show still another fourth configuration of an error correction encoder and an error correction decoder to which the present invention is applied. The configuration of FIG. 1n is the same as that of FIG. 8 except for the interleaver (31).

In this example, the coding channels are divided into three groups. The first group consists of interleavers (3
1) is not delayed, the second group is delayed by one word period, the third group is delayed by two word periods,
Also, no channel transposition is performed. As before, the arrangement in FIG. 11 corresponds to the configuration in FIG. 1n.

The configurations shown in FIGS. 6 and 7 described above are suitable for two-channel (stereo) audio, and the configurations shown in FIGS. 8 and 9 are suitable for two-channel (stereo) audio.
The configuration shown in the figure is suitable for use in 3-channel audio, and the configurations in Figures 1n and 11 are suitable for use in 4-channel audio.

In addition, in the above example, the delay amount is varied by D as the delay processing in the interleaver (9), but unlike this regular change in the delay amount, it may be irregular. . Also, the second check word P,
is not only the PCM data but also the first check word Q
This is an error correction code that also includes 1. Similarly, the first check word Q is the second check word P.

It is also possible to include. Specifically, the second check word P may be fed back and supplied to the encoder that forms the first check word.

〔Effect of the invention〕

As understood from the above explanation, according to the present invention,
It uses an error correction code that can correct up to two word errors without using a pointer to indicate the error position, and also uses cross interleaving to disperse burst errors, so random errors and burst errors are eliminated. Effective error correction can be performed for either case. In the error correction code according to the present invention, the decoding algorithm becomes more complicated as the number of correctable error words increases. If only one word error is to be corrected, a decoder with a very simple configuration can be used. Therefore, it is easy to prepare multiple grades of error correction decoders ranging from low to high correction capabilities, and this is suitable for use in cases such as rotating disk playback devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of an error correction encoder to which the present invention is applied, FIG. 2 is a block diagram showing an arrangement during transmission, FIG. 3 is a block diagram of an example of an error correction decoder, and FIGS. 5 is a diagram used to explain the operation of the decoder of the error correction decoder, FIGS. 6 and 7 are block diagrams of other examples of the error correction encoder and error correction decoder to which the present invention is applied, and FIG. 9 and 9 are block diagrams of other examples of an error correction encoder and an error correction decoder to which this invention is applied, and FIGS. 1n and 11 are block diagrams of an error correction encoder and an error correction decoder to which this invention is applied, respectively FIG. 7 is a block diagram of still another example of a correction decoder. (11(91αυ is the interleaver, (8)α0) is the encoder, 00(22) (24) is the deinterleaver, (
21) (23) is a decoder.

Claims (1)

[Claims] 1. Each of the PCM data sequences of a plurality of channels is input to an error correction encoder configured to form k check words for n input words based on a parity check matrix H shown below. A word included in each of the PCM data series of the plurality of channels is supplied to form a first check word sequence, and at least a word included in each of the PCM data series of the plurality of channels is supplied to form the first check word. A word that does not completely match the word is supplied to the error correction encoder having the above configuration to form a second check word series, and the PCM data series of the plurality of channels and the first and second check word series are combined with each other. is transmitted, this transmitted data is received, and errors in the received word are corrected, the method includes performing error correction processing on the received word based on the second check word, and checking whether or not each word has an error. An error correction method in which a pointer indicating the presence or absence of an error is set, and an error correction process is performed based on the check word in 1 above using the pointer indicating the presence or absence of an error. ▲There are mathematical formulas, chemical formulas, tables, etc.▼ Or ▲There are mathematical formulas, chemical formulas, tables, etc.▼ However, when α is an irreducible polynomial on GF(2) as F(x), (F(x) =0). 2. The error correction method according to claim 1, wherein the first and second check word sequences are formed by first and second error correction encoders having different numbers of input words. 3 Words included in each of the PCM data series of multiple channels that do not completely match the words used to form the first check word, and words from the first error correction encoder. 3. The error correction method according to claim 2, wherein the first check word is supplied to a second error correction encoder to form a second check word sequence. 4. A patent claim in which the pointer set when error correction processing is performed based on the second check word is cleared for words whose errors are corrected in error correction processing based on the first check word. The error correction method described in item 1.