JPH037301B2 - - Google Patents

Info

Publication number
JPH037301B2
JPH037301B2 JP59129310A JP12931084A JPH037301B2 JP H037301 B2 JPH037301 B2 JP H037301B2 JP 59129310 A JP59129310 A JP 59129310A JP 12931084 A JP12931084 A JP 12931084A JP H037301 B2 JPH037301 B2 JP H037301B2
Authority
JP
Japan
Prior art keywords
signal
strobe
clock
phase
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59129310A
Other languages
English (en)
Japanese (ja)
Other versions
JPS619058A (ja
Inventor
Shigeyuki Ito
Yoshizumi Wataya
Koji Kaniwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59129310A priority Critical patent/JPS619058A/ja
Publication of JPS619058A publication Critical patent/JPS619058A/ja
Publication of JPH037301B2 publication Critical patent/JPH037301B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59129310A 1984-06-25 1984-06-25 デ−タ・ストロ−ブ装置 Granted JPS619058A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59129310A JPS619058A (ja) 1984-06-25 1984-06-25 デ−タ・ストロ−ブ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59129310A JPS619058A (ja) 1984-06-25 1984-06-25 デ−タ・ストロ−ブ装置

Publications (2)

Publication Number Publication Date
JPS619058A JPS619058A (ja) 1986-01-16
JPH037301B2 true JPH037301B2 (ko) 1991-02-01

Family

ID=15006404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59129310A Granted JPS619058A (ja) 1984-06-25 1984-06-25 デ−タ・ストロ−ブ装置

Country Status (1)

Country Link
JP (1) JPS619058A (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4345059A1 (de) * 1993-12-31 1995-07-06 Nec Electronics Europ Gmbh Verfahren und Vorrichtung zum Dekodieren eines diphase-kodierten digitalen Signals
EP2168230A2 (en) 2007-07-16 2010-03-31 Enphase Energy, Inc. Method and apparatus for anti-islanding of distributed power generation systems

Also Published As

Publication number Publication date
JPS619058A (ja) 1986-01-16

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