JPH0371658A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable even a semiconductor chip of large size to be mounted by a method wherein the peripheral part of the rear side of a cap and at least the lower ends of protrudent parts are sealed to the upside of a package base body and the base of a chip cavity with an adhesive agent. CONSTITUTION:To secure a sealing overlap width equivalent to the thickness d/2 of a side wall reduced for providing recesses 101 on the side of a cavity 2, plate-like protrusions 102 fitted into the recesses 101 on the side of the cavity 2 are provided to the underside of a cap 12. The cap 12 is made to cover a package base body 1 so as to fit the plate-like protrusions 102 into the recesses 21 on the side of the cavity 2, and the lower ends of the plate-like protrusions 102 whose thickness is half the thickness d of a side wall are welded to the residue (d/2) of the sealing overlap width with a low melting point glass 13. Therefore, a sealing overlap width equivalent to the thickness d of the side wall of a package can be secured through the sum of both the thicknesses of the protrusion 102 and the package base body 1. By this setup, a semiconductor chip of large size can be mounted without enlarging a package in external dimension.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the package structure of a semiconductor device, especially a semiconductor device sealed in a ceramic package, the present invention relates to an improvement in the package structure of a semiconductor device, particularly a semiconductor device enclosed in a ceramic package, which has the same external dimensions as the conventional one, and the dimensional range of the semiconductor chip to be mounted is the same as the conventional one. A semiconductor device in which a cap is sealed on a package base having a cavity in which a semiconductor chip is inserted and mounted, with the aim of providing a package structure that can be expanded to a larger size, and the cap is sealed on a package base opposite to the cavity of the package base. has a recess extending from the top surface to the bottom surface of the cavity on the side surfaces in at least two directions, and has a plate-shaped protrusion on the lower surface that fits into the recess on the side surface of the cavity to the bottom surface of the recess. A cap is placed on the cavity with the protrusion fitted into the recess on the side surface of the cavity, and the peripheral edge of the lower surface of the cap and at least the lower end surface of the protrusion are bonded to the upper surface of the package base and the upper surface of the package base with an adhesive. It has a structure that is sealed to the bottom surface of the chip cavity.

[Industrial application field]

The present invention relates to improvements in the package structure of semiconductor devices, particularly semiconductor devices sealed in ceramic packages.

In recent years, as LSIs and other devices have become more multi-functional and highly integrated, semiconductor chips have tended to become larger.Also, there has been a strong trend toward high-mix, low-volume production, and the size of semiconductor chips often changes each time. It has become to.

On the other hand, in order to avoid the expansion of information processing equipment, etc. in which semiconductor devices are installed, it is undesirable to increase the size of the packages that make up semiconductor devices, and each time the size of a semiconductor chip changes with a change in product type, it is necessary to It is undesirable to design and manufacture a package that is similar in size because it lengthens the development period of the semiconductor device.

Therefore, we have expanded the range of chip sizes that can be mounted, suppressed the increase in external dimensions of semiconductor devices due to the increase in the size of semiconductor chips, and created a package structure that does not prolong the development period due to package design steps when using large chips. is desired.

[Conventional technology]

FIG. 5 is a schematic diagram showing the main parts of a conventional semiconductor device mounted on a conventional flat glass (frit) sealed ceramic package with two-way leads; (a)
is a plan view, ~) is a cross-sectional view taken along the line A-A, and (C) is a cross-sectional view taken along the line B-B.

In the figure, 51 is a package base made of ceramic, 52 is a cavity, 53 is a depth stage, 54 is an internal wiring, 55 is a via, 56 is an external connection lead, 57 is a soldering part, 58 is a semiconductor chip, and 59 is a brazing material. , 60 is a bonding pad, 61 is a bonding wire, 62
63 indicates a ceramic cap, and 63 indicates a low melting point glass.

As shown in the cross-sectional view of the Gui bonding process shown in FIG. The chip stage 53 is pressed onto the chip stage 53 on which the bottom surface of the cavity 52 is plated with Au, etc., on which the bellet of brazing filler metal is placed, and is scrubbed by a distance α on both sides along the direction B-B shown by the arrow. It is firmly fixed to the top with a brazing material 59 interposed therebetween.

After wire bonding, as shown in the cross-sectional view of the sealing process shown in FIG. Ceramic cap with 6
2 is fused onto a frame-shaped region surrounding the cavity 52 of the package base 51 with a low-melting glass 63 by a frame-shaped flat surface surrounding the recess 64, thereby sealing the cap.

[Problem to be solved by the invention]

Therefore, as is clear from the description of FIG. 6(a), the width h2 of the cavity 52 in the B-B direction is 0.3 to
The value on both sides (twice) of the sum of the scrub distance α of about 0.5 mm, the thickness β of the tip of the Guicolet 65 of about 0.2 mm, and the gripping width T of the tip of about 0.2 mm. 1.
Since a margin of about 4 to 1.8 mm must be allowed for the width of the chip 57, the chip that can be mounted is correspondingly smaller.

If a semiconductor chip that is even slightly larger than this is used, a package base having a cavity of a newly optimized size and a cavity width of −2 as shown in FIG. 4(b) are used. However, it is necessary to design and manufacture a ceramic cap that is compatible with the package base, taking into account the sealing width d that ensures sealing strength.
As semiconductor devices have become larger, there has also been a problem in that the development period has become significantly longer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a package structure that has the same external dimensions as the conventional package structure and can expand the size range of the mounted semiconductor chip to a larger size than the conventional package structure.

[Means to solve the problem]

The above problem is a semiconductor device in which a cap is sealed on a package base having a cavity in which a semiconductor chip is inserted and mounted, the cap being sealed on at least two opposing sides of the cavity of the package base. A cap having a recess extending from the top surface to the bottom surface, and having a plate-shaped protrusion on the lower surface that fits into the recess on the side surface of the cavity up to the bottom surface of the recess on the package base; It is covered with the protrusion inserted,
In addition, the present invention provides a semiconductor device in which the peripheral edge of the lower surface of the cap and at least the lower end surface of the protrusion are sealed to the upper surface of the package base and the bottom surface of the chip cavity with an adhesive.

[For production]

FIGS. 1(a) to 1(b) are process cross-sectional views explaining the present invention in detail.

As shown in FIG. 1(a), the package base 1 according to the present invention has cavities necessary to obtain a required sealing strength on at least two opposing sides of a cavity 2 in which a semiconductor chip 18 can be mounted. By forming a recess 101 reaching from the top surface to the bottom surface of the cavity 2 and having a depth of, for example, 1/2, that is, d/2 of the thickness d of the side walls in the two directions of the chip stage 3, By expanding the width along both sides by a dimension of d/2 corresponding to 172 of the cavity side wall, the gripping allowance (γ) of the die collet 65 during die bonding, the width along the die collet 65
Taking into account the thickness of the tip (β) and the scrub width (α) as before, the width in the above direction of the semiconductor chip 18 that can be mounted in the cavity 2 is, for example, d/2X 2 with respect to the conventional width.
= Enables expansion by d.

(9 is a brazing material) As shown in FIG. A plate-shaped protrusion 102 is provided on the lower surface of the cap 12 so as to fit into the recess 101 on the side surface of the cavity 2 completely from the top surface to the bottom surface, and the cap 12 is placed on the package base 1. The plate-shaped protrusion 102 is fitted into the recess 21 on the side surface of the cavity 2 and covered, and the lower end surface of the plate-shaped protrusion 22 having a thickness of 172 times the thickness d of the side wall of the conventional package is connected to the base of the plate-shaped protrusion 102. The remaining portion (d/2) of the sealing margin on the bottom surface of the outer cap 12 is welded with the low melting point glass 13, and the sum of both secures the width of the sealing margin equivalent to the thickness d of the side wall of the conventional package, and increases the strength. , the reliability of sealing, such as airtightness, is maintained almost the same as before.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 2 is a schematic diagram of a package base in an embodiment of a two-way lead flat package according to the present invention.
) is a plan view, (b) is a sectional view taken along A-A, (C) is B-
3 is a schematic diagram of the cap in the same embodiment, (a) is a plan view, (b) is a sectional view taken along line A-A,
(C) is a cross-sectional view taken along the line B-B, FIG. 4 is a schematic diagram of a semiconductor device incorporated in the package of the same example, (a) is a plan view, and (b) is a cross-sectional view taken along the line A-A. , (C) is a sectional view taken along the line B-B.

Identical objects are indicated by the same reference numerals throughout the figures.

The package base of the two-way lead flat package according to the present invention is made of ceramic and has a glass (frit) seal structure, as shown in FIGS. 2(a), Φ), and (C). A cavity 2 is formed in the center of the package base 1 having equal external dimensions and thickness. This cavity 2 has the same depth as the conventional one, and has the same depth as the conventional one.
The two side faces in the direction B-
For example, the thickness d of the side wall in the same direction is 1/1/2 on the two side faces in the B direction.
A recess 101 according to the invention is formed having a depth t of 2/d, which is 2, and reaching from the top surface to the bottom surface of the cavity 2. Then, around the cavity 2 on the surface of the ceramic substrate 1, a low melting point glass 13 is coated to have the same width as the conventional one in the AA direction and 1/2 the conventional width in the B-B direction. An extended portion of the internal wiring 4 is led out to the upper surface of the ceramic substrate 1 via a via 5, and an external connection lead 6 is brazed to that portion. Note that 3 is a chip stage whose metallized layer is plated with Au, etc., and 7 is a soldered part.

As mentioned above, in this package base, in the B-B direction of the cavity 2, the depth t = 2/
A recess 101 of d is formed, and the width is expanded by the depth thereof, that is, d, compared to the conventional one. Therefore, as explained earlier with reference to FIG. 1(a), when considering the conventional scrub width, the thickness of the tip of the guicolet, and the chip gripping allowance for chip mounting, it is possible to mount a semiconductor chip with the same adhesion strength as before. The width in the same direction can be increased by d. Note that the direction AA is the same as the conventional one.

Further, the ceramic cap 12 used in the above-mentioned package according to the present invention has the same external dimensions as the conventional one, as shown in FIGS. 3(a), (b), and (C). A shallow recess 14 is formed to avoid bonding wire contact. The welded part i5 with the package base 1 formed around this recess 14 is connected to the cavity side wall in the A-A direction where the internal wiring 4 is disposed in the cavity 2 of the package base l, as in the conventional case. has a flat surface with a width d corresponding to the thickness of B-
In direction B, a shape having a thickness of d/2 and fitting into a region having a width of d/2 inside the fusion part 14 from the top to the bottom over the entire area of the recess 101 on the side surface of the cavity 2 of the package base 1. A plate-shaped protrusion 102 having a certain size is provided, and a low-melting glass 13 is applied to the welded portion 15 and the tip surface of the plate-shaped protrusion 102.

The part of this cap 12 where the low melting point glass 13 is applied and welded to the package base 1 is the same as the conventional one in the A-A direction, and is left outside the plate-shaped protrusion 102 in the B-B direction. Welded part 15 with a width of d/2
By combining the tips of the plate-like protrusions 102 having a thickness of d/2, a width d similar to the conventional one is secured, and the reliability of the sealing is improved compared to the conventional one.

(Refer to the explanation in FIG. 1(b)) The semiconductor device according to the present invention formed using the above-mentioned package base and ceramic cap is shown in FIG. 4(a), O),
It is schematically shown in (C).

In the figure, 1 is a ceramic base, 2 is a cavity, and 3 is a ceramic base.
is a chip stage, 4 is an internal lead, 5 is a via, 6 is an external connection lead, 7 is a soldering part, 8 is a semiconductor chip, 9
10 is a soldering material, 10 is a bonding pad, 11 is a bonding wire, 12 is a ceramic cap, 13 is a low melting point glass, 14 is a recess on the bottom surface of the cap, 15 is a welded part, 1
01 indicates a recess on the side surface of the cavity, and 102 indicates a protrusion on the plate.

As is clear from the above description, in the semiconductor device according to the present invention, when bonding semiconductor chips,
The width of the cavity in which the chip is mounted is increased by the amount that the package base on the side wall of the cavity is thinned. Therefore, it is possible to mount a split-type semiconductor chip in which the wall thickness of the cavity side wall of the package base is reduced without increasing the external dimensions of the package, and it is possible to expand the size range of semiconductor chips that can be mounted. .

In addition, in the structure according to the present invention, when the cap is placed on the package base, the plate-like protrusion of the cap and the recess on the side surface of the cavity serve as guides to maintain high alignment accuracy. High airtightness is maintained, and mechanical strength is also maintained high due to the engagement between the plate-like protrusion and the recess on the side surface of the cavity.

Although not shown, in the structure according to the present invention, if the side surface of the plate-shaped protrusion of the cap is also welded with low melting point glass in the same way as the lower end surface, the reliability of airtightness will be further improved.

〔Effect of the invention〕

As explained above, according to the semiconductor device according to the present invention, it is possible to mount a larger semiconductor chip than before without increasing the external dimensions of the package, so development of a new semiconductor device using a large chip is possible. The number of turns can be shortened, and equipment equipped with the semiconductor device can be downsized.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a detailed process of the present invention, and FIG. 2 is a schematic diagram of an embodiment of a package base according to the present invention.
a) is a plan view, (b) is a sectional view taken along the line A-A, and (C) is B
3 is a schematic diagram of an embodiment of the ceramic cap according to the present invention, (a) is a plan view, (b) is a sectional view taken along the line A-A, and (C) is a sectional view taken along the arrow B. 4 is a schematic diagram of a semiconductor device according to the present invention, in which (a) is a plan view, (b) is a sectional view taken along A-A, and (C) is a sectional view taken along B-B. 5 is a schematic diagram of a conventional semiconductor device, in which (a) is a plan view, (b) is a cross-sectional view taken along the line A-A, and (C) is a cross-sectional view taken along the line B-B. 1 is a process cross-sectional view of a conventional semiconductor device. In the figure, ■ is a ceramic substrate, 2 is a cavity, 3 is a chip stage, 4 is an internal lead, 5 is a via,
6 is the external connection lead, 7 is the brazing part,
8 is a semiconductor chip, 9 is a brazing material, 10 is a bonding pad, 11 is a bonding wire, 12 is a ceramic cap, 13 is a low melting point glass, 14
15 is a welded portion, 101 is a recess on the side surface of the cavity, and 102 is a protrusion on the plate. (α) Fibond ink” (α) Plan view (b) A-A arrow view 1tIT surface view/j-Diagram principle and explanation v3 Work process drawings IU! Top view of one embodiment of the foundation Fig. 2 (a) Plan view 3 (b) A-A cross-sectional view Figure 5 ((11) ) Undefined August 1; Schematic diagram of Kararogyu Doka Omote Nao Ichimi Ubai 1 No. 4
Figure 6: Process cross-section of conventional meridian surface installation

Claims (1)

[Scope of Claim] A semiconductor device in which a cap is sealed on a package base having a cavity in which a semiconductor chip is inserted and mounted, the cap being sealed on at least two opposing sides of the cavity of the package base. A cap having a recess extending from the top surface to the bottom surface of the cavity, and having a plate-shaped protrusion on the lower surface that fits into the recess on the side surface of the cavity up to the bottom surface of the recess is mounted on the package base. The cap is covered with the protrusion fitted into the cap, and the peripheral edge of the lower surface of the cap and at least the lower end surface of the protrusion are sealed to the upper surface of the package base and the bottom surface of the chip cavity with an adhesive. A semiconductor device characterized by: