JPH0370398B2 - - Google Patents
Info
- Publication number
- JPH0370398B2 JPH0370398B2 JP4206087A JP4206087A JPH0370398B2 JP H0370398 B2 JPH0370398 B2 JP H0370398B2 JP 4206087 A JP4206087 A JP 4206087A JP 4206087 A JP4206087 A JP 4206087A JP H0370398 B2 JPH0370398 B2 JP H0370398B2
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- hole
- multilayer printed
- blind
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 16
- 238000005553 drilling Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 1
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、各種電子機器の電子部品を実装する
ために使用される多層プリント配線板に関し、特
にブラインドスルーホール（非貫通孔）を有する
多層プリント配線板に関するものである。Detailed Description of the Invention (Industrial Application Field) The present invention relates to a multilayer printed wiring board used for mounting electronic components of various electronic devices, and particularly to a multilayer printed wiring board having blind through holes. It relates to printed wiring boards.
（従来の技術）
従来の多層プリント配線板にあつては、部品挿
入用の孔は勿論、経由孔（バイア・ホール）にあ
つても貫通孔の形で設けられており、めつき等に
よりこれら孔内壁に導体層を形成するのが一般的
である。(Prior art) In conventional multilayer printed wiring boards, not only holes for inserting components but also via holes are provided in the form of through holes, and these are formed by plating etc. It is common to form a conductive layer on the inner wall of the hole.
一方、近年の電子機器の高度化に伴い、多層プ
リント配線板においても、よりいつそうの高多層
高密度化への要求が高まつてきている。 On the other hand, as electronic devices have become more sophisticated in recent years, there has been an increasing demand for higher multilayer density in multilayer printed wiring boards.
バイア・ホールを貫通孔の形で設ける、従来の
多層プリント配線板にあつては、このバイア・ホ
ールによつて、高密度化のための配線密度が著し
く阻害されるという問題が生じている。そのた
め、バイア・ホールを小径化することによつて、
配線密度を確保し対応しているが、高多層化に伴
つて板厚も増加しており、これにより板厚／孔径
の比（アスペクト比）が増加してしまい、多層プ
リント配線板の製造性が著しく阻害されている。 In conventional multilayer printed wiring boards in which via holes are provided in the form of through holes, a problem arises in that the via holes significantly impede wiring density. Therefore, by reducing the diameter of the via hole,
Although the wiring density has been ensured, the board thickness has also increased as the number of layers increases, and this increases the ratio of board thickness/hole diameter (aspect ratio), making it difficult to manufacture multilayer printed wiring boards. is severely inhibited.
そこで、従来、一つの試みとしてブラインドス
ルーホールによつて、配線の密度を向上させた多
層プリント配線板が知られている。この製造方法
の一つとして、ドリルによつて多層板に非貫通孔
を片面ずつ形成し、めつき等により孔内壁に導体
層を形成する方法がある。 Therefore, as an attempt, a multilayer printed wiring board has been known in which the wiring density is improved by using blind through holes. One of the manufacturing methods is to form non-through holes on each side of the multilayer board using a drill, and to form a conductor layer on the inner wall of the hole by plating or the like.
（発明が解決しようとする問題点）
しかしながら、ドリルによる穴明けでブライン
ドスルーホールを形成する場合、当然のことなが
ら多層板の厚さ方向に対してドリルの深さを制御
する必要があるが、多層板の積層工程において、
多層板の板厚の変動は避けられず、また穴明け作
業の方法によつては、第５図に示すブラインドス
ルーホール１２の底部１４と、次の層の導体回路
１３との距離ｈが変動するため、導体回路の電気
的特性が大きく変化化するという欠点があつた。(Problems to be Solved by the Invention) However, when forming blind through holes by drilling, it is necessary to control the depth of the drill in the thickness direction of the multilayer board. In the process of laminating multilayer boards,
Variation in the thickness of a multilayer board is unavoidable, and depending on the method of drilling, the distance h between the bottom 14 of the blind through hole 12 and the conductor circuit 13 of the next layer shown in FIG. 5 may vary. Therefore, there was a drawback that the electrical characteristics of the conductor circuit changed greatly.
（問題点を解決するための手段）
以上の問題点を解決するために、本発明が採つ
た手段を、実施例に対応する第１図及び第２図を
参照して説明する。(Means for Solving the Problems) In order to solve the above problems, the means taken by the present invention will be explained with reference to FIGS. 1 and 2, which correspond to embodiments.
第１図は本発明に係る多層プリント配線板の一
部を切り欠いた部分斜視図であり、第２図はその
部分拡大縦断面図である。第１図及び第２図に示
すように、本発明の多層プリント配線板１は、内
層基板等の積層後、ドリルによる穴明けで設けら
れた非貫通孔の内壁に、めつき等により導体層を
形成して設けられたブラインドスルーホール２を
有し、前記ブラインドスルーホール２に最も近い
内層に、導体回路３が形成されたものであつて、
前記内層導体回路３の、前記ブラインドスルーホ
ール２の底部４の近傍に対応する部分６を、前記
底部４の直下部分５を迂回して形成したことを特
徴とする多層プリント配線板１である。 FIG. 1 is a partially cutaway perspective view of a multilayer printed wiring board according to the present invention, and FIG. 2 is a partially enlarged vertical sectional view thereof. As shown in FIGS. 1 and 2, the multilayer printed wiring board 1 of the present invention has a conductive layer formed by plating or the like on the inner wall of a non-through hole formed by drilling after laminating inner layer substrates, etc. A conductor circuit 3 is formed in the inner layer closest to the blind through hole 2, and a conductor circuit 3 is formed in the inner layer closest to the blind through hole 2.
This multilayer printed wiring board 1 is characterized in that a portion 6 of the inner layer conductor circuit 3 corresponding to the vicinity of the bottom 4 of the blind through hole 2 is formed by bypassing a portion 5 directly below the bottom 4.
（発明の作用）
本発明が以上のような手段を採ることによつ
て、以下のような作用がある。(Actions of the Invention) By adopting the above measures, the present invention has the following effects.
従来の多層プリント配線板１１にあつては、多
層板の積層工程における板厚の変動や、穴明け工
程におけるドリルのストロークの下限の変動等に
よる、ブラインドスルーホール１２の底部１４
と、次の層の導体回路１３との距離ｈの変動は避
けられないことは前述した通りである。 In the case of the conventional multilayer printed wiring board 11, the bottom 14 of the blind through hole 12 is caused by variations in board thickness during the multilayer board lamination process, variations in the lower limit of the drill stroke during the drilling process, etc.
As described above, variations in the distance h between the conductor circuit 13 of the next layer and the conductor circuit 13 of the next layer are unavoidable.
しかしながら、本発明によれば、内層導体回路
３のブラインドスルーホール２の底部４の近傍に
対応する部分６を、底部４の直下部分５を迂回し
て形成したことにより、ブラインドスルーホール
２の底部４と、次の層との距離ｈが変動しても、
ブラインドスルーホール２と、次の層の導体回路
３との距離ｉは一定の長さ以上に保たれる。 However, according to the present invention, the portion 6 corresponding to the vicinity of the bottom portion 4 of the blind through hole 2 of the inner layer conductor circuit 3 is formed by bypassing the portion 5 directly below the bottom portion 4. Even if the distance h between 4 and the next layer changes,
The distance i between the blind through hole 2 and the conductor circuit 3 in the next layer is maintained at a certain length or more.
次に、本発明を各実施例に従つて詳細に説明す
る。 Next, the present invention will be explained in detail according to each embodiment.
（実施例）
実施例 １
第１図及び第２図に示すように、ブラインドス
ルーホール２に最も近い内層に、導体回路３であ
るベタパターンが形成された多層プリント配線板
１において、ベタパターンのブラインドスルーホ
ール２の底部４の近傍に対応する部分６にクリア
ランスホールを形成して本発明に係る多層プリン
ト配線板１を得る。(Example) Example 1 As shown in FIGS. 1 and 2, in a multilayer printed wiring board 1 in which a solid pattern, which is a conductor circuit 3, is formed on the inner layer closest to the blind through hole 2, the solid pattern is A clearance hole is formed in a portion 6 corresponding to the vicinity of the bottom 4 of the blind through hole 2 to obtain the multilayer printed wiring board 1 according to the present invention.
実施例 ２
第３図に示すように、ブラインドスルーホール
２に最も近い内層に、導体回路３であるラインパ
ターンが形成された多層プリント配線板１におい
て、ラインパターンのブラインドスルーホール２
の底部４の近傍に対応する部分６を、底部の直下
部分５を迂回して形成して本発明に係る多層プリ
ント配線板１を得る。Example 2 As shown in FIG. 3, in a multilayer printed wiring board 1 in which a line pattern, which is a conductor circuit 3, is formed in the inner layer closest to the blind through hole 2, the blind through hole 2 with the line pattern
The multilayer printed wiring board 1 according to the present invention is obtained by forming a portion 6 corresponding to the vicinity of the bottom portion 4 of the substrate, bypassing the portion 5 immediately below the bottom portion.
（発明の効果）
以上詳述した通り、本発明に係る多層プリント
配線板にあつては、ブラインドスルーホールに最
も近い内層の導体回路の、前記ブラインドスルー
ホールの底部の近傍に対応する部分を、前記底部
の直下部分を迂回して形成したことにその特徴が
あり、これにより、ブラインドスルーホールの底
部と、導体回路との間に一定以上の距離が保たれ
るので、電気的特性の変動が少ない多層プリント
配線板を提供することができる。また、以上のよ
うな理由から、多層板の板厚の変動や、ドリルの
ストロークの下限の変動等の許容範囲を従来に比
べ大きくとることができ、製造性を著しく向上さ
せるという効果をも奏する。(Effects of the Invention) As detailed above, in the multilayer printed wiring board according to the present invention, the portion of the conductive circuit in the inner layer closest to the blind through hole, which corresponds to the vicinity of the bottom of the blind through hole, Its characteristic lies in the fact that it is formed by bypassing the part directly below the bottom, and as a result, a distance above a certain level is maintained between the bottom of the blind through hole and the conductor circuit, thereby preventing fluctuations in electrical characteristics. It is possible to provide a multilayer printed wiring board with a reduced number of layers. In addition, for the reasons mentioned above, the tolerance range for variations in the thickness of the multilayer board and the lower limit of the drill stroke can be made larger than in the past, which has the effect of significantly improving manufacturability. .
第１図は本発明に係る多層プリント配線板を示
す一部を切り欠いた部分斜視図、第２図は第１図
に示す多層プリント配線板の部分拡大縦断面図、
第３図は本発明に係る別の多層プリント配線板を
示す一部を切り欠いた部分斜視図、第４図は従来
の多層プリント配線板を示す一部を切り欠いた部
分斜視図、第５図は第４図に示す多層プリント配
線板の部分拡大縦断面図である。
符号の説明 １…多層プリント配線板、２…ブ
ラインドスルーホール、３…内層導体回路、４…
底部、５…直下部分、６…底部の近傍に対応する
部分。
FIG. 1 is a partially cutaway partial perspective view showing a multilayer printed wiring board according to the present invention, FIG. 2 is a partially enlarged vertical sectional view of the multilayer printed wiring board shown in FIG. 1,
FIG. 3 is a partially cutaway perspective view showing another multilayer printed wiring board according to the present invention, FIG. 4 is a partially cutaway perspective view showing a conventional multilayer printed wiring board, and FIG. The figure is a partially enlarged vertical cross-sectional view of the multilayer printed wiring board shown in FIG. 4. Explanation of symbols 1...Multilayer printed wiring board, 2...Blind through hole, 3...Inner layer conductor circuit, 4...
bottom, 5... part directly below, 6... part corresponding to the vicinity of the bottom.
Claims (1)
体回路が形成された多層プリント配線板におい
て、前記内層導体回路の、前記ブラインドスルー
ホールの底部の近傍に対応する部分を、前記底部
の直下部分を迂回して形成したことを特徴とする
多層プリント配線板。1. In a multilayer printed wiring board in which a conductor circuit is formed in the inner layer closest to the blind through hole, a portion of the inner layer conductor circuit corresponding to the vicinity of the bottom of the blind through hole is bypassed by a portion directly below the bottom. A multilayer printed wiring board characterized by forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4206087A JPS63208298A (en) | 1987-02-24 | 1987-02-24 | Multilayer printed interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4206087A JPS63208298A (en) | 1987-02-24 | 1987-02-24 | Multilayer printed interconnection board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63208298A JPS63208298A (en) | 1988-08-29 |
| JPH0370398B2 true JPH0370398B2 (en) | 1991-11-07 |
Family
ID=12625557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4206087A Granted JPS63208298A (en) | 1987-02-24 | 1987-02-24 | Multilayer printed interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63208298A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200611612A (en) | 2004-09-29 | 2006-04-01 | Unimicron Technology Corp | Process of electrically interconnect structure |
-
1987
- 1987-02-24 JP JP4206087A patent/JPS63208298A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63208298A (en) | 1988-08-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |