JPH0369210A - Level shifter circuit - Google Patents

Abstract

PURPOSE:To make design easy by using the gate of a first inverter as an input terminal, connecting the output to the gate of a second inverter and one open/ close terminal of a switch, on the other hand, connecting the other open/close terminal to a specified terminal, using the output of the second inverter and the control terminal of the switch as output ends, and specifying the amplitude to be a specified value. CONSTITUTION:When a signal at VSS level is inputted to an input terminal IN, a P1 is turned ON and an N1 is turned OFF. Thus, since a P2 equivalent with a diode is in a regular direction to a connecting point A, the connecting point A is close to a VDD level. Accordingly, an N2 is turned ON and since a P3 is not completely turned to an OFF state, however, an output terminal OUT does not come to the complete VSS level. Therefore, since the output is lowered, a P4 is turned to an ON state and the connecting point A comes to a VCC level. Thus, the P3 is completely turned OFF, and the output comes to the complete VSS level. At such a time, since the level of the connecting point A is higher than the VDD and an inverse bias state is obtained by inserting the P2 equivalent with the diode, a current does not flow from the connecting point A to the VDD side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level shifter circuit, and particularly to a level shifter circuit using 0MOS transistors.

[Conventional technology]

Conventionally, such level shifter circuits are P-channel type MOS
It is composed of transistors, inverters made of N-channel MOS transistors, and the like.

FIG. 5 is a level shifter circuit diagram showing an example of such a conventional device.

As shown in FIG. 5, the conventional level shifter is mainly used for analog switches and the like, and the analog switches are controlled by a control signal having an amplitude smaller than the amplitude of the signal passing between the switches. In Figure 5,
One inverter 1 connected between VDD vss and two P-channel MOS transistors P7. P8 and two N-channel type MOS) transistors N7. It is composed of N8. That is, MOS) transistor P7
and N7 are connected to each other, the source side of P7 is connected to VCC, and the source side of N7 is connected to Vss. Furthermore, the drain sides of MOS transistors P8 and N8 are also connected, and the source side of P8 is connected to V. 0 and N
Connect the source sides of 7 to VSS, respectively. On the other hand, M.O.
S) MOS transistor P7 gate
and the drain side of N8, and the gate of P8 is connected to the drain side of P7 and N7, and the inverter 1 (VDI
)<VCC), connect the input terminal IN to the gate of N7 and the input of inverter 1, and connect the output of P8 and N8.
Connect the drain side of the terminal to the output terminal OUT.

The operation of such a level shifter circuit expands the logic amplitude of the power supply VDDVSS so that it becomes the amplitude of VCC-Vss (VDD<VCC).

[Problem to be solved by the invention]

In the conventional level shifter circuit described above, the channel widths of N7 and N8 must be made sufficiently larger than the channel widths of MOS transistors P7 and P8.

For example, when a rising signal from the power supply V33 to VD is input to the input, N7 turns on and the gate potential of P8 becomes low, so that P8 starts to turn ON. At the same time, since N8 turns OFF' (state of ■), P7
Since the gate potential of becomes high and shifts to the OFF state,
The gate potential of P8 becomes even lower and shifts to the ON side,
Therefore, the output finally becomes VCC level. At this time, if the value of the channel width W of P7 is large, P7 is still in the ON state in the state of ■, so the drain side of N7 is V
There is a problem that it is difficult to reach the B8 level and it takes time to output the VCC signal from the output.

On the other hand, when a falling signal from VDD to VSS is input, N8 turns on and the gate potential of P7 becomes low, so that P7 becomes 0. Since NL begins and N7 turns OFF (state ■), the gate potential of P8 becomes high and shifts to the OFF state, so the gate potential of P7 becomes even lower and shifts to the ON side, so the final output becomes v, level 8. At this time, if the channel width of P8 is large, there is a problem that it takes time for the output to reach the VSS level because P8 is in the ON state in the state (2).

From the above, it is necessary to make the channel widths of N7 and N8 sufficiently larger than those of P7 and P8, which increases the area of the device and makes it difficult to balance the channel widths of N7 and N8 in terms of design. There are drawbacks.

An object of the present invention is to solve such problems and provide a level shifter circuit with small elements and easy design.

[Means to solve the problem]

The level shifter circuit of the present invention includes a switch that has a pair of opening/closing terminals and a control terminal, and the opening/closing terminal opens and closes when a signal of a predetermined level is input to the control terminal, and an input element that allows current to flow in only one direction. P channel type MOS
A first inverter is connected to the drain side of the transistor, and its output is connected to the drain side of the N-channel MOS transistor, and the connection point is the output, and the input signal is connected to the first inverter connected between V and -VSS. Invert and output between v cc and v ss or VDD and VD
a second inverter connected between D1 and D1, the gate of the first inverter is an input terminal, and the output thereof is connected to the gate of the second inverter and one opening/closing terminal of the switch. , the other opening/closing terminal V.

. or connect to vo and use the output of the second inverter and the control terminal of the switch as output terminals, and
The DD-VDD amplitude is expressed as the Vcc Vss amplitude (V D
D < V cc ) or VDI) - vl+! It is configured to make one swing @(Vss>Vxm).

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a level shifter circuit for explaining a first embodiment of the present invention.

As shown in FIG. 1, this embodiment has a pair of opening/closing terminals and a control terminal, and when an L (or H) signal is input to this control terminal, the previous opening/closing terminal opens (or closes). It has a switch 2. Further, in this embodiment, the input signal supplied from the input terminal IN is inverted and outputted, and the power supply Vf1. )-V and s, and the input signal from this first inverter 1 is inverted and outputted, and the power supply VCC-V
It has a second inverter 3 connected between SS. Moreover, the output of the first inverter 1 is connected to the input of the second inverter 3 and one switching terminal of the switch 2, and the other switching terminal is connected to the power supply vo. The output terminal of the second inverter 3 and the control terminal of the switch 2 are connected to the output terminal OUT.

FIG. 2 is a circuit diagram embodying the block configuration shown in FIG. 1.

As shown in FIG. 2, the first inverter 1. switch 2
P1 to P4 constituting the second inverter 3 are P-channel MOS transistors, N1 and N2 are N-channel MOS transistors, and point A is P2. P4. Point B represents the connection point between the drain side of Nl and the gate of P3°N2, and point B represents the connection point between Pl and P2 in the inverter 1 on the drain side. When a signal of V level is input to the input terminal IN of such a level shifter circuit, Pl turns OFF.
', Nl is turned ON, so the connection point A becomes the VS9 level. Therefore, P3 is ON, N2 is OFF, and the output terminal OUT is V cc (V DD < V cc )
become the level. At this time, P4 is turned OFF.

Next, when a VSS level signal is input to the input terminal IN, Pl is turned on and Nl is turned off. However, since P2, which is equivalent to a diode, is in the forward direction from connection point B to connection point A, connection point A becomes close to the VDD level. That is, the potential is lowered by the potential obtained by subtracting the V of P2, which is equivalent to a diode, from v and D. Therefore, N2 is turned ON, but since P3 is not completely OFF, the output terminal O
UT will not be at perfect VSS level. Therefore, since the output becomes low, P4 becomes ON state, and connection point A
is V. Become C level. As a result, P3 is completely OF
F, the output will be at full VSS level.

At this time, since connection point A is at a higher level than vDn, if the inverter is made up of only PI and Nl, current will flow from connection point A to the VDD side, but if P2, which is equivalent to a diode, is inserted. Since it is in a reverse bias state, no current flows from the connection point A to the vgx side.

FIG. 3 is a block diagram of a level shifter circuit for explaining a second embodiment of the present invention.

As shown in FIG. 3, in comparison with the first embodiment (FIG. 1) described above, the power supply to the switch 2 is reduced in this embodiment. 0 to VEX, and the power supply to the inverter 3 is V. . -VSS to VDD-Vlm. The same applies to inverter 1.

This embodiment has a pair of opening/closing terminals and a control terminal, and when an H (or L) signal is input to this control terminal,
A switch 2 that opens (or closes) the opening/closing terminal, and the input of an element through which current flows only in one direction is connected to the drain side of the N-channel MOS transistor, and the output is connected to the drain side of the P-channel MOS transistor. At the same time, it has a first inverter 1 which outputs the connection point and is connected between VDD and V38, and a second inverter 3 which inverts the input signal and outputs it and is connected between VDD and vgx. , the gate of the first inverter 1 is set as an input terminal IN, its output is connected to the gate of the second inverter 3 and one switching terminal of the switch, and the other switching terminal is connected to vgx, The output of switch 3 and the control terminal of switch 2 are connected to the output terminal OUT.

FIG. 4 is a circuit diagram embodying the block configuration shown in FIG. 3.

As shown in FIG. 4, in this embodiment, P5 and P6, which constitute inverter 1, switch 2, and inverter 3, are P-channel type MOS transistors, N3 to N6 are N-channel type MOS transistors, and point 0 is P5. N3. Represents the connection point between the drain side of N6 and the gate and gate of P6°N5, and D
The dot represents the connection point of N3 and N4 on the drain side.

When a signal at the V9S level is input to the input terminal IN of such a level shifter circuit, P5 is turned on and N4 is turned off, so that the connection point C becomes the VDD level. Therefore, P
6 is OF'F and N5 is ON, so the output is V gg
(V ss > V wz ) level. At this time, N6 is OFF.

Next, when a van level signal is input to the input terminal IN, P5 turns OFF and N4 turns ON, and since N3, which is equivalent to a diode, is in the forward direction from the connection point C to the connection point, the connection point C is close to VB8 level. That is, the value is 72 times larger than N2, which is equivalent to a diode for VSS. Therefore, P6 turns ON, but N5 is completely 0F.
Since there is no FL, the output is not accurate ■. Although it does not reach the D level, the output becomes low, so N6 is turned on, and the connection point C becomes the VO level. As a result, N5 is completely turned off, so that the output terminal OUT becomes at the complete VDD level.

At this time, the connection point C is ■8. Because it is at a lower level, P5. If the inverter consists of only N4, VS
Current flows from S to connection point C, but since a reverse bias is created by inserting N3, which is equivalent to a diode, no current flows from V9S to connection point C.

In the above-described embodiments, a MOS transistor was used as a switch and a diode, but any element fulfilling the respective roles may be configured in the same manner.

〔Effect of the invention〕

As explained above, the level shifter circuit of the present invention is
There is no need to make the channel width of each P-channel type and N-channel type MOS) transistor particularly large, and the channel width ratio can be designed simply by considering the ratio of each inverter, so the device size becomes smaller and design is easier. It has the effect of becoming

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a level shifter circuit for explaining the Q-Q embodiment of the present invention, FIG. 2 is a circuit diagram embodying the block configuration shown in FIG. 1, and FIG. A block configuration diagram of a level shifter circuit for explaining the second embodiment, FIG. 4 is a circuit diagram embodying the block configuration shown in FIG. 3, and FIG. 5 is a level shifter circuit diagram showing a conventional example. be. 1.3...Inverter, 2...Switch, P1-P6...P-type MOS transistor,
N1-N6-----N type MO3) transistor, VD
D# VOCr Vss rv21... Power supply terminal. Porridge 1 figure

Claims (1)

[Claims] A switch has a pair of opening/closing terminals and a control terminal, and the opening/closing terminal opens and closes when a signal of a predetermined level is input to the control terminal, and the input of an element through which current flows only in one direction is connected to the drain of a P-channel MOS transistor. and connects its output to the drain side of the N-channel MOS transistor, and connects the connection point to the first inverter connected between V_D_D and V_S_S, and inverts the input signal and outputs the output. issue V_C_C-V
a second inverter connected between _S_S or between V_D_D and V_Z_Z, the gate of the first inverter is an input terminal, and the output thereof is an opening/closing terminal of the gate of the second inverter and one of the switches. and the other switching terminal is connected to V_C_C or V_Z_Z, and the output of the second inverter and the control terminal of the switch are used as output terminals, and the V_D
_D-V_S_S amplitude is the V_C_C-V_S_S amplitude (V_D_D<V_C_C) or V_D_D-V
A level shifter circuit characterized in that the amplitude is _Z_Z (V_S_S>V_Z_Z).