JPH0983336A - Input buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To freely set the function of an input buffer and also to change this function in a short time by switching the input of the external terminal of a semiconductor integrated circuit. SOLUTION: An inverting input buffer circuit 3 inverts the signal supplied from an input terminal 8 an outputs it to an output terminal 11. An N type FET transistor TR 1 is connected to a power terminal 10 of a resistor 2 and opened there by the control signal of a control terminal 7. An inverter 6 inverts the control signal of a control terminal 9. Then a NOR circuit 4 performs the ON/OFF control of an N type FET TR 5 by the output of both circuit 3 and inverter 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer circuit, and more particularly to an input buffer circuit of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, an input buffer function of a semiconductor integrated circuit is designed and manufactured to have any one kind of function.
For this reason, it is impossible to change the input buffer function of the semiconductor integrated circuit on the way due to the requirement on the interface, and in the case of changing it, it is necessary to newly design the circuit and manufacture it again.

FIG. 3 is a block diagram showing an input buffer circuit of a conventional semiconductor integrated circuit.

FIG. 3A shows an inverting input buffer circuit, FIG. 3B shows an inverting input buffer circuit with a pull-up resistor, and FIG. 3C shows a Schmitt trigger type input buffer circuit.

The functions and circuits of the input buffers shown in FIGS. 3A to 3C are fixed, and each is incorporated in a semiconductor integrated circuit to perform the operation of that function.

Referring to FIG. 3A, when the input terminal 8 of the inverting input buffer circuit 3 is at a high level, the P-type field effect transistor 13 is in the OFF state and the N-type field effect transistor 14 is in the ON state. The ground potential connected to the source of the N-type field effect transistor 14 is output to the output terminal 11 and becomes the low level.

When the input terminal 8 is at low level, P
Since the N-type field effect transistor 13 is turned on and the N-type field effect transistor 14 is turned off, the output terminal 1
1, the voltage of the power supply terminal 10 connected to the drain of the P-type field effect transistor 13 is output to high (high).
h) Level.

In the circuit of FIG. 3 (b), the input terminal 8 of the inverting type input buffer circuit 3 is connected to the power supply terminal 1 with a pull-up resistor 12.
The output terminal 1 is connected to 0, and the N-type field effect transistor 14 is turned on even when the input terminal is open.
A low level is always output to 1.

In the circuit of FIG. 3C, an inverter 16 is connected to the output terminal 11 of the inverting type input buffer circuit 3, the output of the inverter 16 is connected to the gate of the N-type field effect transistor 15, and the source and drain thereof. Are respectively connected to the ground point and the output terminal 11.

Referring to FIG. 3C, when the input terminal 8 of the inverting input buffer circuit 3 is at high level, the P-type field effect transistor 13 is in the OFF state and the N-type field effect transistor 14 is in the ON state. The ground potential connected to the source of the N-type field effect transistor 14 is output to the output terminal 11 and becomes low level.

The low level output at the output terminal 11 is inverted by the inverter 16 and becomes a high level to try to shift the N-type field effect transistor 15 to the ON state, but the drain of the N-type field effect transistor 15 is at the ground potential. Therefore, it is turned off, and the output terminal 11 maintains the low level.

When the input terminal 8 is at low level, P
Since the N-type field effect transistor 13 is turned on and the N-type field effect transistor 14 is turned off, the output terminal 1
The voltage of the power supply terminal 10 connected to the drain of the P-type field effect transistor 13 is output to 1 and becomes high level.

The high level output at the output terminal 11 is inverted by the inverter 16 and becomes a low level to turn off the N-type field effect transistor 15, so that the output terminal 1
1 keeps high level.

Since the functions of all the input buffer circuits described above are fixed, the semiconductor integrated circuit must be used according to the fixed functions, and the function of the input buffer circuit cannot be changed.

A "semiconductor integrated circuit" described in Japanese Patent Laid-Open No. 4-319816 is known as an example of a circuit for changing the function of the input buffer circuit without remanufacturing the semiconductor integrated circuit.

The circuit described in this publication is a Schmitt trigger type input buffer circuit having a hysteresis characteristic in the output level corresponding to the input level of the inverting type input buffer circuit by rewriting the contents of the read only memory (ROM). You can change it freely.

[0017]

In the conventional input buffer circuit described above, the semiconductor integrated circuit itself must be redesigned and manufactured when the input buffer function is changed on the way, so that the economical efficiency of time and cost is impaired. have.

Further, there is a drawback that a ROM and peripheral circuits are required to change the input buffer function and a step of rewriting the contents of the ROM is required.

An object of the present invention is to provide an input buffer circuit in which the function of the input buffer can be freely set by switching the input of the external terminal of the semiconductor integrated circuit and the function can be easily changed in a short time.

[0020]

An input buffer circuit according to the present invention comprises a first control terminal, a first control terminal to which a gate is connected, a drain to a power supply terminal, and a source to one end of a resistor. An N-type field effect transistor, a P-type field effect transistor having a drain connected to the power supply terminal, and a second N-type field effect transistor having a source connected to a ground point, and the gates of these transistors are commonly connected to each other to form an input terminal And an inverting input buffer circuit connected to the other end of the resistor and connected to the source of the P-type field effect transistor and the drain of the second N-type field effect transistor as an output terminal, and a second control terminal An inverter for inverting the control signal, and a NOR circuit to which the inverter output and the output of the inverting input buffer circuit are input, Drain gate connected to the output of the NOR circuit is characterized in that the source connected to said output terminal is composed of a third N-type field effect transistor connected to said ground point of.

Further, a first control terminal, a first N-type field effect transistor having a gate connected to the control terminal, a drain connected to a power supply terminal and a source connected to one end of a resistor, and a drain connected to the power supply. A P-type field effect transistor connected to a terminal and a second N-type field effect transistor having a source connected to ground, the gates of these transistors being commonly coupled and connected to the input terminal and the other end of the resistor and An inverting type input buffer circuit which connects the source of the P-type field effect transistor and the drain of the second N-type field effect transistor and uses it as an output terminal;
An inverter that inverts the control signal of the second control terminal, a NOR circuit to which the inverter output and the output of the inverting input buffer circuit are input, a gate connected to the output of this NOR circuit, and a drain whose output terminal is the output terminal. A third N-type field effect transistor having a source connected to the ground point and a read-only memory for outputting a control signal to the first and second control terminals. There is.

The first and second N-type field effect transistors are P-type field effect transistors, and the P-type field effect transistor is an N-type field effect transistor.

[0023]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the input buffer circuit of the present invention.

The present embodiment shown in FIG. 1 has a control terminal 7 for inputting a control signal, and an N terminal having a gate connected to the control terminal 7, a drain connected to a power supply terminal 10 and a source connected to one end of a resistor 2. -Type field-effect transistor 1 and P-type field-effect transistor 1 whose drain is connected to power supply terminal 10
3 and an N-type field effect transistor 14 whose source is connected to the ground, and the gates of these transistors are commonly connected and connected to the input terminal 8 and the other end of the resistor 2 and the source and N of the P-type field effect transistor 13 are connected. -Type field effect transistor 14 connected to the drain and output terminal 1
1, the inverting input buffer circuit 3, the inverter 6 that inverts the control signal at the control terminal 9, and the NO to which the output of the inverter 6 and the output of the inverting input buffer circuit 3 are input.
It is composed of an R circuit 4 and an N-type field effect transistor 5 having a gate connected to the output of the NOR circuit 4, a drain connected to the output terminal 11, and a source connected to the ground point.

In FIG. 1, components corresponding to those shown in FIG. 3 are designated by the same reference numerals or symbols, and their description will be omitted.

FIG. 2 is a diagram showing hysteresis characteristics of the Schmitt trigger type input buffer circuit.

Next, the operation of the present embodiment will be described in more detail with reference to FIGS.

When the control signals at the control terminals 7 and 9 are at low level, the N-type field effect transistor 1 is OF
Since the output of the inverter 6 becomes high level and the output of the NOR circuit 4 becomes low level, the N-type field effect transistor 5 is turned off. Therefore, the present embodiment operates as the conventional inverting type input buffer circuit shown in FIG.

Next, when the control signal at the control terminal 7 is at the low level and the control signal at the control terminal 9 is at the high level, the N-type field effect transistor 1 is in the OFF state, but the output of the inverter 6 is at the low level, and thus NOR. The output of the circuit 4 is determined by the output of the inverting input buffer circuit 3, and the N-type field effect transistor 5 is controlled to either the OFF state or the ON state.

That is, in the operation of the NOR circuit 4, since the output of the inverter 6 is low level as shown in the truth table of Table 1, when the output terminal 11 is low level, the output of the NOR circuit 4 becomes high level and the output terminal 11 Is high level, the output of the NOR circuit 4 becomes low level. This is NO
It is equivalent to a circuit in which the R circuit 4 is replaced with an inverter.

[0032]

When the input terminal 8 of the inverting input buffer circuit 3 is at low level, the output terminal 11 is at high level, the output of the NOR circuit 4 is at low level, and the N-type field effect transistor 5 is turned off. On the other hand, when the input of the inverting type input buffer circuit 3 changes to high level, the output terminal 11 becomes low level, the output of the NOR circuit 4 becomes high level, and the N-type field effect transistor 5 becomes O.
The N state is set.

As a result, the ratio of the drivability of the P-type field effect transistor 13 and the N-type field effect transistor 14 held in the inverting type input buffer circuit 3 collapses, and the threshold level of the inverting type input buffer circuit 3 decreases. This means that there are two threshold levels at the input of the inverting type input buffer circuit 3, and it operates as the conventional Schmitt trigger type input buffer circuit shown in FIG. 3C having the hysteresis characteristic shown in FIG. .

Next, when the control signal at the control terminal 7 is at a high level and the control signal at the control terminal 9 is at a low level, the N-type field effect transistor 1 is in the ON state, and the output of the inverter 6 is at the high level, and the NOR circuit. Since the output of 4 becomes low level, the N-type field effect transistor 5
In the FF state, the present embodiment operates as the conventional inverting input buffer circuit with pull-up resistor shown in FIG.

Next, when the control signal of the control terminal 7 and the control signal of the control terminal 9 are at the high level, the N-type field effect transistor 1 is in the ON state, but the output of the inverter 6 is at the low level, and therefore the NOR circuit. The output of 4 is determined by the state of the output of the inverting input buffer circuit 3. This is equivalent to the case where a pull-up resistor is attached to the input buffer having the hysteresis characteristic, and this embodiment operates as a Schmitt trigger type input buffer circuit with a pull-up resistor.

The above-mentioned control terminals 7 and 9 can be set to either a high level or a low level by an external circuit to allow the semiconductor integrated circuit to have an arbitrary input buffer function, but other embodiments are possible. As an alternative, it is also possible to output the output of a read only memory (ROM) in which the control data can be arbitrarily rewritten to the control terminals 7 and 9. The ROM can be built in the semiconductor integrated circuit or used as an external circuit.

Further, by replacing the above N-type field effect transistor with a P-type field effect transistor and replacing the P-type field effect transistor with an N-type field effect transistor, respectively, and setting the related signals to opposite polarities, the logic circuit is changed. , And it is possible to achieve the same effect. In this case, the hysteresis characteristic of the Schmitt trigger type input buffer circuit can be obtained with the reverse characteristic.

[0039]

As described above, according to the input buffer circuit of the present invention, the function of the input buffer can be freely set and changed in a short time by switching the input of the external terminal of the semiconductor integrated circuit. Have

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an input buffer circuit of the present invention.

FIG. 2 is a diagram showing hysteresis characteristics of a Schmitt trigger type input buffer circuit.

FIG. 3 is a block diagram showing an input buffer circuit of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 N-type field effect transistor 2 Resistance 3 Inversion type input buffer circuit 4 NOR circuit 5 N-type field effect transistor 6 Inverter 7 Control terminal 8 Input terminal 9 Control terminal 10 Power supply terminal 11 Output terminal 12 Pull-up resistor 13 P-type field effect transistor 14 N-type field effect transistor 15 N-type field effect transistor 16 Inverter

Claims (3)

[Claims] 1. A first control terminal, a first N-type field effect transistor having a gate connected to the control terminal, a drain connected to a power supply terminal, and a source connected to one end of a resistor; and a drain having the power supply. A P-type field effect transistor connected to a terminal and a second N-type field effect transistor having a source connected to ground, the gates of these transistors being commonly coupled and connected to the input terminal and the other end of the resistor and An inverting type input buffer circuit in which a source of the P-type field effect transistor and a drain of the second N-type field effect transistor are connected to each other to serve as an output terminal;
An inverter that inverts the control signal at the control terminal of the NOR circuit, a NOR circuit to which the inverter output and the output of the inverting input buffer circuit are input, and a gate connected to the output of the NOR circuit and a drain connected to the output terminal. And an input buffer circuit having a third N-type field effect transistor whose source is connected to the ground point. 2. A first control terminal, a first N-type field effect transistor having a gate connected to the control terminal, a drain connected to a power supply terminal, and a source connected to one end of a resistor, and a drain having the power supply. A P-type field effect transistor connected to a terminal and a second N-type field effect transistor having a source connected to ground, the gates of these transistors being commonly coupled and connected to the input terminal and the other end of the resistor and An inverting type input buffer circuit in which a source of the P-type field effect transistor and a drain of the second N-type field effect transistor are connected to each other to serve as an output terminal;
An inverter that inverts the control signal from the control terminal of the NOR circuit, a NOR circuit to which the inverter output and the output of the inverting input buffer circuit are input, and a gate connected to the output of the NOR circuit and a drain connected to the output terminal. An input having a third N-type field effect transistor whose source is connected to the ground point and a read-only memory which outputs a control signal to the first and second control terminals. Buffer circuit. 3. The first and second N-type field effect transistors are P-type field effect transistors, and the P-type field effect transistor is an N-type field effect transistor. The input buffer circuit according to item 2.