JPH0369189B2 - - Google Patents

Info

Publication number
JPH0369189B2
JPH0369189B2 JP59156801A JP15680184A JPH0369189B2 JP H0369189 B2 JPH0369189 B2 JP H0369189B2 JP 59156801 A JP59156801 A JP 59156801A JP 15680184 A JP15680184 A JP 15680184A JP H0369189 B2 JPH0369189 B2 JP H0369189B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
thick film
circuit device
film hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59156801A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6135555A (ja
Inventor
Tooru Kamata
Shozo Noguchi
Yasuhiro Kurokawa
Kazuaki Uchiumi
Hideo Takamizawa
Keiichi Yotsuyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15680184A priority Critical patent/JPS6135555A/ja
Publication of JPS6135555A publication Critical patent/JPS6135555A/ja
Publication of JPH0369189B2 publication Critical patent/JPH0369189B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
JP15680184A 1984-07-27 1984-07-27 厚膜混成集積回路装置 Granted JPS6135555A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15680184A JPS6135555A (ja) 1984-07-27 1984-07-27 厚膜混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15680184A JPS6135555A (ja) 1984-07-27 1984-07-27 厚膜混成集積回路装置

Publications (2)

Publication Number Publication Date
JPS6135555A JPS6135555A (ja) 1986-02-20
JPH0369189B2 true JPH0369189B2 (enrdf_load_stackoverflow) 1991-10-31

Family

ID=15635615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15680184A Granted JPS6135555A (ja) 1984-07-27 1984-07-27 厚膜混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS6135555A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2787953B2 (ja) * 1989-08-03 1998-08-20 イビデン株式会社 電子回路基板
JPH0379504U (enrdf_load_stackoverflow) * 1989-12-07 1991-08-14
JP2004303466A (ja) 2003-03-28 2004-10-28 Canon Inc ヒータ駆動回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178688A (ja) * 1984-02-27 1985-09-12 株式会社東芝 高熱伝導性回路基板
JPS60178687A (ja) * 1984-02-27 1985-09-12 株式会社東芝 高熱伝導性回路基板

Also Published As

Publication number Publication date
JPS6135555A (ja) 1986-02-20

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term