JPH0367338A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To attain the effective use of a memory by providing a vector selection register between an interruption factor and a vector and selecting the vector to the interruption factor. CONSTITUTION:The contents of a vector selection register 3a are changed with an interruption factor 1a, and the vectors 2d, 2e, 2f, etc., are freely selected to start plural interruption routines. In the same way, the contents of the vector selection registers 3b and 3c are changed with the interruption factors 1b and 1c, and the vectors 2d - 2f are selected to start plural interruption routines. Thus the registers 3a - 3c are provided between the interruption factors 1a - 1c and the vectors 2d - 2f. As a result, the vectors 2 can be freely selected to the factors 1a - 1c. Thus the desired vectors 2 if included in a memory have not to be newly produced with application of factors 1a - 1c. Then the memory can be effectively used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control circuit that makes effective use of memory.

[Conventional technology]

FIG. 2 is a block diagram showing the operation 4 of a conventional interrupt circuit. In the figure, ... is an interrupt factor, rla)H@
1 +7) Interruption factor, rtb) Hth g-th interrupt factor, (lc) is the eighth interrupt factor. (2) Jump destination storage address on the hafmori map (hereinafter referred to as vector)
% (2a) is the first vector, (gb) is 2I
The vector of IIJg, (fa) is the eighth vector.

I will explain the next VC# work.

When the vector for the interrupt factor when the interrupt occurs is determined and it is the interrupt factor (1a) of button υ, @l, the CPU jumps to the jump address indicated by the first vector (ga) and enters the 1st interrupt routine. If it is the second interrupt cause (Ib), the process jumps to the destination address indicated by the B-th vector (8b) and enters the interrupt routine.

When it is the 8th interrupt factor (lc), the 80th pector Nt
The program jumps to the destination address indicated by c) and enters the interrupt routine.

[Problem to be solved by the invention]

Since the conventional interrupt circuit is configured as one or more, the first interrupt factor, the eighth interrupt factor, and the eighth interrupt factor are respectively the first vector, the second vector, and the i@8. The vectors correspond to l to l. For example, if the jump addresses indicated by the first vector, second vector, and eighth vector are the same address, there are 8 vectors indicating the same jump address on the memory map. When increasing the number, even if the destination address indicated by the vector corresponding to this factor already exists on the memory map, the number of vectors must be equal to the number of interrupt factors, so the number of vectors must also be increased. Must be increased. As mentioned above, there was a problem with the inefficiency of VC and memory.

This invention was made to solve the above-mentioned problems, and its object is to enable free VC selection for one interrupt factor using a vector, that is, a jump destination address program.

[Means to solve the problem]

The imprint control circuit according to the present invention is provided with a vector selection register between one interrupt cause and a vector storing a jump address for entering an interrupt routine.

[Effect]

The vector selection register according to the present invention allows vectors to be freely selected by a program.

〔Example〕

Hereinafter, one embodiment of the present invention will be described according to the drawings. FIG. 5 is a block diagram showing the operation of the 1-interrupt control circuit.

In the figure, +11, (la) ~ (la),
+! Since this is the same as that shown in the conventional example of the NjvIit diagram, a complete explanation will be omitted. (2d) is the fourth vector, (2
e) is the fifth vector, (2f) is the 60th vector, (8a
) fl is the first vector selection register, (8b) is the second vector selection register, and (8c) ij is the 80th vector selection register.

Next, the operation will be explained. 1g1 interrupt factor (l
In case a), the fourth vector (2d), @50 vector (2e), 60th vector (2f), and other vectors can be freely selected by changing the contents of the first vector selection register (8a). and can enter multiple interrupt routines. Similarly, the second interrupt factor (11)
), what about changing the contents of the eighth vector selection register (8b)?

The fourth vector (2d), the fifth vector (go), the sixth vector (2f), and other vectors can be freely selected, and a plurality of interrupt routines can be entered. 8th
When the interrupt factor (la) occurs.

By changing the contents of the 8th vector selection register (8C), the 4th vector (2d), 60th vector rge)
, the sixth vector (2f), and other vectors can be freely selected, and multiple interrupt routines can be entered.

〔Effect of the invention〕

As described above, according to the present invention, by providing a vector selection register between an interrupt cause and a vector, a vector can be freely selected by software for one interrupt cause.

This eliminates the need for as many vectors as the number of interrupt factors as in the past, and if there are multiple vectors indicating the same jump address, they can be combined into one vector. Even if you want to add a new interrupt source, if a vector indicating the jump destination address you want to jump to when this interrupt source is applied already exists on the memory map, there is no need to create a new vector, and just use vector selection. Just select a vector that already exists in the register. Therefore, memory? r: It becomes possible to use it effectively @

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the operation of an interrupt control circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram showing the operation of a conventional interrupt circuit. Factor % (la) is the first interrupt factor, (lb) f'i is the second interrupt factor, (
lc) is the interrupt factor of WIJ8, 2) Havector, (g
a) is the first vector, (21)) is the second vector, (2
c) ij is the 80th vector, (fa) is the 4th vector, (2
e'Jd is the fifth vector, (2f) is the sixth vector, (k
l first vector selection register, (8b) ij first vector selection register* (Jlc) is the eighth vector selection register. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An interrupt control circuit characterized in that a register is provided between an interrupt cause and a destination storage address on a memory map, allowing the destination storage address to be selected by a program.