JPH0365676B2 - - Google Patents

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Publication number
JPH0365676B2
JPH0365676B2 JP20829882A JP20829882A JPH0365676B2 JP H0365676 B2 JPH0365676 B2 JP H0365676B2 JP 20829882 A JP20829882 A JP 20829882A JP 20829882 A JP20829882 A JP 20829882A JP H0365676 B2 JPH0365676 B2 JP H0365676B2
Authority
JP
Japan
Prior art keywords
sheet
hole
holes
conductor
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP20829882A
Other languages
Japanese (ja)
Other versions
JPS5998596A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20829882A priority Critical patent/JPS5998596A/en
Publication of JPS5998596A publication Critical patent/JPS5998596A/en
Publication of JPH0365676B2 publication Critical patent/JPH0365676B2/ja
Granted legal-status Critical Current

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Landscapes

  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

〔発明の利用分野〕 本発明は電子部品を搭載するための多層セラミ
ツク基板に関し、特にスルーホールの形状を改良
した多層セラミツク基板に関する。 〔従来技術〕 電子部品を搭載する多層セラミツク基板は、多
くの文献に記載(例えば、「電子技術」第23巻第
14号P96〜100)されているように、シート積層
法によつて製造されている。 第1図A〜Cは、従来のシート積層法による多
層セラミツク基板の製造プロセスの一部を示すも
のである。まず、公知のドクターブレード法によ
つて作成されたセラミツクのグリーンシート(以
下、単に「シート」という。)1に、金型を用い
てスルーホールの打抜き加工を行うA。ここで、
従来は、ポンチ2の径を160μm、ダイ3の径を
180μmという如く、ポンチ・ダイ径差を20μm程
度にとると前記シート1上下の孔径がともにダイ
型にそろい、孔型Dが180μmである円筒形のス
ルーホール4を得ていた。 次に、孔あけ加工された前記シート1に導電ペ
ーストによるスルーホール4の導体充填を行い、
これに続いて、通常、前記導電ペーストとは異な
る組成を有する導電ペーストによる導体パターン
配線(以下、単に「配線」という。)5の印刷を
行うB。このとき、配線5とスルーホール4内の
導体4′の上面6との間の導体間隔Sは、前記印
刷のバラツキによつてシヨートを生じないように
するため、設計上60μm必要であつた。また、こ
の工程では、スルーホール4の孔埋充填不良が数
多く発生し問題となつていた。孔埋充填不良はス
ルーホール4の下部に導体ペーストが完全に行き
わたらず、空洞8が残る現象であり、これが発生
するとシート1の焼結時に基板にクラツクが入つ
たり、スルーホール4内での導体の断線が生じた
りするため、印刷後のシート1の外観検査を行つ
て不良シートを取り除いていた。 次の工程はシート1の積層であるC。この工程
では、検査済みのシート1をガイドピンを用いる
等して位置合わせするが、実際には位置ずれが発
生する場合があり、この場合、上側のシートのス
ルーホール4内の導体4′の下面7と下側のシー
トの配線5がシヨートするという不良が発生す
る。これは、第1図Cに示した積層体におけるシ
ートの位置合わせ精度aは15μm程度であるた
め、積層した場合のスルーホールと配線との間の
導体間隔S′は45μm程度となり、前記同一シート
内の導体間隔Sの3/4になつてしまうことに原因
があるが、この故障は外観検査では発見できない
ため、多層セラミツク基板の製造歩留りを低下さ
せることになり、重大な問題となつていた。 〔発明の目的〕 本発明は上記事情に鑑みてなされたもので、そ
の目的とするところは、従来の多層セラミツク基
板における上述の如き問題を解消し、前記スルー
ホールの孔埋充填不良および積層時の位置ずれに
起因するシヨート故障による製造歩留りの低下を
防止可能な多層セラミツク基板を提供することに
ある。 〔発明の概要〕 本発明の上述の目的は、セラミツク・グリーン
シートに孔あけ加工をを行い、該孔部に導電ペー
ストを充填するとともに必要な配線の印刷を行つ
た後、これを複数枚積層し焼結して作成される多
層セラミツク基板において、前記シートに設ける
孔を、上下に孔径差が焼結後寸法で略30μmある
孔としたことを特徴とする多層セラミツク基板に
よつて達成される。 〔発明の実施例〕 以下、本考案の実施例を図面に基づいて詳細に
説明する。 第2図A〜Cは本発明の一実施例である多層セ
ラミツク基板の製造プロセスの一部を示すもので
あり、前記第1図A〜Cに対応するものである。 まず、シート1にスルーホールの打抜き加工を
行うA。ここで重要なことは、例えば、ポンチ2
の径を140μm、ダイ3の径を180μmという如く、
ポンチ径を従来より更に小さくしてポンチ・ダイ
径差を40μm程度と積極的に大きくとるようにし
た点である。これにより、得られるスルーホール
4Aの形状は、ほぼ、円錐台状となり、シート1
上での孔径は、上側の孔径dは150μm、下側の
孔径Dは180μmにすることができた。 次に、孔あけ加工された前記シート1の孔径の
大きい面を上にして、導電ペーストによるスルー
ホール4Aの導体充填および印刷による配線5の
形成を、通常の方法により行うB。このとき、配
線5とスルーホール4A内の導体4Aの上面6A
との間の設計上の導体間隔Sは従来と同様60μm
とする。上記導体充填工程においては、スルーホ
ール4Aが、上部が拡がつた形であるため、導体
充填が従来よりスムーズに行われ孔埋充填不良が
発生しないという効果があり、印刷後シートの歩
留りを大幅に向上させることができた。 次の工程はシート1の積層であるC。この工程
で生ずるシート1の位置ずれaは前記ガイドピン
を用いる等の方法で位置合わせする関係で15μm
程度となる。しかしながら、本実施例のシート1
のスルーホール4Aの孔径は上側、下側で30μm
程度の差があるため、位置ずれaが15μm程度あ
つても、スルーホール4A内の導体4A′の上面
6Aと配線5との間の導体間隔Sは設計値60μm
が確保される。これにより、積層時のシヨート故
障が大幅に減少し、多層セラミツク基板の製造歩
留りを格段に向上させることができた。 本実施例における具体的な実験結判の一例を、
第1表に示す。第1表は、前述の、ポンチ2の径
を140μmとした場合の例を示すものであり、100
mm角のシートを18層積層したセラミツク多層基板
を作成した結果を示す例である。ここで、スルー
ホール数は20000穴、スルーホール間の配線の総
延長は約200mである。なお、従来例としては、
ダイ径165μmに対応するものを挙げた。 第1表に示す結果は、上述の方法により各5枚
のサンプルを作成し、充填不良およびシヨート不
良に関しては、全数検査によりその性能評価を行
つたものである。
[Field of Application of the Invention] The present invention relates to a multilayer ceramic substrate for mounting electronic components, and particularly to a multilayer ceramic substrate with improved through-hole shapes. [Prior Art] Multilayer ceramic substrates on which electronic components are mounted are described in many documents (for example, "Electronic Technology" Vol. 23,
14, pages 96-100), it is manufactured by a sheet lamination method. FIGS. 1A to 1C show part of a process for manufacturing a multilayer ceramic substrate using a conventional sheet lamination method. First, a process A in which through-holes are punched out using a mold in a ceramic green sheet (hereinafter simply referred to as "sheet") 1 created by a known doctor blade method. here,
Conventionally, the diameter of punch 2 was 160 μm and the diameter of die 3 was
When the punch-die diameter difference was set to about 20 μm, such as 180 μm, the hole diameters on the upper and lower sides of the sheet 1 were both aligned with the die shape, and a cylindrical through hole 4 with a hole shape D of 180 μm was obtained. Next, the through-holes 4 are filled with a conductor using conductive paste in the perforated sheet 1,
Following this, a conductor pattern wiring (hereinafter simply referred to as "wiring") 5 is printed using a conductive paste having a composition different from that of the conductive paste. At this time, the conductor spacing S between the wiring 5 and the upper surface 6 of the conductor 4' in the through hole 4 was designed to be 60 μm in order to prevent shorts from occurring due to the printing variations. Further, in this process, many defects in filling the through holes 4 occurred, which was a problem. Hole filling failure is a phenomenon in which the conductive paste does not completely spread to the bottom of the through hole 4, leaving a cavity 8. If this occurs, cracks may occur in the board during sintering of the sheet 1, or cracks may occur inside the through hole 4. Since the conductor of the sheet 1 may be disconnected, the appearance of the sheet 1 after printing is inspected to remove defective sheets. The next step is lamination of sheets 1 (C). In this process, the inspected sheet 1 is aligned using guide pins, etc., but in reality, misalignment may occur, and in this case, the conductor 4' in the through hole 4 of the upper sheet A defect occurs in which the lower surface 7 and the wiring 5 of the lower sheet are shot. This is because the positioning accuracy a of the sheets in the laminate shown in Figure 1C is about 15 μm, so the conductor spacing S' between the through hole and the wiring when stacked is about 45 μm, and the same sheet The cause of this failure was that the conductor spacing S within the circuit was reduced to 3/4, but since this failure could not be detected by visual inspection, it reduced the manufacturing yield of multilayer ceramic substrates and became a serious problem. . [Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to solve the above-mentioned problems in conventional multilayer ceramic substrates, and to solve problems such as poor filling of the through holes and during lamination. An object of the present invention is to provide a multilayer ceramic substrate that can prevent a decrease in manufacturing yield due to shot failure caused by positional deviation of the substrate. [Summary of the Invention] The above-mentioned object of the present invention is to form a hole in a ceramic green sheet, fill the hole with conductive paste, print necessary wiring, and then laminate a plurality of sheets. This is achieved by a multilayer ceramic substrate produced by sintering, wherein the holes provided in the sheet are holes with a diameter difference of approximately 30 μm between the top and bottom after sintering. . [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. 2A to 2C show a part of the manufacturing process of a multilayer ceramic substrate according to an embodiment of the present invention, and correspond to the above-mentioned FIGS. 1A to 1C. First, in step A, punching of through holes is performed on the sheet 1. The important thing here is, for example, punch 2
For example, the diameter of die 3 is 140 μm, and the diameter of die 3 is 180 μm.
The punch diameter is made smaller than before, and the difference between the punch and die diameters is increased to approximately 40 μm. As a result, the shape of the obtained through hole 4A becomes approximately a truncated cone shape, and the sheet 1
The upper pore diameter d was 150 μm, and the lower pore diameter D was 180 μm. Next, with the side of the perforated sheet 1 with the larger hole facing up, the conductor filling of the through holes 4A with conductive paste and the formation of the wiring 5 by printing are performed by a normal method B. At this time, the upper surface 6A of the conductor 4A in the wiring 5 and the through hole 4A
The designed conductor spacing S between the
shall be. In the above conductor filling process, the through holes 4A have a widened upper part, which has the effect of allowing conductor filling to be performed more smoothly than in the past, preventing defects in hole filling, and greatly increasing the yield of sheets after printing. was able to improve. The next step is lamination of sheets 1 (C). The positional deviation a of the sheet 1 that occurs in this process is 15 μm due to the alignment using the guide pins etc.
It will be about. However, sheet 1 of this example
The hole diameter of through hole 4A is 30 μm on the upper and lower sides.
Due to the difference in degree, even if the positional deviation a is about 15 μm, the conductor spacing S between the upper surface 6A of the conductor 4A′ in the through hole 4A and the wiring 5 is the designed value of 60 μm.
is ensured. As a result, shot failures during lamination were significantly reduced, and the manufacturing yield of multilayer ceramic substrates was significantly improved. An example of specific experimental results in this example is as follows:
Shown in Table 1. Table 1 shows an example when the diameter of the punch 2 is 140 μm, as described above.
This is an example showing the results of creating a ceramic multilayer substrate made by laminating 18 mm square sheets. Here, the number of through holes is 20,000, and the total length of wiring between the through holes is approximately 200 m. In addition, as a conventional example,
The ones that correspond to a die diameter of 165 μm are listed. The results shown in Table 1 were obtained by making five samples each using the method described above, and performing a 100% inspection to evaluate the performance for filling defects and shot defects.

【表】【table】

〔発明の効果〕〔Effect of the invention〕

以上述べた如く、本発明によれば、セラミツ
ク・グリーンシートに孔あけ加工を行い、該孔部
に導電ペーストを充填するとともに必要な配線の
印刷を行つた後、これを複数枚積層し焼結して作
成される多層セラミツク基板において、前記シー
トに設ける孔を、上下の孔径差が焼結後寸法で略
30μmある孔としたので、前記導電ペーストの孔
埋充填不良および積層時の位置ずれに起因するシ
ヨート故障を防止することができ、製造歩留りを
大幅に向上させるという効果を奏するものであ
る。
As described above, according to the present invention, holes are formed in ceramic green sheets, the holes are filled with conductive paste, and necessary wiring is printed, and then a plurality of sheets are laminated and sintered. In the multilayer ceramic substrate created by
Since the hole is 30 μm in size, it is possible to prevent shot failure due to poor filling of the conductive paste and positional deviation during lamination, and this has the effect of significantly improving manufacturing yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A〜Cは従来の多層セラミツク基板の製
造プロセスの一部を示す図、第2図A〜Cは本発
明の一実施例である多層セラミツク基板の製造プ
ロセスの一部を示す図、第3図A,Bは本発明の
他の実施例の要部を示す図である。 1:シート、2:ポンチ、3:ダイ、4,
4′:スルーホール、4A,4A′:スルーホール
内の導体、5:配線、6,6A:導体の上面、
7,7A:導体の下面。
1A to 1C are diagrams showing a part of the manufacturing process of a conventional multilayer ceramic substrate, and FIGS. 2A to 2C are diagrams showing a part of the manufacturing process of a multilayer ceramic substrate according to an embodiment of the present invention. FIGS. 3A and 3B are diagrams showing essential parts of another embodiment of the present invention. 1: sheet, 2: punch, 3: die, 4,
4': Through hole, 4A, 4A': Conductor in through hole, 5: Wiring, 6, 6A: Top surface of conductor,
7, 7A: Bottom surface of conductor.

Claims (1)

【特許請求の範囲】[Claims] 1 セラミツク・グリーンシートに孔あけ加工を
行い、該孔部に導電ペーストを充填するとともに
必要な配線の印刷を行つた後、これを複数枚積層
し焼結して作成される多層セラミツク基板におい
て、前記シートに設ける孔を、上下の孔径差が焼
結後寸法で略30μmある孔としたことを特徴とす
る多層セラミツク基板。
1. A multilayer ceramic substrate created by drilling holes in a ceramic green sheet, filling the holes with conductive paste, and printing the necessary wiring, then stacking and sintering a plurality of sheets. A multilayer ceramic substrate characterized in that the holes provided in the sheet have a diameter difference of approximately 30 μm between the upper and lower holes after sintering.
JP20829882A 1982-11-27 1982-11-27 Multilayer ceramic board Granted JPS5998596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20829882A JPS5998596A (en) 1982-11-27 1982-11-27 Multilayer ceramic board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20829882A JPS5998596A (en) 1982-11-27 1982-11-27 Multilayer ceramic board

Publications (2)

Publication Number Publication Date
JPS5998596A JPS5998596A (en) 1984-06-06
JPH0365676B2 true JPH0365676B2 (en) 1991-10-14

Family

ID=16553928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20829882A Granted JPS5998596A (en) 1982-11-27 1982-11-27 Multilayer ceramic board

Country Status (1)

Country Link
JP (1) JPS5998596A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6178116A (en) * 1984-09-25 1986-04-21 日本電気株式会社 Multilayer hybrid electronic component
JPS6196548U (en) * 1984-11-30 1986-06-21
JP2580074B2 (en) * 1990-11-30 1997-02-12 日本電装株式会社 Equipment for manufacturing ceramic substrates
JP4974422B2 (en) * 2001-06-25 2012-07-11 京セラ株式会社 Multilayer board

Also Published As

Publication number Publication date
JPS5998596A (en) 1984-06-06

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