JPH0363832A - Emulation chip - Google Patents

Abstract

PURPOSE:To easily obtain a targeted evaluation kit without preparing an out-fitted circuit by combining prescribed peripheral circuits in plural emulation chips by providing a memory circuit to store the address of the peripheral circuit in the inside and an address detection circuit. CONSTITUTION:Plural peripheral circuits 30, 31 allocated to prescribed addresses, the memory circuits 20, 21 which store the addresses of the plural peripheral circuits 30, 31, and detection circuits 22, 23 which detect the coincidence detection of the addresses by comparing the contents of the memory circuits 20, 21 with the addresses inputted to the emulation chip 5 are provided. Also, an OR circuit which sets the output of the detection circuits 22, 23 as input and controls whether or not the output of the emulation chip 5 should be prohibited is provided. In such a manner, it is possible to select the peripheral circuits 30, 31 in the plural emulation chips fitting in a targeted chip and to use them with combination.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an emulation chip.

[Conventional technology]

General emulation chips are used in evaluation kits (hereinafter referred to as evaluation kits) that have debugging functions for developing application programs in microcomputers.

Conventionally, this type of Eva kit uses a CPU (Central
It consisted of an evaluation chip (hereinafter referred to as an evaluation chip) that operated as a processing unit (Processing Unit), and three emulator chips that had built-in peripheral circuits such as a timer, serial interface, and ports.

Therefore, when developing a new microcomputer with the same CPU but different peripheral circuits, an emulation chip with the necessary peripheral circuits must also be manufactured.

On the other hand, as shown in FIG.
By combining the peripheral circuits included in the emulation chip 46 made for the microcomputer of
EVA kits for microcomputers are also being made.

At that time, if there is a peripheral circuit, such as a boat, that is included in both emulation chips and that reads and writes with the same address designation, a dedicated selection address decoder 41 is used to decide which of them to select. The necessary peripheral circuits are selected by switching circuits 43 and 44.

For example, when operating a timer in the emulation chip 45 and outputting data from a port in the emulation chip 46, first,
The address of the timer is output from the evaluation chip 1 to the address bus 3.

The selected address decoder 41 reads the address.

Here, since the timer is located in the emulation chip 45, the switching circuit 44 is inhibited by the selection signal S4y.

As a result, the data output from the evaluation chip 1 is transmitted only to the emulation chip 45, and data for operating the timer is written.

Next, when reading the timer value to the EV chip 1, the timer address is output, so the selection address decoder 41
Since the switching circuit 44 is inhibited in the same way as described above, the evaluation chip 1 can read the value of the timer in the emulation chip 45.

When outputting data to the boat, when the Eva chip outputs the address of the boat, the selection address decoder 44 receives the address of the boat and inhibits the switching circuit 43 by the selection signal S42.

Therefore, the data output from the Eva chip 1 will be output from the port in the emulation chip 46.

[Problem to be solved by the invention]

With the conventional emulation chips mentioned above, when making microcomputers using the same CPU but with different peripheral circuits, if you make individual emulation chips for each microcomputer, it is difficult to design each emulation chip. It is necessary to carry out quality tests such as property evaluation and lifespan.
The disadvantage is that development costs are high.

Further, as shown in FIG. 3, an emulation chip 45 containing the peripheral circuits of the first microcomputer and an emulation chip 46 containing the peripheral circuits of the second microcomputer are combined to form an emulation chip of the third microcomputer. When used as emulation chip 45 and emulation chip 4
In 6, peripheral circuits with the same type of function are assigned to the same address, so when two or more emulation chips are combined and used, it is necessary to determine which peripheral circuit of which emulation chip to select. There must be.

However, since the Eva chip does not have a means to select the emulation chip, a switching circuit must be inserted between the selection address decoder 41 and the address bus to switch, which has the disadvantage of increasing the number of components, and the address is not fixed. Therefore, if you select a peripheral circuit built into one emulation chip, you will no longer be able to use the peripheral circuits built into other emulation chips that are assigned to the same address. The drawback is that the scope of its use is narrow.

For example, when creating a new microcomputer with a large number of votes, if the emulation chip has a fixed address, the emulation chip with the most votes among the multiple emulation chips that can be used as a new microcomputer is the upper limit. There was a drawback that it became .

[Means to solve the problem]

The emulation chip of the present invention includes a plurality of peripheral circuits assigned to predetermined addresses, a memory circuit that stores the addresses of the plurality of peripheral circuits, and a memory circuit that compares the contents of the memory circuit with the address input to the emulation chip to determine the address. The device includes a detection circuit that performs coincidence detection, and an OR circuit that receives the output of the detection circuit as an input and controls whether or not to inhibit the output of the emulation chip.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a pull diagram of an evaluation kit using an embodiment of the present invention, and FIG. 2 is a block diagram of the inside of the emulation chip of FIG. 1.

First, FIG. 1 will be explained.

Eva chip 1 outputs address space switching signal 2,
It also outputs the address to address bus 3 and data bus 4.
Data input/output is performed via.

In addition, data read signal 7 and data write signal Ss
are output to the emulation chips 5 and 6, respectively.

The emulation chips 5 and 6 receive an address space switching signal S2, an address from an address bus 3, and input/output data via a data bus 4.

In addition, data read signal S7 and data write signal S
, respectively.

Next, FIG. 2 will be explained.

The input buffer 10 receives an address from the address bus 3 and outputs the address to the self registers 14 and 15.

The selector 14 is set when the address space switching signal 2 is High.
When , input the address output by input buffer lO,
Output to address decoders 18 and 19.

Here, when the address space switching signal S2 is Low, it is an address assigned to a peripheral circuit (hereinafter referred to as a peripheral address).

Specify the space and address space switching signal S2
At the time of h, the allocated address (hereinafter referred to as storage address) space of the storage circuit (hereinafter referred to as address storage circuit) that stores the peripheral address of each peripheral circuit is specified.

These two address spaces are assigned the same address and are switched by an address switching signal S.

Address decoder 18 includes peripheral circuits 31 . The storage address of the address storage circuit 20 that stores the peripheral address of is
When generated from the selector 14, it outputs High to the address storage circuit 20.

The address decoder 19 outputs the old gh to the address storage circuit 21 when the storage address of the address storage circuit 21 that stores the peripheral address of the peripheral circuit 30 is generated from the selector 14 .

The inversion circuit 13 inputs the address space switching signal 2,
Output to selector 15 and selector 17.

When the output of the inversion circuit 13 is old gh, the selector 15 outputs the peripheral address output from the input buffer 10 to the address-number output circuits 22 and 23.

The input buffer 11 receives data output from the data bus 4 and outputs it to the selectors 16 and 17.

The output buffer 12 is configured so that the output of the AND circuit 24 is High.
At this time, the data on the internal data bus 32 is output to the data bus 4.

The selector 16 is set when the address space switching signal 2 is High.
At this time, the data output from the input buffer 11 is output to the address storage circuits 20 and 21.

The output of the inverting circuit 13 is the old GH for the selector 17.

At this time, the data output from the input buffer 11 is output to the internal data bus 32.

The address storage circuit 20 stores the data output from the selector 16 as the peripheral address of the peripheral circuit 31 using the data write signal S8 when the output of the address decoder 18 is old gh.

When the output of the address decoder 19 is old gh, the address storage circuit 21 stores the data output from the selector 16 as the peripheral address of the peripheral circuit 300 using the data write signal S.

The address-number output circuit 22 compares the address output by the selector 15 and the peripheral address stored in the address storage circuit 20, and when they match, sets the match signal 821 to the old gh.

The address/number configuration circuit 23 compares the peripheral address output from the selector 15 with the peripheral address stored in the address storage circuit 21, and when they match, a match signal S!
, to High.

The OR circuit 25 inputs the coincidence signal 32m + 82@,
Output to AND circuit 24.

The AND circuit 26 connects the output of the OR circuit 25 and the inverting circuit 13.
, and outputs a control signal for the output buffer 12.

The AND circuit 33 inputs the match signal S2S and the data read signal S, and outputs it to the peripheral circuit 30.

The AND circuit 34 inputs the match signal 829 and the data write signal S and outputs it to the peripheral circuit 30.

The AND circuit 35 inputs the match signal 821 and the data read signal S, and outputs it to the peripheral circuit 31.

The AND circuit 36 outputs the match signal 821 and the data write signal S.
, is input and output to the peripheral circuit 31.

The peripheral circuit 30 outputs data to the internal data bus 32 when the output of the AND circuit 33 is old gh, and inputs data from the internal data bus 32 when the output of the AND circuit 34 is old gh.

The peripheral circuit 31 outputs data to the internal data bus 32 when the output of the AND circuit 35 is old gh, and inputs data from the internal data bus 32 when the output of the AND circuit 36 is old gh.

Next, the operations shown in FIGS. 1 and 2 will be explained.

First, when the Eva chip l is started, it sets all the peripheral addresses of the peripheral circuits in the emulation chip in accordance with the periphery of the target chip, and then starts normal emulation operation.

When setting the peripheral address of the peripheral circuit in the emulation chip, first use the address space switching signal S.
2 to the old gh, select the storage address space, and open selector 14.16.

The evaluation chip outputs the memory address of the address storage circuit corresponding to the peripheral circuit for which the peripheral address is to be set to the address bus 3, and outputs the peripheral address to be set to the data bus 4.

The input buffer lO receives an address from the address bus 3 and outputs it to the selector 14.

Here, for example, a case where the address of the peripheral circuit 30 is set will be described.

Address decoder 19 receives the address output from selector 14 .

If the address output by the selector 14 is the address assigned to the address storage circuit at this time, the address decoder 19 outputs the old gh.

The address storage circuit 21 is permitted to write since the output of the address decoder 19 is the old gh.

On the other hand, the input buffer 11 inputs the peripheral address to be set from the data bus 4 and outputs it to the selector 16.

The selector 16 inputs the address output from the input buffer 11 and outputs it to the address storage circuit 21.

At this time, the address storage circuit 21 receives the data write signal S.
, is the old gh, the peripheral address output from the selector 16 is written into the address storage circuit 21.

As described above, the peripheral address of the peripheral circuit is set according to the target chip.

Next, in FIG. 1, the evaluation chip 1 sends data to the timer of the emulation chip 5 (for example, the peripheral circuit 30 in FIG. In this section, the case of sending data to the peripheral circuit 30) will be described.

First, the Eva chip 1 sends the selector switching signal S! is L
ow (for example, normal operating state) and selector 15,
Select 17.

It also outputs the peripheral address of the timer of the emulation chip 5 to the address bus 3.

The input buffer 1° of the emulator 3 chip 5 receives the input peripheral address from the address bus 3 through the selector 15.
Output to.

The selector 15 outputs the peripheral address input from the input buffer 15 to the address-number output circuits 22 and 23.

The address-number output circuit 22 is stored in the address storage circuit 20.

A match signal S is sent because there is no match compared with the peripheral address. is Low, and on the other hand, the address-number output circuit 23 compares it with the peripheral address stored in the address storage circuit 21, and since they match, it outputs the old gh.

On the other hand, in order to write data to the timer, the EVA 1 outputs the data to be written to the data bus 4, and sets the data write signal S to the old gh.

The input buffer 11 inputs data on the data bus 4 and outputs it to the selector 17.

The selector 17 outputs the data output from the input cover 11 to the internal data bus 32.

On the other hand, since the data write signal S is the old gh and the match signal 29 is also the old gb, the AND circuit 34 outputs the old gh and permits writing of data to the timer. You can receive data from.

In the manner described above, the Evachip 1 can write data to the timer.

Next, when the Eva chip 1 reads data from the timer, it first outputs the peripheral address of the timer to the address bus 3 and sets the data read signal S7 to the old gh.

Here, the timer is selected in the same manner as when writing data.

On the other hand, since the data read signal St is the old gh, A
The ND circuit 34 becomes the old GH and permits reading of data from the timer.

As described above, the timer data is transferred to internal data bus 3.
Output to 2.

At this time, since the coincidence signal S2゜ is the old gh, the OR
Circuit 25 is old GH, while selector switching signal 2 is L
Since it is OW, the inversion circuit 13 becomes the old gh, and the AND circuit becomes the old gh.

Here, the output buffer 12 is the control signal AND@path 2
Since the output of 4 is the old gh, the data on the internal data bus 32 is output to the data bus 4.

Further, since different peripheral addresses are set for the peripheral circuits in the one-sided emulation chip, those peripheral circuits are not selected, and the ou circuit 25 of the other emulation chip is Low, and the AND circuit 24 is Low, the output buffer is prohibited, and only the emulation chip containing the target peripheral circuit can output data to the data bus 4.

Next, if you want to output the data read by Evachip 1 as described above to the emulation chip board,
This is done in the same way as when writing to the timer of the emulation chip 5.

In the manner described above, peripheral circuits from a plurality of emulation chips can be selected and used in combination.

In this embodiment, the reason why the address space switching signal and selector group are provided is that the address space is separate, and the peripheral address space of the peripheral circuit is not narrowed. However, by changing the peripheral address and the memory address, It is also possible to eliminate selector groups by placing them in the same space.

[Effects of the Invention] As explained above, the present invention has a memory circuit for storing addresses of peripheral circuits and an address detection circuit inside an emulation chip, so that a predetermined peripheral circuit in a plurality of emulation chips can be Combining and attaching the desired EVA kit externally has the effect of easily realizing it without a circuit.

In addition, since the emulation chip of the present invention can freely set the address of each peripheral circuit, it is possible to use as many peripheral circuits as necessary depending on the target chip, and to use existing emulation chips. There is also the effect that the new microcomputers could potentially be exploited for.

[Brief explanation of drawings]

Figure 1 is a block diagram of an evaluation kit using an embodiment of the present invention, Figure 2 is an internal block diagram of the emulation chip shown in Figure 1, and Figure 3 is an example of a conventional emulation chip. FIG. 2 is a block diagram of an evaluation kit. 1...Evaluation chip, 3...Address bus, 4...Data bus, 5...Emulation chip, 6...Emulation chip, 10・・・・・・Enkahafa, 11・・・・・・
・Input Huffer, 12... Output Huffer, 13
...Inverting circuit, 14...Selector, 1
5...Selector, 16...Selector,
17...Selector, 18...Address decoder, 19...Address decoder, 20.
... Address storage circuit, 21 ... Address storage circuit, 22 ... Address - several sheet output circuit,
23... Address - several output circuit, 24...
...AND circuit, 25...OR circuit, 30...
... Peripheral circuit, 31 ... Peripheral circuit, 32.
...Internal data bus, 33...AND circuit, 34...AND circuit) 35...A
ND circuit, 36...AND circuit, 41...
...Selection address decoder, 43...Switching circuit, 44...Switching circuit, 45...
・Emi. Raysilan chip, 46...Emulation chip, Sl...Address space switching signal, S
7... Data read signal, Sl... Data write signal, 82@r S2@'... Match signal, 842... Selection signal, Sat...・
・Selection signal.

Claims (1)

[Claims] In an emulation chip that includes a plurality of peripheral circuits and outputs data of a predetermined peripheral circuit from the plurality of peripheral circuits from a tri-state buffer in response to a read request, the plurality of peripheral circuits store addresses assigned to each of the peripheral circuits. a storage means, a plurality of detection means for comparing the contents of each of the storage means and an address input to the emulation chip and detecting a match between the addresses, and an OR circuit receiving the outputs of the plurality of detection means as input; An emulation chip characterized in that the tri-state buffer is controlled by the output of the OR circuit.