JPH03110489A - Pattern generating device - Google Patents

Abstract

PURPOSE:To facilitate timing control by providing an algorithmic pattern generator and a '0' or '1' pattern generator and selecting their outputs by a selector. CONSTITUTION:The selector 6 selects the output of either of the algorithmic pattern generator 3, all-'0' pattern generating circuit, and all-'1' pattern generat ing circuit 5 according to a selection control signal from a pattern generator selection data memory 8. Then this selection is made by reading data dynami cally out of a memory according to the address access of a memory device to be measured, so a combination of an algorithmic pattern and a random sequential pattern is free set according to the contents of the data stored in the memory. Further, selected data is stored in the memory and read out, so the timing control is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a pattern generator, and more specifically, in an IC tester that generates an algorithmic pattern to test a memory, it is possible to generate an algorithmic pattern and a random sequential pattern. The present invention relates to a pattern generating device that can generate patterns in combination.

[Prior Art] In the conventional pattern generator of an IC tester for memory,
An algorithmic pattern that changes sequentially is generated using an arithmetic unit (ALU). On the other hand, in the pattern generator of a logic tester, a sequence pattern generator (
It has an address circuit that accesses a pattern memory called a sequence generator (SQPG) or a sequence generator, and sets pattern data to be generated in the pattern memory to generate a predetermined pattern necessary for testing.

[Problem to be solved] Recent memory IC testers perform tests by generating algorithmic patterns such as checker patterns and diagonal patterns, as well as tests that generate combination patterns that generate random sequential patterns in the middle. occurrence is required. However, it is fundamentally difficult to generate completely random sequential patterns using an ALU, and conversely, it is difficult to generate regular patterns using a pattern generator that accesses a pattern memory. In other words, when using pattern memory to generate regular patterns, the longer the period of continuous pattern generation, the more memory capacity must be allocated accordingly. It is difficult to generate an algorithmic pattern with a long length.

Therefore, an idea is to generate an algorithmic pattern using the ALU, generate a random pattern using the data stored in the pattern memory, and then control switching between these to generate a combination of the algorithmic pattern and the random pattern. However, when pattern generators having different configurations are switched midway to perform $ control, there is a drawback that timing control becomes difficult.

The present invention solves the problems of the prior art, and provides a pattern generator capable of generating a combination of an algorithmic pattern and a random sequential pattern under nctt $Ij control. Let that be [1 point].

[Means for Solving the Problems] In order to achieve such an rJ characteristic, the pattern generator of the present invention includes a first pattern generator that generates an algorithmic pattern, and a "0" pattern or a "1" pattern. a second pattern generator that generates a pattern; a selector that receives outputs from the first and second pattern generators and selects one of the outputs according to a control signal; and the control signal. , and the memory is accessed in response to address access by the device under test.

[Operation] In this way, the algorithmic pattern generator and “0
” or “1” pattern generator, these outputs are selected by a selector, and this selection is performed by dynamically reading data stored in the memory in accordance with address access of the memory device to be measured. Therefore, combinations of algorithmic patterns and random sequential patterns can be freely set according to the contents of the data stored in the memory.Furthermore, since the selected data is stored in the memory and read out, Timing control is easy.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the pattern generator of the present invention, and FIG. 2 is an explanatory diagram showing an example of a combination of an algorithmic pattern and a random pattern.

10 is a pattern generation system, which includes a CPU 1;
A pattern generator (PG) 2, an algorithmic pattern generator 3 that generates an algorithmic pattern.
, an all "0" pattern generating circuit 4, an all "1" pattern generating circuit 5, a selector 6, an EXOR circuit 7, and a pattern generator selection data memory 8.

The CPU I, PG2, algorithmic pattern generator 3, and pattern generator selection data memory 8 are connected to each other via a bus 9! i, and the algorithmic pattern generator 3 receives a control signal from the PG2 and generates, for example,
Data such as checker patterns and diagonal patterns are generated in response to address access to the memory of the device under test (1) UT) 11. Note that 11 is a memory device as a DUT, to which pattern data (DATA) and address signals (ADD) are supplied from the pattern generator 10 via a pin electronics circuit (not shown) or the like.

The algorithmic pattern generator 3 is composed of an address generator 31 and a data generator 32, and inside the address generator 31, an ALU 31a, a register 31b,
31c is provided.

An addition value is set in the register 31b from the CPUI,
The addition and subtraction of the ALU 31a is controlled by a control signal from the PG2. The data generation circuit 32 has various built-in logic circuits such as an EXOR circuit and an ANI) circuit, and one of these logic circuits is selected by a control signal from the PG2. In response to the signal (A I) D), the address data is processed by the logic circuit selected by PO2, and algorithmic pattern data is generated by the logic circuit and output from the algorithmic pattern generator 3.

Here, the address generator 31 selects the DUT II to be tested.
It generates two addresses, X and Y, according to the RAS and CAS of , and sends them to DUT II. For that reason AL
U31a is composed of two ALUs corresponding to X and Y, respectively, and two registers 31b and 31c are also provided corresponding to X and Y, respectively.

The PO2 is mainly composed of an instruction memory as in the past, and has a built-in selector, program counter, and the like. Various types of control data are output according to the data contents of the instruction memory, and a portion of the control data is set in the program counter to control the sequence of pattern data to be generated next.

The all "0" pattern generation circuit 4 always applies an output of "O" to the selector 6, and the all "1" pattern generation circuit 5 always applies an output of "1" to the selector 6.

The selector 6 selects one of the algorithm pig pattern generator 3, all "0" 7 inch turn generation circuit 4, or all "1" pattern generation circuit 5 according to the selection control signal from the pattern generator selection data memory 8. Select one output.

The pattern generator selection data memory 8 has an address space equal to or larger than the address space (memory capacity) of the DUTll, and control data to be selected from the CPU 1 is set therein, and the pattern generator selection data memory 8 is set with control data to be selected from the CPU 1.
The control data read out by the X and Y address signals from the address generator 31 is applied to the selector 6 and the EXOR circuit 7, respectively.

The data added to the selector 6 from the pattern generator selection data memory 8 is data for selecting one of the three notch generators, so only 2-bit data is required, and the data is applied in accordance with the address access of the DUTll. The algorithmic pattern is generated 7A43 by being read out.
The selector 6 selects the output of one of the all "0" turn generation circuit 4 and the all "1" pattern generation circuit 5. Also, the data of 1 pin applied to the other input of EXOR circuit 7 is “0”.
” or “1” determines whether the selected output of the selector 6 is inverted or not, and this one bit is also sent out from the pattern generator selection data memory 8 in response to the address access of DUT II.

Next, the operation of the pattern generator 10 will be explained. First, the CPU operates the algorithm to control the turn generator 3, the all "0" pattern generation circuit 4, and the all "1" pattern generation circuit 5 according to the address access of the ADUT II. The selection data 8 is stored in the pattern generator selection data memory 8 corresponding to the address of the selection data DUTII.

Next, when the CPUI starts PO2 and tests it, P
When the pattern generator selection data memory 8 and DUTll are simultaneously accessed by the X and Y address signals generated from the algorithmic pattern generator 3 under the control of O2 and the same address is specified, the data selected for that address is The resulting pattern is output from the EXOR circuit 7, and is written to the same address of I) UTII.

As a result, data for selecting the algorithmic pattern generator 3 is written in the white address area in the pattern generator selection data memory 8 as shown in FIG. 2(a).
Data for selecting the all “0” pattern generation circuit 4 is written in the hatched address area, and P
If the algorithmic pattern selected by O2 is a checker pattern, such data is
When the pattern generator selection data is read from the memory 8 at the same time as the Tll address access, as shown in FIG. 2(b).
As shown in the figure, a checker pattern is assigned to the white address area, and “0” is assigned to the hatched address area.
The combination pattern to which "" is assigned is written to DUTII. In the above case, the EXOR circuit 7 is always set to "0".
``Suppose it is human data.

The following describes the checker pattern, but the algorithmic pattern generator 3 is provided with various patterns, and the all "0" pattern generation circuit 4 and the all "1" pattern generation circuit 5 are also used. I) More complex patterns can be generated by dynamically selecting UTII depending on the address being accessed. Furthermore, various random patterns can be generated by freely combining algorithmic patterns and random "O"s and "1"s in correspondence with addresses.

As described above, the pattern generator selection data memory may be a ROM in which data is set in advance without writing data from the CPU. Further, in the embodiment, both an all "0" pattern generation circuit and an all "1" pattern generation circuit are provided, but only one of these may be used.

In an embodiment, the pattern generator selection data memory and I)
UT and T are accessed in a 1:1 address correspondence, but these are accessed in a 1:1 address correspondence (n is an integer greater than 2 and D
(corresponding to UT).

[Effect of the invention] As can be understood from the explanation below, in this invention, an algorithmic pattern generator and "O" or "
1" pattern generator, these outputs are selected by a selector, and this selection is made by dynamically reading data stored in the memory in accordance with address access of the memory device to be measured. Combinations of algorithmic patterns and random sequential patterns can be freely set according to the content of data stored in the memory.Furthermore, since the selected data is stored in the memory and read out, its timing can be controlled. It's easy.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the pattern generator of the present invention (D
The book diagram, FIG. 2, is an explanatory diagram showing an example of the combination of the algorithmic pattern and the random pattern. l... CPU, 2... PG (sequential generator), 3... algorithmic pattern generator,
4... All "0" pattern generation circuit, 5... All "L" pattern generation circuit, 6... Selector, 7... -
EXOR circuit, 8... Pattern generator selection data memory, 9... Bus, 10... Pattern generation system, 11... Device under test (DUT).

Claims (1)

[Claims] (1) A first pattern generator that generates an algorithmic pattern, a second pattern generator that generates a “0” pattern or a “1” pattern, and outputs from the first and second pattern generators. a selector that receives the control signal and selects one of these outputs according to a control signal; and a memory that generates the control signal, and the memory is accessed in response to address access of the device under test. A pattern generator featuring: