JPH036125A - Clocked in-phase circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction due to a noise by connecting in series N-P channel transistors which gate-input a data signal and P-N channel transistors which gate-input a clock signal, respectively. CONSTITUTION:When the clock signal (phi) goes to to 'L' and transistors(TR) Q2 and Q3 are turned off and the electric charge of a load capacitor C1 is held at a charged state, a voltage between the source and the gate of the TR Q3 can be prevented from exceeding the threshold value due to the noise even when the TR Q4 is turned on by a ground noise, and also, the TR Q3 remains at an off state, and no malfunction to discharge the capacitor C1 occurs. Also, even when the electric charge of the capacitor C1 is discharged and a TR Q1 is turned on by a power source noise at the time of turning off the TRs Q2 and Q3, the TR Q2 remains turned off, and no malfunction to charge the capacitor C1 occurs. Therefore, the malfunction due to the noise can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clocked in-phase circuit used in a semiconductor integrated circuit.

[Conventional technology]

FIG. 2 is a circuit diagram of an example of a conventional clocked in-phase circuit. Transistor Q2. Q!
This is a circuit that can hold the charge of the load capacitor C1 by turning off. When transistor Q21Q is off and the charge stored in load capacitor C1 is discharged, if noise occurs in the power supply, which is the source electrode of the P-channel transistor, P-channel transistor Q5. Q2 gate
Due to the change in the voltage between the sources, the transistors Qs and Qa are turned on, and the load capacitor C1 is charged with charge, which may cause malfunction. Also, transistor Q2. When Q3 is off and load capacitance C1 is charged,
When noise occurs at the ground, which is the source electrode of the N-channel transistor Q6, the N-channel transistor Qs
, Qa may turn on due to a voltage change between the gate and source of Qa, and the charge stored in the load capacitor C1 may be discharged, causing a malfunction.

[Problem to be solved by the invention]

In the conventional clocked common-mode circuit described above, when noise occurs in the power supply that is the source electrode of the P-channel transistor Q, the transistors Q a and Q 2 may turn on and malfunction, and the N-channel transistor There is a drawback that when noise occurs in the ground, which is the source electrode of Q6, transistors Q31Q6 may turn on and cause malfunction.

An object of the present invention is to provide a clocked common-mode circuit which eliminates these drawbacks and reduces the possibility of malfunction.

[Means to solve the problem]

The configuration of the clocked in-phase circuit of the present invention is such that a first N-channel transistor whose gate input is a data input signal and whose source electrode is connected to a power supply is connected in series with a tenth P-channel transistor whose gate input is a clock negative phase signal. A 20th P-channel transistor whose gate input is the data signal and whose source electrode is grounded is connected in series with a second ON-channel transistor whose gate input is the clock signal, and the source of the first P-channel transistor is connected in series. The present invention is characterized in that the electrode and the drain electrode of the second N-channel transistor are commonly connected to form an output terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the clocked in-phase circuit of the present invention. An N-channel transistor Q1 whose source electrode is the power supply VDD, a P-channel transistor Q2 connected in series to this transistor Q1, a P-channel transistor Q4% whose source electrode is the ground, an N-channel transistor Q4 connected in series to this transistor Q4. It consists of a channel type transistor Q.

When data signal A is high, transistor Qt is on and transistor Q4 is off. When the clock signal φ becomes high, the transistor Q2°Q turns on and charges the load capacitor C1. and clock signal φ
becomes low, transistor Q2. Q3 is turned off and the charge on the load capacitor C1 is held. Even if the P-channel transistor Q is on, its drain voltage will not become lower than the gate voltage, so the data signal A will be low, and even if the transistor Q4 is on, the noise generated on the ground will cause the transistor Q, The drain voltage of transistor Q is never lower than the gate voltage, and the source voltage of transistor Q is never lower than the gate voltage. Therefore, due to ground noise, transistor Q,
Since the voltage between the source and gate of the transistor Q3 does not exceed the threshold value, the transistor Q3 remains in an off state, and a malfunction in which the charge in the load capacitance C1 is discharged does not occur.

Further, when the data signal A is low, the transistor Ql is turned off and the transistor Q4 is turned on. When clock signal φ goes high, transistors Q2. Q3 is turned on and the charge stored in the load capacitor C1 is discharged. Then, when the clock signal φ becomes low, the transistor Q2
．． Q3 is turned off and the charge on the load capacitor C1 is held. Even when the N-channel transistor Q1 is turned on, its drain voltage does not become higher than the gate voltage, so even if the data signal A is high and the transistor Q1 is turned on, the noise generated in the power supply causes the transistor Q+
Since the drain voltage of transistor Q2 never becomes higher than the gate voltage, the source voltage of transistor Q2 never becomes higher than the gate voltage.

Therefore, the voltage between the source and gate of the transistor Q2 will not exceed the threshold value due to power supply noise, and a malfunction in which the transistor Q2 remains off and the load capacitor C1 is charged will not occur.

As described above, the present invention provides a clocked common-mode circuit that does not malfunction due to noise generated in the power supply or ground.

[Effects of the Invention] As is clear from the above description, the clocked common-mode circuit of the present invention can prevent malfunctions caused by noise generated in the power supply or ground, and can reduce the number of transistors compared to conventional circuits. There is an effect that it can be done.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a clocked in-phase circuit of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional clocked in-phase circuit. A...Data signal, φ...Clock signal, ■...Clock reverse phase signal, n......
Transistor output, V on - power supply, C1...
...Load capacity, Ql, Q31Q a, Q *・
...N-channel transistor, C2゜C4,Q
s, Qv...P channel type transistor.

Claims (1)

[Claims] A first N-channel transistor whose gate input is a data input signal and whose source electrode is connected to a power supply is connected in series with a first P-channel transistor whose gate input is a reverse phase clock signal, and the data signal is input to the gate. A second P-channel transistor whose source electrode is grounded and a second N-channel transistor whose gate input is a clock signal are connected in series, and the source electrode of the first P-channel transistor and the second A clocked in-phase circuit characterized in that drain electrodes of N-channel transistors are commonly connected to serve as an output terminal.