JPS59207735A - Input circuit - Google Patents

Abstract

PURPOSE:To increase operating speed of an input circuit by selecting an input circuit of relatively low threshold value voltage when an input signal rises and selecting an input circuit of relatively high threshold value voltage when the input signal falls. CONSTITUTION:An input circuit 1 has relatively low threshold value voltage Vth1, and an input circuit 2 has relatively high threshold value voltage Vth2. Output of circuits 1, 2 is supplied to SWS1 and S2 of a switching SW section 4, and SWS1, S2 are controlled by a switch control circuit 3. The hysteresis circuit 5 of the circuit 3 has two threshold value voltage Vth3 (<Vth1) and Vth4 (>Vth2), and output of the circuit 5 controls SWS1, and output of an inverter IV1 of the circuit 3 controls SWS2. Before rise of an input signal Vin, SWS1 is on state and S2 is off state. At rise time of the signal Vin, the circuit 1, circuit 2 and circuit 5 fall at Vth1, Vth2, Vth4 respectively, and at fall time of the signal Vin, the circuit 1, circuit 2 and circuit 5 rise at Vth1, Vth2 and Vth3 respectively. Accordingly, output of IV2 of the SW section 4 falls at Vth1 and rises at Vth2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is particularly effective when applied to large-scale integrated circuits (hereinafter referred to as LSI).
The present invention relates to a technology that is effective for use in input circuits within LSIs for receiving signals from the outside.

[Background technology]

Generally, in an LSI or the like, an input signal generated from an external signal generating means is provided within the LSI and supplied to a π input circuit. For example, it is known from Figure 5.15 on page 280 of the integrated circuit application handbook published by Shokusho Shoten. The input circuit has an appropriate threshold voltage for determining the input signal level. This causes the input circuit to form an output signal that corresponds to the input signal level and is deemed to be at an appropriate level by the LSI internal circuitry.

The rising and falling speed of the signal supplied to the input circuit is limited by the influence of stray capacitance or parasitic capacitance that may be undesirably coupled to the single signal line between the signal generating means and this input circuit. . As a result, a relatively large delay is avoided between when the input signal is changed and when the output of the input circuit is brought to six levels in response to the input signal.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an input circuit such as an LSI with increased operating speed. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of representative inventions disclosed in this application is as follows.

In other words, an input circuit with a relatively low level threshold and an input circuit with a relatively high level threshold are connected by a reverse circuit, so that when the input signal rises, the input circuit has the low level threshold. Input circuit! ? At the time of falling, the input circuit having the above-mentioned high level threshold is selected.

[Example 1] Examples of the present invention will be specifically described below with reference to the drawings.

FIG. 1A is a circuit diagram showing one embodiment of the present invention. The circuit of this embodiment is composed of input circuits 1 and 2, a switch control circuit 3 as a selection circuit, and a switch section 4. Input circuits 1 and 2 are not limited to MO
It consists of an inverter made of BFKT. The input circuit 1 is made to have a threshold voltage Vth+ at a relatively low level close to the low level of the input signal by appropriately setting the MO8FFXT constituting the input circuit 1 to 7Th%.

In contrast, the input circuit 2 is made to have a relatively high level threshold voltage Vth* close to the 71-level of the input signal. The outputs of the input circuits 1 and 2 are connected to the switches 1 . El, and B2. The switch states of the switches S and B2 are controlled by the switch control circuit 3. Switch control circuit 3
is composed of a hysteresis circuit 5 such as, but not limited to, a known Schmidt circuit, and an inverter v1. Further, the switch control circuit 3 receives an input signal supplied from the input terminal IN and rolls the switches S and St. Hysteresis circuit 5 has two threshold voltages Vths and Vth4. The threshold voltage Vth4 for detecting that the input signal changes from low level to low level is the threshold voltage Vthz of the input circuit 2.
is set to a value larger than . On the other hand, the threshold value Vths for detecting that the input signal is changed from the high level to the low level is made smaller than that of the input circuit 1 by a factor of one. Switch S.

is, the input to the hysteresis circuit 5 is the threshold voltage V't
When it is lower than lx<, it is turned on by the output of the hysteresis circuit 5. Switch S2 is Qui9chi1
3. is turned on in a complementary manner to

FIG. 1B is an operation waveform diagram for explaining the operation of FIG. 1A.

The rise and fall times of the input signal V1n are relatively long due to delays caused by parasitic capacitance and stray capacitance between the signal lines, as shown by the curve VIn in FIG. 1B.

When the input signal v1n rises from the low level to −.1, the output voltage VOI of the input circuit 1 is
As shown by the curve VOI in the figure, the input signal ■1n is the threshold value vt
If you press h+, it will be reversed from no-irrepel to low level. The output voltage VO2 of the input circuit 2 corresponds to the curve vo in FIG. 1B.
, when the input signal Vtn exceeds the threshold value Vtht, it is inverted from the no-y level to the low level. Conversely, when the input signal V1n falls to a low level from the current level, the output voltage VOI of the input circuit 1 is equal to the input signal ■1n.
When the input signal van falls to a level below the threshold value Vth+ JU, the output voltage of the input circuit 2 changes from a low level to a no-level level. changed to.

Output voltage V of the hysteresis circuit 5 forming the switch control circuit 3. I is curve iv in FIG. 1B when the input signal Vln rises. , the input signal V1n is the threshold value Vth
When the level of 4 is exceeded... it changes from high level to low level, and when the input signal Vin falls, the input signal Vln
is the threshold voltage Vths, and the input signal Vin, which is changed to a lower level below
Before the rise of the signal, the signal □ is in the on state, and the switch S2 is in the off state. The output voltage V of the hysteresis circuit 5 is increased by the rise of the input signal v1n. 1 is no.
When the level is inverted from high to low, switch St is turned off and switch 2 is turned on. When the output voltage VQI of the hysteresis circuit 5 is inverted from a low level to a level of 1 due to the fall of the input signal Vin, the switch S
2 is turned off and switch S1 is turned on. In other words, the voltage VOut supplied to the inverter 2 is inverted from high level to low level when the input signal 'V1n reaches the threshold value Vth+ at the rising edge, as shown by the curve Vout in FIG. 1B, and at the falling edge. , Le is inverted from low level to high level when the level is lower than the low value vthzN. The voltage VOut is connected to the output terminal OU via the inverter V2.
TK is supplied.

That is, although not shown, the voltage supplied to the output terminal UT is such that when the input signal V1n rises from the low level to the high level, the input signal Vin becomes the threshold voltage vtb+(7).
When the input signal falls from a high level to a low level, when the input signal Vtn falls to a level below the threshold voltage '7th2JV, it changes from a high level to a low level. . Therefore, the output signal output to the output terminal OUT is
When the input signal vtn rises, it is output when the input signal v1n is at a relatively low level, and when the input signal v1n falls, it is not output when the input signal is at a relatively high level f:r.

[Embodiment 2] FIG. 2A is a circuit diagram showing another example of the present invention.

This example circuit is composed of input circuits 1 and 2 and an output signal forming circuit 6 as a reverse folding circuit.

Like the input circuits 1 and 2 in FIG. 1A, they are constructed from inverters made of MOSFETs and have the same characteristics ν. The output signal forming circuit 6 is composed of a NOR circuit, an AND circuit G2, a circuit BI and S2, and an inverter V. The outputs of input circuits 1 and 2 are connected to switches s, , J
and is supplied to the IJOR circuit G1 and the AND circuit G2, respectively.

Switch 1 is set to 1'! by the output of AND circuit G3. R
When the output of AND circuit G is at a high level, it is turned on. Switches 2, 2 are controlled by the output of the OR circuit GK, and are turned on when the output of the NOR circuit is at a high level.

FIG. 2B is an operational waveform diagram for explaining the operation of FIG. 2A.

The output voltages VOI and v02 of the input circuit "=' t: h + and vth2 are determined by the curve M vn 1 * of FIG. 1B.
■Same as o*. When the outputs of input circuits 1 and 2 supplied to NOR circuit G1 are both low level, NO
The output voltage C+ of the R circuit GI changes as shown by the curve cI in Fig. 2B.
Turn on 2. On the other hand, when the outputs of input circuits 1 and 2 supplied to the AND circuit are both at high level, the output voltage c2 of AND circuit G2 changes from low level 17 to high level as shown by curve C3 in FIG. 2B. Turn on the switch. In addition, the switch S is turned on after the switch SI is turned off until the switch s2 is turned on, and during the period after the switch S2 is turned off and when the switch S1 is turned on.
! and S2 are both off, but the voltage Vout supplied to inverter v2 at this time is maintained at its previous state due to the stray capacitance at the input end of inverter v2. With this, inverter V? When the human input signal v1n rises as shown in the song 1mVou,t in Figure 2B, the voltage Vout supplied to the input signal V1n is inverted from high level to low level when it exceeds the threshold value vthI. When the signal V11 falls below the threshold value Vt
When the level drops to below hz J>J, the low level is changed to the high level.

In other words, although the voltage supplied to the output terminal OUT is not shown, when the input signal v1n rises from a low level to a high level, when the input signal VIH falls below the level of the threshold voltage Vth+, it changes from a low level to a high level. changed,
Conversely, when the human input signal V1n falls from a high level to a low level, the input signal V41 falls.

When the voltage drops to a level below the threshold voltage vth2JxJ, the high level is changed to the low level. Therefore, the output signal output to the output terminal OUT is output when the input signal Vln is at a relatively low level when the human input signal Vin rises, and when the input signal V4n is at a relatively high level when the input signal vIn falls. Output when level.

[Embodiment 3] Figure 3A shows the NOR circuit and AND circuit G! of Figure 2A. Reset on the output side of 1. Tofuri,, puf a, p(
FIG. 12 is a circuit diagram of another embodiment of the present invention using a 3D R8-FF.

The circuit of this embodiment is composed of input circuits 1 and 2 and an output signal forming circuit 7 as a selection circuit.

Input circuits 1 and 2 are similar to the circuits of the previous embodiment.

The output signal forming circuit 7 uses the output side KR8@FA of the NOR circuit and AND circuit in FIG. 2A to generate the output signals Q and Q.

and control the eight senses. Switch 1 is turned on by the output Q of R8-FW when the input voltage 02 supplied to terminal R of R8-FF' is lower than the threshold voltage Vth+. Nuibuti s2 is turned on by the output Q of its Re@FT when the input voltage 01 supplied to the set terminal S of Re@FF is higher than the threshold voltage Vt.

FIG. 3B is an operation waveform diagram for explaining the operation of FIG. 3A.

Output voltage voI of input circuit '7th+ and 'V'thz
and VO, and the output voltage 0. of the NOR circuit and AND circuit. and C-tomi is the song # vo + + in Figure 2B.
Same as vot, C4, and C2. The output of the NOR port circuit is supplied to the set terminal of the Re-FF.

The output of the Al3Ti circuit G is also supplied to the R8/FIFI terminal R. As shown by the curve Q in FIG. 3B, when the input signal v1rI rises, the output voltage of Re -FF is Q multiplied by the voltage Q, and the voltage supplied to the set terminal S is 0. is changed from low level to high level when it is changed from a-level to no-irrepel. Conversely, when the input signal vin falls at 9 o'clock R
8.The output voltage Q of the FF is changed from low level to low level when the electric power EF Ot supplied to the reset terminal R is changed from low level to high level. 8th・IFF output voltage Q.

The state is opposite to that of the output voltage QK. Input signal VIH
Before the rise of , the switch S is turned on and the switch S2 is turned off. When the output voltage Q of R8-FF is changed from a low level to a high level according to the shape of the input signal vln, the switch 1 is turned off,
The switch 81 is turned on. Conversely, input signal ■1n
When the output voltage Q of R8.F'F is changed from a low level to a low level due to the falling of the switch, the switch S is turned off and the switch S is turned on. That is, the output voltage Taut supplied to the inverter V,
As in the song 11j V out in Figure 3B, when the input signal vtn rises, it exceeds the level of the threshold voltage '7th I... it changes from low to low level, and the input signal V 1 n falls. time is the threshold voltage Vtht
The level below u is changed to nine, low level, empty high level, and so on. That is, although the voltage supplied to the output terminal 017T is not shown in the figure, when the input signal 71B rises from a low level to a high level, when the input signal VIH exceeds the level of the threshold voltage V th I, it goes low. It changes from level to no-i level. When the input signal V1n falls from a high level to a low level, when the input signal V1n falls to a level below the threshold voltage Vth*, it changes from a high level to a low level. Therefore, the output terminal O
The output signal output to the UT is output when the input signal 71n rises and the input signal v1n is at a relatively low level, and when the input signal V1n falls, the output signal is output when the input signal is at a relatively high level. be done.

[Embodiment 4] FIG. 4A is a circuit diagram showing still another embodiment of the present invention. The circuit of this embodiment is composed of input circuits 1 and 2 and an output signal forming circuit 9 as a selection circuit. Input circuit 1 and 2 MO8'F1 having the same bamboo structure as each of the above embodiment circuits
It consists of an inverter made of nT. The output signal forming circuit consists of nine output signal forming circuits, a delay circuit 8 consisting of input signals I and 2, a resistor R, and a capacitor C, an inverter IT3, and an inverter IT3.

The outputs of input circuits 1 and 2 are supplied to switches 81 and s2. Switch day! and El, the outputs of the delay circuit 8
The current is supplied to the temporary capacitor C via the resistor MR, and then to the inverter v3. The switch 8□ is controlled by the output of this inverter v3. Further, the output of the inverter MV3 is supplied to the inverter v4, and the switch S is controlled by this output.

FIG. 4B is an operation waveform diagram for explaining the operation of FIG. 4A.

Output voltages VO1 and VO8 of input circuits 1 and 2 are the same as in each of the circuits of the above embodiments. The outputs of input circuits 1 and 2 are supplied to a delay circuit 8. Figure 4B song 1flJ O
o, the output voltage C9 of the delay circuit 8 and the input signal V4
When H is rising ±υ, the input signal v1n is the threshold voltage vth
When it exceeds the + level, it begins to change from high level to low level. When the input signal V'1n falls, the input signal V1n is at the level Kf! which is lower than the threshold voltage Vthz! Lutlow level begins to change to Karahai lepel. The rise and fall times are relatively long due to the delay of the output voltage O6 of the delay circuit 8 and the resistor R capacitor C. The inverter has a threshold voltage V ths approximately at the midpoint for distinguishing between high and low levels of the output voltage co of the delay circuit 8. The output voltage C8 of the inverter v3 is the input signal V4
H's writer's time is curve C in Figure 4! As shown below, the threshold value Vth5JA at the approximate midpoint of the output co of the delay circuit 8 is +7)L.
When the input signal "in" falls, it changes to a high level and a low level when it exceeds the level of the threshold value Vtbs at the approximate midpoint of the output voltage a6 of the delay circuit 8. input signal v1
Before n rises, the switch S1 is turned on and the switch s2 is turned off. When the output voltage C1 of the inverter v3 is changed from the a-level to the high level by the rise of the input signal v1n, the switch 81 is turned off and the switch S2 is turned on. input signal V
1n falls, the output voltage CI of inverter v3
is changed from high level to low level, switch 8
The goose is turned off and switch S is turned on.

In other words, the voltage "Out" supplied to the inverter v2 is changed from high level to a-level when the threshold value vthl is applied at the rising edge of the input signal V1n, as shown in the curve 11i) Vnut in FIG. 4B. At the time of falling, when the level is below the threshold value vthtLJ, it changes from low level to high level.In other words, the voltage supplied to the output terminal OUT is the same as the previous example circuit, although it is not shown in the figure. When the input signal V1n rises from a low level to a high level, when the input signal 711 exceeds the level of the threshold voltage vth+, it changes from a low level to a high level, and the input signal van rises from a high level to 0-. When the input signal V1n falls to a level below the threshold voltage Vthz when the 17th bell falls, the high level is changed to the a- level.Therefore, the output signal output to the output terminal OUT is as follows.
When the input signal V4H rises, it is output when the input signal vtn is at a relatively low level, and when it falls, it is output when the input signal V11 is at a relatively high level.

[Example 5] FIG. 5A is a circuit diagram illustrating an example of the present invention.

The circuit of this embodiment is composed of input circuits 1 and 2 and an output signal forming circuit 10 as a reverse folding circuit.

Input circuits 1 and 2 are composed of inverters made of MO8FFiT having the same characteristics as the circuits of the respective embodiments.

The output signal forming circuit 10 is composed of a NOR circuit Gl, an AND circuit, a T-type flip-flop (referred to as T-FF), and an inverter v5. The output of the input circuit 1 is supplied to a NOR circuit, and the output of the input circuit 2 is supplied to the NOR circuit via an inverter. The outputs of the input circuits 1 and 2 are supplied to the A/ND circuit G. The output of the NOR circuit is supplied to the trigger terminal T of T@FP, and the output of the AND circuit G2 is T@F'
It is supplied to the reset terminal 7'H of F. It is connected to the Q output terminal OUT of T/FF.

FIG. 5B is an operation waveform diagram for explaining the operation of FIG. 5A.

Output voltages of input circuits 1 and 2 ■o1 and vO! is the same as in each of the embodiment circuits described above. The output of the input circuit 1 is supplied as is to the NOR circuit G, the output of the input circuit 2 is supplied to the inverter 5, and its output is supplied to the NOR circuit. The output voltage VO4 of the NOR circuit,
When the input signal vtn rises, the song M V O4 in FIG. 5B is played.
As shown in FIG. be done. When the input signal V1n falls, when the input signal Vin falls below the threshold voltage '7th*, it changes from low level to no level, and when the input signal falls below the threshold voltage Vtht level, it changes to high. changed from level to low level. The output voltage vO6 of the AND circuit G2 is equal to the input signal V at the rising edge of the input signal as shown by the curve Vo5 in FIG. 5B.
11 exceeds the level of the threshold voltage Vthl, it is changed from high level to a-level, and the input signal 'V1n
When the input signal 1n falls below the level of the threshold voltage Vtht, it changes from low level to high level. The T-FF is triggered at the rising edge 9 of the input pulse. Further, when a low level voltage is supplied to the trigger terminal T, the previous state is maintained. That is, the Q of T-PIF
As shown by the curve Vout in FIG. 5B, when the input signal v1n rises, the output voltage changes from the a- level to 1 when the input signal 'Vln exceeds the level of the threshold voltage V't h+.
When the input signal v1n falls below the level of the threshold voltage Vthz, the level is changed from the high level to the low level. Therefore, when the input signal 'V1y) rises, the output signal output to the output terminal OUT is output when the input signal is at a relatively low level, and when the input signal V1n falls, the output signal 'V1y) is output when the input signal 'V1y) is at a relatively low level. Output when the target level is high.

〔effect〕

According to the present invention, the input circuit 1 has a threshold value Vth+ relatively close to the low level, and the input circuit 2 has the threshold value Vth2 relatively close to the high level, so that the input signal rises. By selecting the input circuit 1 when the input signal falls and selecting the input circuit 2 when the input signal falls, the effect of increasing the operating speed can be obtained.

In the embodiment of FIG. 1A, the input signals vj, n are directly supplied to the Nuivuchi control circuit 3, so that the switch control circuit 3 can respond to the input signal Vin at high speed. Therefore, the circuit shown in the figure can receive relatively high-speed input signals.

However, in order to sufficiently lower the level of the threshold voltage Vtb+ and to sufficiently increase the level of the threshold voltages Vt, ht, the threshold voltage Vtha of the hysteresis circuit 5 must be adjusted accordingly. It is necessary to further lower the threshold voltage Vth than the threshold voltage 7th, and to raise the threshold voltage Vtht further higher than the threshold voltage Vthz. Therefore, in such a case, the general calculation of the hysteresis circuit 5 becomes difficult.

In the case of the embodiment shown in FIG. 2A, since the outputs of the input circuits 1 and 2 are used to control the switches S and s2, it is easy to set the threshold voltage.

In the embodiment of FIG. 3A, the period during which switches S and 82 are simultaneously turned off is substantially zero. Accordingly, it is possible to prevent the input of inverter v2 from being left in a floating state. As a result, even if there is undesired coupling capacitance such as stray capacitance that is formed between the input of inverter V2 and the signal wiring (not shown), noise is transmitted to the input of inverter V through the coupling capacitance. You can prevent it from being given to you.

In the case of the embodiment shown in FIG. 4A, the number of elements in the circuit for controlling the nulls St and S2 can be slightly reduced.

The present invention made by Nagisa on the Moon will be specifically described based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without deviating from the gist thereof. Needless to say.

For example, input circuit 1, switch S1 and input circuit? and switch B are each constructed from a CMOS clocked inverter circuit as shown in FIG. In the figure, switches MO8FETQ and Q3 are simultaneously turned on and off by complementary switch signals φ and φ.

The input circuits 1 and 2 may be composed of hysteresis circuits. In this case, even if noise is added to the input signal, the input circuits 1 and 2 are virtually insensitive to the noise added to the input signal due to their hysteresis characteristics.

[Application field]

As is clear from the above Kinmei, according to the present invention, LSI
It can be applied to input circuits inside LSIs that receive signals from outside the L8 factory, etc. The present invention can be applied at least to conditions where it is desired to increase the operating speed.

[Brief explanation of the drawing]

1A, 2A, 3A, 4A, and 5A are circuit diagrams of practical examples of the present invention, respectively. Figures 1B, 2B, 3B, 4B, and 5B correspond to the above circuit diagrams, respectively. 2... Inverter with a high level threshold value, 3... Switch changeover circuit, 4 ...Switch 9 section, 5...Hysteresis circuit, 6.7.9.10...Output signal forming circuit, 8...
・Delay circuit, engineering ■1 to engineering v5...inverter, 81b
``!...Switch% Gl...IJ, OR circuit, G2...AND circuit. Fig. 1A Fig. 1B , -(~; L -1Σ (, (j'i Fig. 5A 1 / θ Fig. 5B'1 Nigomi kt JP-A-59-207735 (9) Fig. 6

Claims (1)

[Claims] 1. a first input circuit having a relatively low threshold voltage; a second input circuit having a relatively high threshold voltage and to which an input signal common to the input signal of the first input circuit is applied;
a selection circuit, wherein the selection circuit selects the first input circuit when the input signal rises and selects the second input circuit when the input signal falls. An input circuit characterized by: