JPS61196614A - Chopper type comparator - Google Patents

Abstract

PURPOSE:To prevent the increase in the power consumption in the initial condition by charging a capacitor and biasing an inverter by the second voltage source in the initial condition and stopping to supply an electric power to the inverter. CONSTITUTION:At first, a switch 6 connected to an input terminal 200 to which a reference voltage Vref is inputted, and a switch 13 connected to a bias voltage source 12 are closed by clock signals phi and -phi, and the switch 5 connected to an input terminal 100 to which an input voltage Vin is inputted, a switch of a pMOSFET 10 to control an electric power supply to a CMOS clocked inverter 20 and a switch of an nMOSFET 11 are opened, and a penetrating electric current of a CMOS clocked inverter 20 is cut off. A capacitor 4 is charged by the voltage which is (Vref-Vbai). When clock signals phi and -phiare inverted, the sampling period of an input voltage Vin is started.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a chopper type comparator, and particularly to a chopper type comparator with low power consumption.

[Prior Art] FIG. 2 is a connection diagram showing the configuration of an example of a conventional chopper type comparator. First, the configuration of this comparator will be explained. In the figure, the chopper type comparator consists of an input switching circuit 1, a CMOS inverter 2, a switch 3 connected in parallel between the input and output of this inverter, and a capacitive coupling of the input switching circuit 1 to the CMOS inverter 2. It consists of a capacitor 4 and an output terminal 9. To explain in more detail, the input switching circuit 1 includes a switch 5 whose one conduction terminal is connected to an input terminal 100 to which an input voltage Van is input, and whose other conduction terminal is connected to a capacitor 4; is connected to an input terminal 200 to which a reference voltage Vref is input, and a switch 6 whose other conductive terminal is connected to a capacitor 4. switch 3.5
．． 6 are semiconductor elements such as MOS field effect transistors. 51.52 is the goo 1 terminal of switch 5, 61.62 is the gate terminal of switch 6, and 31.32 is the gate terminal of switch 3.

Clock signals φ and φ are applied to these gate terminals,
The opening and closing of each of the switches 3, 5, and 6 is controlled by this clock signal. At this time, switch 5 and switch 3.6 open and close in a complementary manner.

The CMOS inverter 2 includes a p-channel MO8 field effect transistor (hereinafter abbreviated as pMO8FET) 7 and an n-channel MO8 field effect transistor (hereinafter nMO8F).
(abbreviated as ET). p MO8FET
One electrode of 2 is at voltage V. Power terminal 13 to which 0 is given
', and the other electrode is connected to one electrode of nMO8FET8. The other electrode of n MO8FET8 is grounded. CMOS inverter 2 and switch 3 are connected to output terminal 9.

Next, the operation of this chopper comparator will be explained.

3 is a diagram showing the input/output characteristics of the CVOS inverter 2. Curve a in the figure is CMOS inverter 2
The relationship between the input voltage (horizontal axis) and the output voltage (vertical axis) is shown.

First, the reference voltage Vy is set by the clock signals φ and φ.
The switch 6 connected to the input terminal 200 to which af is input and the switch 3 connected in parallel between the input and output of the CMOS inverter 2 are closed, and the switch 5 connected to the input terminal 200 to which the input voltage Van is input is closed. open. Here, the switch 3 stabilizes the bias voltage between the input and output of the CMOS inverter 2 in this initial state.

In the above shunt state, CMOS inverter 2
The input and output voltages of will be equal. Therefore, the bias voltage between the input and output of the CMOS inverter 2 in the initial state is the point d (V
l, J, V) is the input and output voltage at J). In addition, in this shunt state, the capacitor 4 is connected to the reference voltage V vtf input via the switch 6 to CM
The above bias voltage V&al of OS inverter 2
will be charged with the voltage minus the

In the above initial state, when each clock signal φ, φ is inverted, switches 6 and 3 are opened, switch 5 is closed, and during the sampling period of the input voltage Van.
enter. During this sampling period, the input voltage vln
is higher or lower than the reference voltage VYe,
The change in the input voltage to the CMOS inverter 2 via the capacitor 4 becomes positive or negative, respectively, and the output voltage level of the CMOS inverter 2 changes from point d in FIG. 3 to O or V. It approaches 0 and enters a certain fixed logic state.

Conventional chopper comparators are constructed as described above, and especially in high-speed A/DI converters, a large number of such chopper comparators are used in parallel to compare the levels of input signals.

[Problems to be Solved by the Invention] However, in the chopper comparator configured as described above, in the initial state, the switch 3 is closed and the CMO
When the input and output of S inverter 2 are shunted,
The input/output voltage of the CMOS inverter 2 becomes the value shown at point d in FIG. 3, and in this state, both the pMO8FET 7 and the nMO3FET 8 constituting the CMOS inverter 2 are turned on. Here, the curve C in Fig. 3 is
D with respect to the input voltage to CMOS inverter 2 (horizontal axis)
This is a curve showing the through current (vertical axis) flowing from MO8FET7 to nMO8FET8. Input/output cashyant status,
In other words, the through current reaches its maximum at point d, as shown in Figure 3, and in high-speed A/D converters that use many such chopper comparators, the power consumption in the initial state, that is, during the shunt period, is extremely low. It had the disadvantage of becoming larger.

This invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a chopper type comparator that can prevent an increase in power consumption in an initial state.

[Means for Solving the Problems] The chopper comparator according to the present invention charges the capacitor and biases the inverter with the second voltage source in an initial state, and does not supply power to the inverter. This is what I did.

[Operation] In the initial state of the present invention, the third switch means connected between the connection point of the capacitor and the inverter and the second voltage source is controlled to close by the clock signal, and The inverter is controlled so that it is not powered by the clock signal.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a connection diagram showing the configuration of a chopper type comparator that is an embodiment of the present invention. First, the configuration of this device will be explained. In the figure, this chopper comparator is
Mainly, the input switching circuit 1, the CMOS clocked inverter 20, the bias supply circuit 30, and the input switching circuit 1
A capacitor 4 capacitively couples the output terminal to the CMOS clocked inverter 20 and the bias supply circuit 30, and an output terminal 9.
It consists of CMOS clocked inverter 20
is the switch l) MO8FET10 and pMO8
FET7, nMO8FET8, and switch n
It is composed of MO8FET11.

One electrode of the pMO8FET 10 is connected to a power supply terminal 13' to which voltage Voo is applied, and the other electrode is connected to EI.
Connected to MO8FET7. nM.

One electrode of the 5FET 11 is connected to the nMO8FET 8, and the other electrode is grounded. 11M08FET
Clock signals φ and φ are applied to the gate electrodes of the MO8FETs 10 and 11, respectively. The opening and closing of the DMO8FETIO switch and the nMO8FET11 switch are respectively controlled by this clock signal, and the electrode supply to the CMOS clocked inverter 20 is controlled by these switches. The bias supply circuit 30 generates a bias voltage 11[1] which generates the voltage V1)at at point d in FIG.
2 and a switch 13 that transmits the potential to the capacitor 4 and CMOS clocked inverter 20. Clock signals φ and φ are applied to gate terminals 131 and 132 of the switch 13, and the opening and closing of the switch 13 is controlled by these clock signals. Switch 13 opens and closes complementary to switch 5.

Next, the operation of this comparator will be explained. First, the clock signals φ and φ close the switch 6 connected to the input terminal 200 to which the reference voltage ■□ef is input, and the switch 13 connected to the bias voltage 1i12.
Input voltage V,. A switch 5 and a CMOS clocked inverter 20 connected to an input terminal 100 into which
The switch of MO8FET10 and the switch of MO8FET11 are connected (here,
The switch 13 connects one end of the capacitor 4 and the input terminal of the CMOS clocked inverter 20 to V at point d in FIG.
"1. It is for biasing to All, p M
In this initial state, the switch of O8FETI O and the switch of MO8FET11 are C at point d in Fig. 3.
This is for blocking the through current of the MOS clocked inverter 20. Also, in this state, capacitor 4 is (
V? , fVb).

In the initial state described above, each clock signal φ.

When φ is reversed, switches 6 and 13 open and switches 5. I) The switch of MO8FET10 and the switch of MO8FET11 are closed, and the input voltage Va
Enters sampling period n. Here, D MO8FE
The switch T10 and the switch 0MO8FET11 are used to supply power to the CMOS clocked inverter 20 during this sampling period to perform normal inversion operation.

During the above-mentioned sampling period, the comparator operates in the same way as a conventional chopper comparator.

In the above embodiment, the chopper type comparator was configured with 0MO8, but the switch may be configured with other switching elements, and the CMOS clocked inverter can also control the power supply to the inverter using a clock signal. If possible, other clocked inverters may be used.

[Effects of the Invention] As described above, according to the present invention, in the initial state, the second voltage source charges the capacitor and biases the inverter, and does not supply power to the inverter. In particular, the power consumption can be significantly reduced in a circuit such as an A/D converter that uses a large number of chopper type comparators in parallel.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing the configuration of a chopper type comparator according to an embodiment of the present invention. FIG. 2 is a connection diagram showing the configuration of a conventional chopper type comparator. FIG. 3 is an input/output characteristic diagram of the CMOS inverter shown in FIG. 2. In the figure, 1 is an input switching circuit, 2 is a CMOS inverter, 20 is a CMOS clocked inverter, 3.5.6
．． 13 is a switch, 4 is a capacitor, 7.10 is a p-channel MO8 field effect transistor, 8.11 is an n-channel MO8 field effect transistor, 9 is an output terminal, 1
2 is a bias voltage source, 13' is a power supply terminal, 30 is a bias supply circuit, 51, 52.61.62, 131.132
is a gate terminal, and 100.200 is an input terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa Yusuke 3cMos4ampery2e+infy#1fLvn Procedural amendment (voluntary) Showa year, month, day 1, case indication Japanese Patent Application No. 60-39600 2, title of invention chopper type comparator 3 , the person who makes the correction 4th generation! Ka Moriya Shiki 5, Detailed explanation of the invention column 6 of the specification subject to amendment, Contents of amendment (1) rpMO8FET2J on page 3, line 19 of the specification
Correct to rpMO8FET7J. (2) “Straight line a” on page 5, line 2 of the specification is “curve a”
Correct to. that's all

Claims (3)

[Claims] (1) a first switch means to which a voltage to be compared is input and controlled by a clock signal; a second switch means to which a reference voltage is input and controlled by the clock signal; an inverter that includes a capacitor, one side of which is connected to the output side of the switching means, and a semiconductor element that is connected to a first voltage source, the input side of which is connected to the other side of the capacitor, and that is controlled by the clock signal; , a chopper comprising: third switch means connected to a connection point between the capacitor and the inverter and controlled by the clock signal; and a second voltage source connected between the third switch means and ground. Type comparator. (2) The chopper type comparator according to claim 1, wherein the voltage value of the second voltage source is set to around 1/2 of the voltage value of the first voltage source. (3) The chopper type comparator according to claim 1, wherein the first, second, and third switch means and the inverter are constructed of CMOS.