CA1215179A - Versatile input circuit for sensing the status of a voltage input over a wide range of voltage levels and waveforms - Google Patents
Versatile input circuit for sensing the status of a voltage input over a wide range of voltage levels and waveformsInfo
- Publication number
- CA1215179A CA1215179A CA000447090A CA447090A CA1215179A CA 1215179 A CA1215179 A CA 1215179A CA 000447090 A CA000447090 A CA 000447090A CA 447090 A CA447090 A CA 447090A CA 1215179 A CA1215179 A CA 1215179A
- Authority
- CA
- Canada
- Prior art keywords
- voltage
- circuit
- signal
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
- G01R19/1658—AC voltage or recurrent signals
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Current Or Voltage (AREA)
- Control By Computers (AREA)
- Electronic Switches (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
An electronic signal conditioning circuit for inputting a wide range of sensed voltage signals of various AC and DC waveforms to a central processing unit of a computer or microprocessor including voltage limiting means such as a zener diode in parallel with a photodiode of an opto coupler and a minimum voltage level activating means for insuring a minimum voltage level is present before activation of the opto coupler. The signal con-ditioning circuit further includes comparator means for processing the output signal of the opto coupler and rectifying means for rectifying any AC sensing means signal input to the signal conditioning circuit.
An electronic signal conditioning circuit for inputting a wide range of sensed voltage signals of various AC and DC waveforms to a central processing unit of a computer or microprocessor including voltage limiting means such as a zener diode in parallel with a photodiode of an opto coupler and a minimum voltage level activating means for insuring a minimum voltage level is present before activation of the opto coupler. The signal con-ditioning circuit further includes comparator means for processing the output signal of the opto coupler and rectifying means for rectifying any AC sensing means signal input to the signal conditioning circuit.
Description
VERSATILE INPUT CIRCUIT FOR SENSING
THE STATUS OF A VOLTAGE INPUT OVER A WIDE
RANGE OF VOLT LEVELS AND W~VEFC)RMS
BACKGROUND OF THE INVENTION
. .
Field of the 'Invention The invention relates generally to electronic circuits and in particular to an input circuit for a central processing unit of a microprocessor or computer Description of the Prior Art:
_.
The signal conditioning circuit interposed between the sensing means and the central processing unit of a microprocessor or computer system is generally referred to in the art as the input card. The input card, which is physically mounted on the input bus interface, was previously sized separately for each expected voltage level of the output of the sensing means which generated the sensed signal. This requires distributors to stock multiple input cards for use with the same controller in order to supply the customer with compatible signal conditioning circuitry for different expected voltage levels of
THE STATUS OF A VOLTAGE INPUT OVER A WIDE
RANGE OF VOLT LEVELS AND W~VEFC)RMS
BACKGROUND OF THE INVENTION
. .
Field of the 'Invention The invention relates generally to electronic circuits and in particular to an input circuit for a central processing unit of a microprocessor or computer Description of the Prior Art:
_.
The signal conditioning circuit interposed between the sensing means and the central processing unit of a microprocessor or computer system is generally referred to in the art as the input card. The input card, which is physically mounted on the input bus interface, was previously sized separately for each expected voltage level of the output of the sensing means which generated the sensed signal. This requires distributors to stock multiple input cards for use with the same controller in order to supply the customer with compatible signal conditioning circuitry for different expected voltage levels of
2 50,741 the sensing means output. Similarly users or customers had to stock multiple input cards if they desired the eon-trial processing unit to have flexibility for different applications. Accordingly it would be desirable to have an input signal conditioning circuit or input card that is compatible with a wide range of input sensed signals for both varying voltage levels and in particular to a wide range of both AC and DC waveforms.
SUMMARY OF THE INVENTION
Briefly the present invention is an electronic signal conditioning circuit for inputting a wide range of sensed voltage signals of various AC and DC waveforms to a central processing unit of a computer or microprocessor.
The input signal conditioning circuit of the invention comprises a first interface means for relaying sensed signals of varying input voltages and waveforms from a sensing means, a second interface means for relaying a signal from the signal conditioning circuit to a central processing unit of a microprocessor or computer controller, a signal conditioning means disposed between the sensing interface means and the input bus interface means for responding to an input signal of the sensing means having AC or DC waveforms over a first predetermined voltage range by generating an output signal having a second predetermined voltage range suitable for inputting to the CPU. The conditioning circuit means includes a voltage limiting means such as for example a zoner diode TRANZORB, or metal oxide varistor placed in parallel with a photo-diode of an opt coupler for clamping the voltage across the photo diode transistor to a predetermined voltage range. The signal conditioning circuit contracted accord-in to the teachings of the invention further includes minimum voltage level activating means for insuring a minimum voltage level is present before activation of the opt coupler. The minimum voltage level activating means includes a predetermined voltage breakdown means such as a zoner diode placed in series with the photo diode of the
SUMMARY OF THE INVENTION
Briefly the present invention is an electronic signal conditioning circuit for inputting a wide range of sensed voltage signals of various AC and DC waveforms to a central processing unit of a computer or microprocessor.
The input signal conditioning circuit of the invention comprises a first interface means for relaying sensed signals of varying input voltages and waveforms from a sensing means, a second interface means for relaying a signal from the signal conditioning circuit to a central processing unit of a microprocessor or computer controller, a signal conditioning means disposed between the sensing interface means and the input bus interface means for responding to an input signal of the sensing means having AC or DC waveforms over a first predetermined voltage range by generating an output signal having a second predetermined voltage range suitable for inputting to the CPU. The conditioning circuit means includes a voltage limiting means such as for example a zoner diode TRANZORB, or metal oxide varistor placed in parallel with a photo-diode of an opt coupler for clamping the voltage across the photo diode transistor to a predetermined voltage range. The signal conditioning circuit contracted accord-in to the teachings of the invention further includes minimum voltage level activating means for insuring a minimum voltage level is present before activation of the opt coupler. The minimum voltage level activating means includes a predetermined voltage breakdown means such as a zoner diode placed in series with the photo diode of the
3 50,741 opt coupler. The signal conditioning circuit according to the teachings of the invention further includes compare atop means for processing the output signal of the opt coupler and rectifying means for rectifying any AC sensing means signal input to the signal conditioning circuit.
BRIEF DESCRIPTION OF HE DRAWING
The invention may be understood and further advantages and uses thereof more readily apparent, when considered in view of the following detailed description of the exemplary embodiment, taken with the accompanying drawing in which:
Figure 1 is a schematic diagram of a signal conditioning circuit constructed according to the teachings of the invention disposed between a sensing means, and the 5 input bus interface to a central processing unit.
DESCRIPTION OF THE PRY ERRED EMBODIMENTS
Referring now to the drawing, Figure 1 thus-trades a signal conditioning circuit 10, constructed according to the teachings of the invention, disposed between the output of a sensing means shown generally at 12 and the input-of an input bus interface shown generally at 14 which input bus interface I is connected to or interfaces with a central processing unit shown generally at 16 of a microprocessor or computer controller. In general signal conditioning circuit lo includes smoothing filter circuit 22, bridge rectifier BRIM voltage condo-toning circuit 26, opt isolating circuit OPT, and come portray circuit 30.
More specifically smoothing filter circuit 22 includes terminals DO, AL, and GOD which are adapted for connection to the high voltage side, low voltage side, and ground of a sensing means such as that shown generally at 12. Terminal OH is connected to one side of resistor Al, with the other side of resistor Al being coupled over conductor 36 to one side of a capacitor C1 and input terminal 38 of bridle rectifier ROY. Terminal AL is connected to one side of resistor R2 with the other side
BRIEF DESCRIPTION OF HE DRAWING
The invention may be understood and further advantages and uses thereof more readily apparent, when considered in view of the following detailed description of the exemplary embodiment, taken with the accompanying drawing in which:
Figure 1 is a schematic diagram of a signal conditioning circuit constructed according to the teachings of the invention disposed between a sensing means, and the 5 input bus interface to a central processing unit.
DESCRIPTION OF THE PRY ERRED EMBODIMENTS
Referring now to the drawing, Figure 1 thus-trades a signal conditioning circuit 10, constructed according to the teachings of the invention, disposed between the output of a sensing means shown generally at 12 and the input-of an input bus interface shown generally at 14 which input bus interface I is connected to or interfaces with a central processing unit shown generally at 16 of a microprocessor or computer controller. In general signal conditioning circuit lo includes smoothing filter circuit 22, bridge rectifier BRIM voltage condo-toning circuit 26, opt isolating circuit OPT, and come portray circuit 30.
More specifically smoothing filter circuit 22 includes terminals DO, AL, and GOD which are adapted for connection to the high voltage side, low voltage side, and ground of a sensing means such as that shown generally at 12. Terminal OH is connected to one side of resistor Al, with the other side of resistor Al being coupled over conductor 36 to one side of a capacitor C1 and input terminal 38 of bridle rectifier ROY. Terminal AL is connected to one side of resistor R2 with the other side
4 50,741 of resistor R2 being coupled over conductor I to one side of capacitor C2 and input terminal 40 of bridge rectifier BRIM The other sides ox capacitor C1 and C2 are coupled over lead 34 to the ground terminal GOD of smoothing filter 22. Smoothing filter 22 functions as a high pass filter to smooth out the waveform of the signal produced by sensing means 12.
Bridge rectifier BRIM includes input terminals 38 and 40, output terminals 42 and 44, and diodes 52, 54, 56, and 58. Input terminal 38 is coupled to the anode terminal of diode 58 and the cathode terminal of diode 56. Input terminal 40 is coupled to the anode terminal ox diode 52 and the cathode terminal of diode 54. Output terminal 42 of bridge rectifier 24 is connected over lead 62 to the cathode terminals of diodes 52 and 58 respectfully.
Likewise output terminal 44 of bridge rectifier BRIM is coupled over lead 64 to the anode terminals of diodes 54 and 56 respectfully. Bridge rectifier BRIM functions to rectify any AC waveforms exiting smoothing filter 22 as shown generally at waveform A into their DC counterpart as shown generally at waveform B. Output terminals 42 and 44 respectfully of bridge rectifier 24 are coupled over leads 62 and 64 respectfully to voltage conditioning circuit 26.
Voltage conditioning circuit 26 includes voltage limiting means Do such as for example the zoner diode Do shown in Figure 1, a MOW varistor, or alternate voltage limiting device coupled in parallel between leads 62 and 64, a series circuit of threshold voltage activation means Do, such as for example the ever diode shown in Figure l or an MOW varistor or other threshold voltage activation means in series with an LED light emitting diode LDl, resistor R3, and the photo diode 74 of opt isolation circuit PI. In particular lead 62 is connected to the cathode of zoner diode Do and one side of resistor R3.
The other side of resistor R3 is connected over lead 66 to the anode side of photo diode 74. The cathode side of photo diode 74 is coupled over lead 68 to the anode side ~0,741 of light emitting diode LDl with the cathode side of light emitting diode LD1 coupled over lead 70 to the cathode terminal of ever diode Do with the anode side of zoner diode Do coupled over lead 64 to the anode side of zoner diode Do. Voltage conditioning circuit 26 functions to clamp the voltage of the signal waveform, exiting from bridge rectifier 24, to a predetermined range of voltage as shown in general by waveform C in Figure 1. This function of the voltage conditioning circuit 26 is provided by the voltage limiting means DIP Voltage conditioning circuit 26 also functions to ensure a minimum voltage level is present before activating the opt isolating circuit 28. This function of voltage conditioning circuit 26 is provided by the threshold voltage activating means Do which may be the zoner diode shown in Figure 1. Voltage conditioning circuit 26 then is input to opt isolation circuit OPT and activates opt isolation circuit OPT by means of the series circuit connection of photo diode 74 which may be for example a light emitting diode or other photo diode.
Opt isolation circuit OPT includes photo diode I and photosensitive transistor 76. Photosensitive transistor 76 is electrically insulated from and photo-coupled to photo diode 74. Opt isolation circuit OPT
functions to electrically isolate comparator circuit 30 from voltage conditioning circuit 26 while responding to a predetermined range of voltage signals through voltage conditioning circuit 26 by generating an output signal having a voltage within a second predetermined range.
The voltage of the second predetermined range output from photosensitive transistor 76 of opt isolation circuit OPT is determined by the value of source 80 of direct current potential represented by a battery in Figure 1 but which may be a bridge rectifier connected to a source of alternating potential, if desired. The post-live terminal of source 80 is coupled over lead 82 to one end of resistor R5, while the negative terminal of source 6 50,741 of direct current potential 80 is coupled over lead 84 to ground. The other side of resistor R5 is coupled over lead 86 to one side of resistor R6 and the collector of photosensitive transistor 76. The other side of resistor R6 is coupled over lead 88 to one side of capacitor C3 while the other side of capacitor C3 is coupled over lead 92 Jo the junction of the emitter of photosensitive tray-sister 76, one side of resistor R4 and ground. The other side of resistor R4 is coupled over lead 94 to the base of photosensitive transistor 76.
Opt isolation circuit OPT functions to generate an output signal having a voltage within a second prude-termined range, denoted by waveform D, in response to an input signal having a voltage over a first predetermined lo range shown generally at waveform C. The ARC filter of resistors R6 and capacitor C3 functions to smooth the output from opt isolation circuit 28 shown generally at waveform D to the waveform shown generally at E. Output signal shown generally by waveform E is input by lead 88 to comparator circuit 30.
In particular lead 88 is coupled to the inverting terminal of comparator Us while the non inverting terminal of comparator Us is coupled over lead 102 to the junction of one side of resistors R10 and R9 respectfully. The other side of resistor R10 is coupled over lead 104 to the output terminal of comparator Us, one side of resistor R11 and terminal 106 of the input bus interface shown goner-ally at 14. The other side of resistor Roll is connected to the positive terminal of a source 112 of direct current potential, represented by a battery in Figure 1 but which may be a bridge rectifier connected to a source of alter-noting potential if desired. The negative terminal of direct current source 112 may be connected to ground.
In operation a proper AC or DC voltage level must be present between terminals OH and AL of signal conditioning circuit 10. For AC waveforms, bridge recta-lien Burl will rectify the AC waveform to its DC equiva-do 7 50,741 lent. Voltage limiting means Do as for example the zenerdiode shown will limit the waveform to its appropriate zoner voltage level. All excess voltage will be dissipated across resistors Al and R2. Smoothing circuit 22, bridge rectifier BRIM and voltage conditioning circuit 26 then function together to clamp a predetermined DC voltage level across zoner diode Do. This DC voltage presence produces a continuous current which flows through the photo diode 74 of opt coupler OPT and the light emitting diode LD1, thereby activating both. Activating the opt coupler OPT, switches photosensitive transistor 76 into saturation. Issue discharges capacitor C3 through resistor R6. When capacitor C3 voltage becomes lower than the reference voltage at the non inverting terminal of compare atop US, the output of comparator US will switch. Finally the input bus interface 14 will relay this message to the CPU 16.
Note that the input voltage to the non inverting terminal of comparator US must be present for the duration of the ARC (resistor R6 and capacitor C3) time constant.
This is an added protection against any noise spikes.
Voltage threshold means which for example as shown in Figure 1 zoner diode Do is used to insure a minimum voltage level is present before activating the opt coupler Owl and the light emitting diode LD1. Resistor R5 is used to charge up capacitor C3 during inactive circuit operation.
Resistor R10 is used to insure that hysteresis will occur, i.e. if the switch point is reached, the feedback through R10 will change the reference slightly to ensure full activation of the output.
Signal conditioning circuit 10 constructed according to the teachings of the invention has advantages over conditioning circuits of the prior art due to its ability to handle a wide range of voltage levels. The voltage limiting means 72 which for example may be zoner diode Do clamps the incoming voltage level to its appear-private zoner voltage and absorbs all excess current which . 8 50,741 is not needed to activate the opt coupler Owl and the light emitting diode LD1. The absence of this voltage clamping means during a varying or switched voltage level would either fail to activate the circuit or destroy several circuit elements. In conclusion what has been disclosed is a unique signal conditioning circuit having a voltage conditioning means for responding to an input signal having a voltage over a first predetermined range by generating an output signal having a voltage within a second predetermined range. The voltage conditioning means further insures that a minimum voltage level is present before generating an input signal to the CPU.
Bridge rectifier BRIM includes input terminals 38 and 40, output terminals 42 and 44, and diodes 52, 54, 56, and 58. Input terminal 38 is coupled to the anode terminal of diode 58 and the cathode terminal of diode 56. Input terminal 40 is coupled to the anode terminal ox diode 52 and the cathode terminal of diode 54. Output terminal 42 of bridge rectifier 24 is connected over lead 62 to the cathode terminals of diodes 52 and 58 respectfully.
Likewise output terminal 44 of bridge rectifier BRIM is coupled over lead 64 to the anode terminals of diodes 54 and 56 respectfully. Bridge rectifier BRIM functions to rectify any AC waveforms exiting smoothing filter 22 as shown generally at waveform A into their DC counterpart as shown generally at waveform B. Output terminals 42 and 44 respectfully of bridge rectifier 24 are coupled over leads 62 and 64 respectfully to voltage conditioning circuit 26.
Voltage conditioning circuit 26 includes voltage limiting means Do such as for example the zoner diode Do shown in Figure 1, a MOW varistor, or alternate voltage limiting device coupled in parallel between leads 62 and 64, a series circuit of threshold voltage activation means Do, such as for example the ever diode shown in Figure l or an MOW varistor or other threshold voltage activation means in series with an LED light emitting diode LDl, resistor R3, and the photo diode 74 of opt isolation circuit PI. In particular lead 62 is connected to the cathode of zoner diode Do and one side of resistor R3.
The other side of resistor R3 is connected over lead 66 to the anode side of photo diode 74. The cathode side of photo diode 74 is coupled over lead 68 to the anode side ~0,741 of light emitting diode LDl with the cathode side of light emitting diode LD1 coupled over lead 70 to the cathode terminal of ever diode Do with the anode side of zoner diode Do coupled over lead 64 to the anode side of zoner diode Do. Voltage conditioning circuit 26 functions to clamp the voltage of the signal waveform, exiting from bridge rectifier 24, to a predetermined range of voltage as shown in general by waveform C in Figure 1. This function of the voltage conditioning circuit 26 is provided by the voltage limiting means DIP Voltage conditioning circuit 26 also functions to ensure a minimum voltage level is present before activating the opt isolating circuit 28. This function of voltage conditioning circuit 26 is provided by the threshold voltage activating means Do which may be the zoner diode shown in Figure 1. Voltage conditioning circuit 26 then is input to opt isolation circuit OPT and activates opt isolation circuit OPT by means of the series circuit connection of photo diode 74 which may be for example a light emitting diode or other photo diode.
Opt isolation circuit OPT includes photo diode I and photosensitive transistor 76. Photosensitive transistor 76 is electrically insulated from and photo-coupled to photo diode 74. Opt isolation circuit OPT
functions to electrically isolate comparator circuit 30 from voltage conditioning circuit 26 while responding to a predetermined range of voltage signals through voltage conditioning circuit 26 by generating an output signal having a voltage within a second predetermined range.
The voltage of the second predetermined range output from photosensitive transistor 76 of opt isolation circuit OPT is determined by the value of source 80 of direct current potential represented by a battery in Figure 1 but which may be a bridge rectifier connected to a source of alternating potential, if desired. The post-live terminal of source 80 is coupled over lead 82 to one end of resistor R5, while the negative terminal of source 6 50,741 of direct current potential 80 is coupled over lead 84 to ground. The other side of resistor R5 is coupled over lead 86 to one side of resistor R6 and the collector of photosensitive transistor 76. The other side of resistor R6 is coupled over lead 88 to one side of capacitor C3 while the other side of capacitor C3 is coupled over lead 92 Jo the junction of the emitter of photosensitive tray-sister 76, one side of resistor R4 and ground. The other side of resistor R4 is coupled over lead 94 to the base of photosensitive transistor 76.
Opt isolation circuit OPT functions to generate an output signal having a voltage within a second prude-termined range, denoted by waveform D, in response to an input signal having a voltage over a first predetermined lo range shown generally at waveform C. The ARC filter of resistors R6 and capacitor C3 functions to smooth the output from opt isolation circuit 28 shown generally at waveform D to the waveform shown generally at E. Output signal shown generally by waveform E is input by lead 88 to comparator circuit 30.
In particular lead 88 is coupled to the inverting terminal of comparator Us while the non inverting terminal of comparator Us is coupled over lead 102 to the junction of one side of resistors R10 and R9 respectfully. The other side of resistor R10 is coupled over lead 104 to the output terminal of comparator Us, one side of resistor R11 and terminal 106 of the input bus interface shown goner-ally at 14. The other side of resistor Roll is connected to the positive terminal of a source 112 of direct current potential, represented by a battery in Figure 1 but which may be a bridge rectifier connected to a source of alter-noting potential if desired. The negative terminal of direct current source 112 may be connected to ground.
In operation a proper AC or DC voltage level must be present between terminals OH and AL of signal conditioning circuit 10. For AC waveforms, bridge recta-lien Burl will rectify the AC waveform to its DC equiva-do 7 50,741 lent. Voltage limiting means Do as for example the zenerdiode shown will limit the waveform to its appropriate zoner voltage level. All excess voltage will be dissipated across resistors Al and R2. Smoothing circuit 22, bridge rectifier BRIM and voltage conditioning circuit 26 then function together to clamp a predetermined DC voltage level across zoner diode Do. This DC voltage presence produces a continuous current which flows through the photo diode 74 of opt coupler OPT and the light emitting diode LD1, thereby activating both. Activating the opt coupler OPT, switches photosensitive transistor 76 into saturation. Issue discharges capacitor C3 through resistor R6. When capacitor C3 voltage becomes lower than the reference voltage at the non inverting terminal of compare atop US, the output of comparator US will switch. Finally the input bus interface 14 will relay this message to the CPU 16.
Note that the input voltage to the non inverting terminal of comparator US must be present for the duration of the ARC (resistor R6 and capacitor C3) time constant.
This is an added protection against any noise spikes.
Voltage threshold means which for example as shown in Figure 1 zoner diode Do is used to insure a minimum voltage level is present before activating the opt coupler Owl and the light emitting diode LD1. Resistor R5 is used to charge up capacitor C3 during inactive circuit operation.
Resistor R10 is used to insure that hysteresis will occur, i.e. if the switch point is reached, the feedback through R10 will change the reference slightly to ensure full activation of the output.
Signal conditioning circuit 10 constructed according to the teachings of the invention has advantages over conditioning circuits of the prior art due to its ability to handle a wide range of voltage levels. The voltage limiting means 72 which for example may be zoner diode Do clamps the incoming voltage level to its appear-private zoner voltage and absorbs all excess current which . 8 50,741 is not needed to activate the opt coupler Owl and the light emitting diode LD1. The absence of this voltage clamping means during a varying or switched voltage level would either fail to activate the circuit or destroy several circuit elements. In conclusion what has been disclosed is a unique signal conditioning circuit having a voltage conditioning means for responding to an input signal having a voltage over a first predetermined range by generating an output signal having a voltage within a second predetermined range. The voltage conditioning means further insures that a minimum voltage level is present before generating an input signal to the CPU.
Claims (2)
1. The electronic signal conditioning circuit for inputting a wide range of input voltage and frequency signals to a central processing unit comprising:
a) first interface means adapted for connection to a sensing means for relaying the output of said sensing means to said signal conditioning circuit;
b) a second interface means for relaying a signal from said signal conditioning circuit to said central process-ing unit;
c) voltage conditioning means disposed between said first interface means and said second interface means which includes a rectifying means for rectifying AC waveforms into their DC counterparts, voltage conditioning means for limiting the voltage to a predetermined value and for activating said electronic circuit only when the voltage exceeds a second predetermined value, input/output isolating means for electri-cally insulating the output of the voltage conditioning means from the balance of said electronic circuit which isolating means includes an opto coupler having a photodiode and a photosensitive transistor and the voltage conditioning means includes voltage limiting means having a predetermined voltage clamping range disposed in parallel with said photodiode of said opto coupler.
a) first interface means adapted for connection to a sensing means for relaying the output of said sensing means to said signal conditioning circuit;
b) a second interface means for relaying a signal from said signal conditioning circuit to said central process-ing unit;
c) voltage conditioning means disposed between said first interface means and said second interface means which includes a rectifying means for rectifying AC waveforms into their DC counterparts, voltage conditioning means for limiting the voltage to a predetermined value and for activating said electronic circuit only when the voltage exceeds a second predetermined value, input/output isolating means for electri-cally insulating the output of the voltage conditioning means from the balance of said electronic circuit which isolating means includes an opto coupler having a photodiode and a photosensitive transistor and the voltage conditioning means includes voltage limiting means having a predetermined voltage clamping range disposed in parallel with said photodiode of said opto coupler.
2. The electronic signal conditioning circuit for inputting a wide range of input voltage and frequency signals to a central processing unit comprising:
a) first interface means adapted for connection to a sensing means for relaying the output of said sensing means to said signal conditioning circuit;
b) a second interface means for relaying a signal from said signal conditioning circuit to said central process-ing unit;
c) voltage conditioning means disposed between said first interface means and said second interface means which includes a rectifying means for rectifying AC waveforms into their DC counterparts, voltage conditioning means for limiting the voltage to a predetermined value and for activating said electronic circuit only when the voltage exceeds a second predetermined value, input/output isolating means for electri-cally insulating the output of the voltage conditioning means from the balance of said electronic circuit which isolating means includes an opto coupler having a photodiode and a photosensitive transistor and the voltage conditioning means includes voltage limiting means having a predetermined voltage clamping range disposed in parallel with said photodiode of said opto coupler and comparator means for generating said output signal having a voltage within said second predetermined range.
a) first interface means adapted for connection to a sensing means for relaying the output of said sensing means to said signal conditioning circuit;
b) a second interface means for relaying a signal from said signal conditioning circuit to said central process-ing unit;
c) voltage conditioning means disposed between said first interface means and said second interface means which includes a rectifying means for rectifying AC waveforms into their DC counterparts, voltage conditioning means for limiting the voltage to a predetermined value and for activating said electronic circuit only when the voltage exceeds a second predetermined value, input/output isolating means for electri-cally insulating the output of the voltage conditioning means from the balance of said electronic circuit which isolating means includes an opto coupler having a photodiode and a photosensitive transistor and the voltage conditioning means includes voltage limiting means having a predetermined voltage clamping range disposed in parallel with said photodiode of said opto coupler and comparator means for generating said output signal having a voltage within said second predetermined range.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47064783A | 1983-02-28 | 1983-02-28 | |
| US470,647 | 1983-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1215179A true CA1215179A (en) | 1986-12-09 |
Family
ID=23868438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000447090A Expired CA1215179A (en) | 1983-02-28 | 1984-02-09 | Versatile input circuit for sensing the status of a voltage input over a wide range of voltage levels and waveforms |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS59167709A (en) |
| CA (1) | CA1215179A (en) |
| DE (1) | DE3406884A1 (en) |
| GB (1) | GB2136233A (en) |
| IT (1) | IT1183712B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61196614A (en) * | 1985-02-26 | 1986-08-30 | Mitsubishi Electric Corp | Chopper type comparator |
| JPS61196172A (en) * | 1985-02-26 | 1986-08-30 | Mitsubishi Electric Corp | Chopper type comparator |
| DE3931063A1 (en) * | 1989-09-14 | 1991-03-28 | Siemens Ag | CIRCUIT ARRANGEMENT FOR MONITORING A POWER SUPPLY DEVICE FOR LOW VOLTAGE |
| WO2002025914A1 (en) * | 2000-09-22 | 2002-03-28 | C.P. Clare Corporation | Method of and system for determining the status of the voltage of a telephone line |
| DE102006030114B4 (en) | 2006-06-28 | 2010-09-09 | Phoenix Contact Gmbh & Co. Kg | Safe input circuit with single-channel I / O connection for the input of a bus participant |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3527986A (en) * | 1967-08-11 | 1970-09-08 | Westinghouse Air Brake Co | Fail-safe electronic circuit arrangement |
| US3801832A (en) * | 1969-06-02 | 1974-04-02 | Philips Corp | Solid-state relay |
| ZA753004B (en) * | 1974-05-30 | 1976-03-31 | Gen Signal Corp | Solid-state fail-safe logic system |
| GB1469374A (en) * | 1975-06-26 | 1977-04-06 | Burroughs Corp | Frequency-doubler circuit |
| US4130764A (en) * | 1977-07-27 | 1978-12-19 | Westinghouse Air Brake Company | Fail-safe or logic circuit |
| US4179629A (en) * | 1977-08-10 | 1979-12-18 | Westinghouse Electric Corp. | Failsafe logic function apparatus |
| US4205344A (en) * | 1978-06-05 | 1980-05-27 | The Grass Valley Group | Special effects memory system |
-
1984
- 1984-02-09 CA CA000447090A patent/CA1215179A/en not_active Expired
- 1984-02-16 GB GB08404130A patent/GB2136233A/en not_active Withdrawn
- 1984-02-23 IT IT41531/84A patent/IT1183712B/en active
- 1984-02-24 JP JP59035082A patent/JPS59167709A/en active Pending
- 1984-02-25 DE DE19843406884 patent/DE3406884A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| GB8404130D0 (en) | 1984-03-21 |
| GB2136233A (en) | 1984-09-12 |
| IT1183712B (en) | 1987-10-22 |
| JPS59167709A (en) | 1984-09-21 |
| DE3406884A1 (en) | 1984-08-30 |
| IT8441531A0 (en) | 1984-02-23 |
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