JPH036124A - Clocked inverter circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction due to the influence of a ground noise from occurring by connecting the drain of a P-channel transistor whose source is connected to a power source to the serial connection part of an N-channel transistor. CONSTITUTION:The drain electrode of the P-channel transistor(TR) Q5 is connected to the connection part of the N-channel TRs Q3 and Q4, and when the TR Q4 is turned off with the '0' of a signal A and a clock signal (phi) goes to '0' and the inverse of (phi) goes to '1', the TRs Q2 and Q3 are turned off, and the TR Q5 is turned on, then, the connection part of the TRs Q3 and Q4 is set at a stable state at a voltage VCC. At this time, a voltage between the gate and the source of the TR Q3 can be prevented from exceeding a threshold value since the drain electrode of the TR Q4 is set at the voltage VCC even when the ground noise occurs, and the TR Q4 is turned on, which prevents the TR from being affected by the ground noise. Therefore, the malfunction due to the ground noise can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clocked inverter circuit in a semiconductor integrated circuit.

[Conventional technology]

FIG. 2 shows an example of a conventional clocked inverter circuit.

Initially, the input signal is "0" and transistor Q1 is on, Q
4 is off, the clock signal φ is "1", and the signal T is rOJ, the transistor Q2 is on, the transistor Q3 is on, the output O becomes the power supply Vcc, and charge is stored in the load capacitor C1.

Next, when the clock signal φ is set to "0" and the signal T is set to rlJ, the output O becomes high impedance.

This is a circuit in which the output signal O can have a high impedance state by turning off the transistor Q2°Q by the clock signals φ and T. Transistor Q2. Qs, Q4
is turned off and the output O is in a high impedance state, and if noise occurs at the ground, which is the source electrode of transistor Q4, N-channel transistor Q3. Due to the change in the gate-source voltage of C4, the transistor Qi
.

C4 is turned on, and the load capacitance C of the output O is discharged, which may cause malfunction.

[Problem to be solved by the invention]

The above-described conventional clocked inverter has a drawback in that when noise occurs at the ground, which is the source electrode of transistor Q, transistors Q i and Q 4 turn on, potentially causing malfunction.

An object of the present invention is to provide a clocked inverter circuit that eliminates such drawbacks and eliminates malfunctions.

[Means to solve the problem]

The configuration of the black and double inverter circuit of the present invention includes a first P-channel transistor whose gate input is a control signal and whose drain is connected to a power supply, and a second P-channel transistor whose gate input is a clock reverse phase signal. are connected in series, the source of the 20th P-channel transistor is a transistor output, a first N-channel transistor whose gate input is the control signal and whose source is grounded, and a second N-channel transistor whose gate input is the clock signal.
N-channel transistors are connected in series, and this second
The drains of the N-channel transistors of the first . It is characterized in that the drain of a third P-channel transistor whose source is connected to a power supply is connected to the series connection portion of the second N-channel transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this embodiment, in order to prevent the conventional circuit from malfunctioning, the drain electrode of the P-channel transistor Q is connected to the connection between the transistors Q 3 and Q-, as shown in Fig. 1, so that the A signal is "0". Transistor Q4 is off, clock φ signal is rOJ, ? When the signal becomes rlJ, transistor Qz
, Qs are turned off, and transistor Qs is turned on, causing transistors Q,,Q.

The connection portion becomes stable at voltage Vcc. At this time, ground noise occurs, and even if transistor Q4 is turned on, the drain electrode of transistor Q is at Vcc voltage, so the voltage between the gate and source of transistor Q does not exceed the threshold value, and transistor Q It does not turn on and is not affected by ground noise.

〔Effect of the invention〕

As explained above, the present invention connects a P-channel transistor to a conventional cross-domain inverter,
This has the effect of preventing malfunctions caused by ground noise.

...Power supply, C1 ...Load capacity, (L+
Qt, Qs...mark P-channel transistor s Q
sp C4...N-channel transistor.

Claims (1)

[Claims] A first P-channel transistor whose gate input is a control signal and whose drain is connected to a power supply, and a second P-channel transistor whose gate input is a clock reverse phase signal are connected in series, and this second P-channel transistor a first N whose source is a transistor output, whose gate input is the control signal and whose source is connected to ground;
A channel type transistor and a second N-channel type transistor whose gate input is a clock signal are connected in series,
A third P-channel transistor whose drain is commonly connected to the output terminal of the second N-channel transistor, and whose source is connected to the power supply at the series connection portion of the first and second N-channel transistors. A clocked inverter circuit characterized by connected drains.