JPH0484517A - Clocked inverter circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction due to the influence of noise of a power supply and ground by connecting a P-channel transistor(TR) and an N-channel TR controlled by a clock signal and its inverted signal to a clocked inverter circuit. CONSTITUTION:P-channel TRs T2, T5 connected in series whose gates receive the inverse of clock signal psi are arranged between the drain of a P-channel TR T1 and an output OUT, and N-channel TRs T3, T7 connected in series whose gates receive a clock signal psi are arranged between a drain of an N- channel TR T4 and the output OUT. Moreover, an N-channel TR T6 whose gate receives the inverse of clock signal psi is arranged between a connecting point of the TRs T5, T2 and a power supply VDD, and a P-channel TR T8 whose gate receives a clock signal psi is arranged between a connecting point of the TRs T7, T4 and the power supply VDD. Thus, the malfunction due to the effect of noise of the power supply and ground is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to clocked inverter circuits.

[Prior Art] As shown in FIG. 2, a conventional clocked inverter circuit has a P-channel transistor T1 whose gate input is a data signal, and a P-channel transistor T2 whose gate input is an inverted clock signal. VDD and output OU
An N-channel transistor T3 whose gate input is a clock signal φ and an N-channel transistor T4 whose gate input is a data signal are connected in series between the output OUT and the ground GND. , and further output OTJT and tl ft+! A load capacitor C is connected between GND and GND. This circuit uses the clock signal φ
, and its reverse phase signal ■, the transistors T2. When T3 is off, the output OUT is in a high impedance state, and is a circuit in which charge is held by the load capacitance C.

[Problems to be Solved by the Invention] In the conventional cocked-in-heart circuit described above, when the input data F) is at a high level, the transistor Tl.

T2. When 'I'3 is turned off and the output OUT is in a high impedance state, if noise occurs in the power supply that is the source input of transistor 'F1, the voltage difference between the gate and source of P-channel transistor T1 causes turns on, which creates a voltage difference between the gate and source of transistor T2, causing transistor T2 to turn on.
By turning on the output 01J T through the route of ■.
There is a possibility that the load capacitance C will be charged and cause malfunction.

Further, when the input data D is at II l=++ level, the transistor T2. T3. T4 turns off and output OUT is 11H
"When in the impedance state, when the ground GNDN which is the source input of transistor T4 occurs, transistor T4 is turned on due to the voltage difference between the gate and source of N-channel transistor T40, thereby increasing the voltage between the gate and source of transistor T3. A difference occurs in the output voltage, and the transistor T3 is also turned on, which causes the load capacitance C of the output OUT to be discharged through the path (2), which may cause malfunction.

As described above, in the conventional clocked inverter circuit, when noise occurs in the power supply, which is the source input of the transistor T1, or the ground GND, which is the source input of the transistor T4, the transistor TI, T2 or the transistor T3. There was a problem that T4 could turn on and cause a malfunction.

[Means for Solving the Problems] The clocked inverter circuit of the present invention includes, in series, a P-channel transistor whose source input is a power source and whose gate input is a data signal, and a P-channel transistor whose gate input is a reverse phase signal of a clock. The drain output of the P-channel transistor is connected to the gate and inputs the reverse phase signal of the clock as the circuit output, while the source input is grounded and the gate input is the data signal.The N-channel transistor whose gate input is the clock signal. In a clocked inverter circuit in which transistors are connected in series and the drain output of an N-channel transistor whose gate is input with a clock signal is used as the circuit output, the P-channel transistor whose gate input is an inverse phase signal of the clock is clocked with both gate inputs. two P-channel transistors arranged in series with opposite phase signals, and the N-channel transistor whose gate input is a clock signal is two N-channel transistors arranged in series whose gate inputs are both clock signals, The drain output of an N-channel transistor whose source input is grounded and whose gate input is a reverse phase signal of the clock is connected to a series connection of two P channel transistors whose gate inputs are reverse phase signals of these clocks. The device is characterized in that the drain output of a P-channel transistor whose source input is a power source and whose gate input is a clock signal is connected to a series connection portion of two N-channel transistors whose gate input is a signal.

C Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a clocked inverter circuit according to an embodiment of the present invention.

Note that the same parts as in the conventional example are given the same reference numerals and redundant explanations will be omitted. In this embodiment, P-channel transistors T2 and T5 are connected in series between the drain of the P-channel transistor T1 and the output OUT, and the gate inputs are both clock inputs having an opposite phase signal f, and the drain of the N-channel transistor T4 is and the output OUT are N-channel transistors T3. and OUT connected in series, both of whose gate inputs are clock signals φ. transistor T7 and transistor T5
．． An N-channel transistor T6 whose gate input is a reverse phase signal T of the clock is connected between the connection point of T2 and the ground GND.
and transistor T? .

A P-channel transistor T8 whose gate input is a clock signal φ is arranged between the connection point of T4 and the power supply VDD. Similar to the conventional circuit, this circuit also has a clock signal φ,
and its reverse phase signal O, the transistor T2. When T3 is off, the output (OUT) is in a high impedance state, and the circuit holds charge by the load capacitance C.

Here, when the input data D is at a high level, the clock signal φ is at the "LIT level," and φ is at a high level, the transistors TI, T2, T3, T5, and T7 are turned off, and T6 and T8 are turned on, and the output (OUT) is in a high impedance state.At this time, when noise occurs in the power supply VDD, which is the source input of the transistor T1, the transistor T1 is turned on due to the voltage difference between the gate and source of the P-channel transistor T1, and the transistor T5 is thereby turned on.
A difference occurs in the voltage between the gate and source of the transistor T
5 is also turned on. However, since the N-channel transistor T6 is on at this time, the source input of the P-channel transistor T2 is in the same state as the ground level, and the influence of the transistor T5, which has been turned on due to the noise of the power supply VDD, is on the transistor T2. Since the transistor T2 remains off, it is not affected by power supply noise.

Further, when the input data D is at a low level, the clock signal φ is at a low level, and T is at a high level, the transistors T2. T
3. T4. T5. T7 is off, T6 and T8 are on, and the output OUT is in a high impedance state. At this time, the ground GND which is the source input of transistor T4
When noise is generated, the transistor T4 is turned on due to the voltage difference between the gate and source of the N-channel transistor T4, which causes a voltage difference between the gate and source of the transistor T7, and the transistor T7 is also turned on. However, at this time, since the P-channel transistor T8 is on, the source of the N-channel transistor T3 is in the same state as the power supply level, and the influence of the transistor T7, which has been turned on due to the noise of the ground GND, is transmitted to the transistor T3. Since the transistor T3 remains off, it is not affected by ground noise.

By connecting two transistors, it has the effect of preventing malfunctions due to the influence of power supply and ground noise.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. D ・ ・ ・ φ・ ・ ・ f ・ ・ OUT ・ VDD ・ GND φ C ・ ・ Data signal, clock signal, reverse phase signal of clock, circuit output, power supply, grounding, load capacitance, [Effects of the invention] As explained above, the present invention includes a clocked inverter circuit that includes a P-channel transistor and an N-channel TI, T2°T5. T8...P-channel transistor, T3゜T4゜-)〇-T6゜]7 ・ ・N-channel transistor,

Claims (1)

[Claims] A P-channel transistor whose source input is a power supply and a gate input which is a data signal is connected in series with a P-channel transistor whose gate input is a reverse phase clock signal, and the drain output of the P channel transistor whose gate input is a reverse phase signal of the clock. is the circuit output, while an N-channel transistor whose source input is grounded and whose gate input is a data signal is connected in series with an N-channel transistor whose gate input is a clock signal, and the drain of the N-channel transistor whose gate inputs the clock signal is connected in series. In a clocked inverter circuit whose output is a circuit output, the P-channel transistor whose gate input is a reverse phase signal of the clock is two P-channel transistors arranged in series whose gate inputs are both reverse phase signals of the clock, The N-channel transistor whose gate input is a clock signal is two N-channel transistors arranged in series whose gate inputs are both clock signals, and two P-channel transistors whose gate inputs are opposite-phase signals of these clocks. Connect the drain output of an N-channel transistor whose source input is grounded and whose gate input is a reverse-phase clock signal to the series connection part, and connect the source to the series connection part of two N-channel transistors whose gate inputs are these clock signals. A clocked inverter circuit characterized in that a drain output of a P-channel transistor is connected, the input being a power source and the gate input being a clock signal.