JPH0358474A - Input protective device of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a surge current from being concentrated and to protect an element against damage when an electrostatic surge is impressed by a method wherein N-type high concentration diffusion regions formed on a first and a second P-type well respectively are connected to an output line which connects an input terminal with an output terminal, and the second P-type well is connected to a ground side or a power source side. CONSTITUTION:A first P-type well 32 and a second P-type well 33 are provided onto an N-type substrate 31. A high concentration N-type diffusion region 34 and a high concentration P-type well contact region 35 are formed on the surface of the first P-type well 32, and a high concentration N-type diffusion region 36 and a high concentration P-type well contact region 37 are formed on the surface of the second P-type well 33. The N-type high concentration diffusion region 34 formed on the first P-type well 32 and the N-type high concentration diffusion region 36 formed on the second P-type well 33 are connected to an output line which connects an input terminal 1 with an output terminal 2, and the second P-type well 33 is connected to a ground side or a power source VDD side. By this setup, a surge current can be prevented from being concentrated when an electrostatic surge is impressed, so that an element can be protected against damage.

Description

DETAILED DESCRIPTION OF THE INVENTION <<Industrial Application Field>> The present invention relates to an input protection device for a semiconductor device that has been improved to increase surge resistance.

<<Prior Art>> As a conventional input protection device of this type, the one shown in FIG. 5 is known.

In the figure, 11 is an N-type substrate on which a CMOS circuit is formed, and on the input side of the N-type substrate 11 is a metal wiring 1 for input.
A resistive high-concentration P-type diffusion region 13 is formed connected to the high-concentration P-type diffusion region 13 and N
A power supply side diode 21 is provided between the mold substrate 11 and the mold substrate 11 .

Further, 12 is a P-type well formed on the N-type substrate 11, and a high concentration N-type diffusion region 1 is provided on the surface of this P-type well 12.
4 and a P-type well contact 15 are formed, and the high concentration N-type diffusion region 14 is connected to the high concentration P-type diffusion region 13 via an output metal wiring 19. is connected to the grounding metal wiring 2o.

Further, 22 is a high concentration N type diffusion region 14 and a P type well 12.
A ground side diode 44 is formed between the P-type well 1
2-based parasitic NPN transistor.

Furthermore, 16 is a field oxide film, 17 is an interlayer insulating film, and an input terminal 1 is connected to an input metal wiring 18, and an output terminal 2 is connected to one output metal wiring.

On the other hand, FIG. 6 shows an equivalent circuit diagram of FIG. 5,
To explain the operation of the input protection circuit shown in FIG. 5 using the same diagram, in this example, when a surge is applied to the input, the surge current flows through the resistive high concentration P type diffusion region 13 and the power supply side. Flows through the diode 21 to the power supply side VDD (
(See arrow A in the figure).

On the other hand, when an e-surge is applied to the input, the surge current flows from the ground side to the input side through the ground side diode 22 and the low resistance high concentration P-type diffusion region 13 (arrow B in the figure).
reference).

<<Problems to be Solved by the Invention>> However, in the conventional input protection device as described in 2.2, in the case of a surge with low output impedance such as an electrostatic surge, the rise of the applied surge Since the current is steep and a large current flows in a short period of time, there are the following problems.

That is, first, when a surge is applied to the input, the surge current flows through the power supply side diode 21 to the power supply side VDD, but since the power supply side diode 21 is formed in a distributed constant manner, a large current flows on the input side. is the power supply side diode 21
There is a problem in that the current flows into the power supply side vDO through the current, causing concentration of current on the input side of the high-concentration P-type diffusion region 13, which tends to cause device destruction.

Furthermore, when an e-surge is applied to the input, the surge current flows from the ground side to the input side through the ground side diode 22 and the resistive high-concentration P-type diffusion region 13; is limited by the high concentration P type diffusion region 13. Therefore, the surge applied voltage at the input of the input protection circuit decreases and exceeds the reverse breakdown voltage of the power supply diode 21, causing a breakdown current to flow through the power supply diode 21. On the other hand, since the power supply side diode 21 is formed in a distributed constant manner as described above, current concentration tends to occur on the input side of the heavily doped P-type diffusion region 13, and the reverse breakdown voltage is It becomes low at the edge part of the losing area 13. For this reason, there is a problem in that current concentration occurs at the input side edge portion of the high-intensity P type diffusion region 13, and the device is likely to be destroyed.

[Object of the Invention] In view of the above-mentioned problems, it is an object of the present invention to provide an input protection device for a semiconductor device that prevents concentration of surge current when an electrostatic surge is applied, and is thereby less likely to cause element destruction. .

(Means for Solving the Problems) In order to achieve the object L, the present invention provides an input protection device for a semiconductor device formed on a semiconductor substrate having an input terminal and an output terminal connected to a semiconductor integrated circuit. two wells formed on the semiconductor substrate with a conductivity type different from the conductivity type of the substrate; and a high concentration diffusion region formed on the surface of each well with the same conductivity type as the semiconductor substrate. The output line connecting the input terminal and the output terminal includes a high concentration diffusion region of the same conductivity type as the semiconductor substrate formed in the first well and a high concentration diffusion region of the same conductivity type as the semiconductor substrate formed in the second well. The conductive type high concentration diffusion region is connected to the second well, and the second well is connected to the ground side or the power source side.

《Explanation of Examples》 The present invention will be explained below based on the drawings.

FIG. 1 shows a cross-sectional structure of an embodiment to which the present invention is applied, and in this example, a first P-type well 32 and a second P-type well 33 are provided on an N-type substrate 31. It is being

Then, a high concentration N type diffusion region 34 and a similarly high concentration P type well contact region 35 are formed on the surface of the first P type well 32, and these are connected to the input/output metal wiring 40.
It is connected to the. In addition, in this first P-type well 32, with the P-type well 32 as a base, an N-type substrate 31,
A first parasitic NPN transistor (bibolar transistor) 42 from the P-type well 32 and the high concentration N-type diffusion region 34
is formed.

On the other hand, on the surface of the second P-type well 33, there is a high concentration N-type diffusion region 36 connected to the human output metal wiring 40 and a high concentration P-type well contact region connected to the grounding metal wiring 41. 37 is formed. Also, this second
In the P-type well 33, a second parasitic NPNI-transistor (bibolar transistor) 44 is formed from the N-type substrate 31, the P-type well 33, and the high concentration N-type diffusion region 36, using the PLY well 33 as a base. In addition, a ground side diode 43 is formed between the high concentration N type diffusion region 36 and the second P type well 33.

Furthermore, in the same figure, 38 is a field oxide film, 39 is a field oxide film, and 39 is a field oxide film.
is an interlayer insulating film. Further, in this example, the input terminal 1 and the output terminal 2 are connected to the input/output river metal wiring 40.

On the other hand, FIG. 2 shows an equivalent circuit diagram of FIG. 1,
The operation of this embodiment will be explained based on the figure.During normal operation, current flows from input terminal 1 to output terminal 2, but when current is applied from the input,
Since the collector and base of the first parasitic NPNI transistor 42 are connected, the transistor 42 is turned on and the surge current flows through the transistor 42 to the power supply side V00. Therefore, in this case, current concentration does not occur (see arrow A in the figure).

On the other hand, when an e-surge is applied from the input, the surge current flows from the ground side to the input through the ground side diode 43 as in the conventional example, but in this example, unlike the conventional example, the surge current flows through the resistive high concentration P-type No diffusion region 13 is provided. Therefore, the flow of current is not restricted. Therefore, current concentration does not occur (see arrow B in the figure).

In this embodiment, as described above, the portions through which the surge current flows are only the forward direction side of the first parasitic NPN} transistor 42 and the ground side diode 43, that is, the second parasitic NPN} transistor 44. Therefore, unlike the conventional example, current concentration does not occur and element destruction does not occur.

In this example, an example of a circuit structure in which a P-type well is formed in an N-type substrate is shown, but an N-type well is formed in a P-type substrate.
In a type of circuit structure in which type wells are formed, P-type and N-type wells may be formed to be opposite to each other, and the polarities of the electrodes may also be reversed.

Next, another example of an input protection circuit that uses a bibolar transistor in the input protection circuit and is configured to eliminate the concentration of surge current when an electrostatic surge is applied, as in the above embodiment, is shown in FIGS. 3 and 4. I will explain. Note that the same reference numerals are given to the same structural members as those used in the above embodiment, and a detailed explanation thereof will be omitted.

By the way, in this example, the difference from the above example is that
The high concentration N type diffusion regions formed in the first P type well 32 are made into four resistive high concentration N type diffusion regions. Therefore, in this example, the high concentration N type diffusion region 49
An input river metal wiring 50 is connected to one side of the
The output metal wiring 51 is connected to the other side, and the output metal wiring 51 is connected to a P well formed in the first P-type well 32.
Type well contact region 35 and second P type well 3
The high concentration N-type diffusion region 36 formed in 3 is connected to the high concentration N type diffusion region 36.

FIG. 4 is an equivalent circuit diagram of the input protection circuit shown in FIG. 3. Next, the operation of this input protection circuit will be explained based on FIG. 4.

First, when a surge is applied, the surge current flows to the power supply side through the first parasitic NPN transistor 42, as in the second embodiment. Therefore, current concentration does not occur.

On the other hand, when an e-surge is applied, the surge current flows from the ground side to the input side through the ground side diode 43 and the resistive high concentration N-type diffusion region 49.

Incidentally, in this case, the surge current is limited by the four heavily doped N-type diffusion regions. Therefore, the design of the ground side diode 43 becomes easy.

On the other hand, since the current is limited as described above, the surge voltage decreases when the input protection circuit is turned on, but since the first parasitic NPN transistor 42 is turned on using the heavily doped N-type diffusion region 49 as an emitter, the voltage is clamped. No current concentration occurs.

(Effects of the Invention) As described above, the input protection circuit according to the present invention is formed on a semiconductor substrate with a conductivity type different from that of the substrate.
Furthermore, on the surface of these wells, a high concentration diffusion region formed of the same conductivity type as the semiconductor substrate mentioned above is provided, and an output line connecting the input terminal and the output terminal is formed in the first well. The high concentration diffusion region of the same conductivity type as the semiconductor substrate formed in the second well is connected to the high concentration diffusion region of the same conductivity type as the semiconductor substrate formed in the second well.
Since the well is configured to be connected to the ground side or the power supply side, it is possible to prevent the concentration of surge current when an electrostatic surge is applied, prevent element destruction due to power concentration, and improve the reliability of the semiconductor device. It has the effect of increasing the

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment to which the present invention is applied, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is another example of an input protection circuit with increased surge resistance. 4 is an equivalent circuit diagram of FIG. 3, FIG. 5 is a sectional view of a conventional input protection circuit, and FIG. 6 is an equivalent circuit diagram of FIG. 1... Input terminal 2... Output terminal 31... N type substrate 32... First P type well 33... Second P type well 34... High concentration N type diffusion region ( (inside the first P-type well)
35...P-type well contact region (inside the first P-type well) 36...High concentration N-type diffusion region (inside the second P-type well)
37... P-type well contact region (inside the second P-type well) 40... Metal wiring for human output 41... Metal wiring for grounding 42... First parasitic NPN} transistor 43... Ground side diode

Claims (1)

[Scope of Claims] 1. In an input protection device for a semiconductor device formed on a semiconductor substrate having an input terminal and an output terminal connected to a semiconductor integrated circuit, an input protection device for a semiconductor device formed on a semiconductor substrate having a conductivity type different from that of the substrate is provided on the semiconductor substrate. It has two wells formed of the same conductivity type and a high concentration diffusion region formed of the same conductivity type as the semiconductor substrate on the surface of each well, and an output line connecting the input terminal and the output terminal. , a high concentration diffusion region of the same conductivity type as the semiconductor substrate formed in the first well and a high concentration diffusion region of the same conductivity type as the semiconductor substrate formed in the second well are connected; An input protection device characterized in that well No. 2 is connected to a ground side or a power supply side.