JPS63313851A - Protective device for mos integrated circuit - Google Patents

Abstract

PURPOSE:To contrive an increase in the efficiency of the title device at low cost by a method wherein the collector and the base of a bipolar transistor formed of a semiconductor substrate, a well region and a diffused layer are connected to the protected part of a MOS integrated circuit. CONSTITUTION:A shallow P-type impurity diffused layer well 13 is provided in an N-type well 9 and a high-concentration N-type diffused region 10 is formed in the well 13. Moreover, a gate poly Si electrode 14 is connected to a low- potential terminal 6 with the aim of isolating the region 10 from a P<+> diffused layer region 8. When a positive static charge is applied to an input terminal 1, for example, against a high-potential terminal 5, the well 13 and the region 10 are forward-biased and minority carriers (electrons) injected in the shallow well 13 are drifted at this time in the strong electric field within the space charge region of the junction between the reverse-biased well 9 and the shallow well 13. That is, a low-impedance path is rapidly formed by a longitudinal bipolar operation and the SiO2 thin film of the part to be protected of a MOS integrated circuit is protected sufficiently.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to integrated circuits using insulated gate field effect transistors, particularly complementary MOS devices (hereinafter referred to as C-MOS).
related to protection devices for inputs, etc.

[Conventional technology]

Various protection devices for resisting electrostatic damage have been put into practical use. Figure 2-4 shows the equivalent circuit of a conventional input protection device of this type (the average shows its cross section). , is connected to the input terminal 7 of the integrated circuit, and is connected to the input terminal 7 of the integrated circuit, the low potential (usually GND) terminal 5 and the high potential (
A first diode 3 and a second diode 4 are respectively provided between the terminal 6 (usually VDD or VCC) to form a protection network.

Next, as shown in FIG.
A mold diffusion region 9 (hereinafter referred to as Herael) is provided,
The N-well 9 is connected to the high-potential terminal 6 through a high-concentration type diffusion region IO gold provided overlapping the substrate 12 and the N-well 9, and a high-concentration P-type diffusion region 8 in the well 9 , and the first diode 4 is formed.

Furthermore, a second diode 3 is formed by a heavily doped Nfi diffusion region 10 in the substrate 1-12, while the substrate 12 is connected to a low potential terminal 5 via a heavily doped P-type diffusion region 8. or.

The surface is partially protected by a selectively formed thick insulation jK11.

Such a protection network depends on the size of the input protection resistor 2, the size of diodes 3 and 4, and the withstand voltage (usually avalanche).
be set appropriately to protect the protected integrated circuits, especially MOSIC-
iIt is protected.

[Problem that the invention seeks to solve]

Next, we will discuss the second problem of the conventional protection network mentioned above.
This will be explained using Figures (C1 and (Di). In Figure 2 (C), the lower horizontal axis represents the size of the input protection resistor 2, and the upper horizontal axis represents the relative ratio of the diffusion layer areas of the protection diodes 3 and 4. The vertical axis shows the electrostatic breakdown voltage.As shown in the figure, to measure the same withstand voltage, increase the resistance value of resistor 2, increase the area of resistor 2 on the IC,
Therefore, an increase in the area of the IC chip cannot be avoided. In addition, there is a case where the resistance value of the resistor 2 cannot be made too large due to the requirement for high speed. FIG. 2 (to) shows the influence of the response speed tD of the diode and the internal resistance Rni of the diode. For example, depending on the response speed tD of the diode and the internal resistance RDi of the diode.

Even if a low clamp voltage is set, a voltage exceeding the intrinsic breakdown withstand capacity of the thin film 8i02 is applied, leading to breakdown.

[Means for solving problems]

The input protection device in the 0MOS device of the present invention has a semiconductor substrate of one conductivity type and a well region of another conductivity type, and a semiconductor diffusion layer of one conductivity type is provided in this well region, thereby forming a vertical bipolar transistor. A protection device for a MOS integrated circuit is obtained in which the base and collector of such a vertical bipolar transistor are connected to an input terminal or the like.

〔Example〕

The invention will now be explained in more detail with reference to one drawing.

FIGS. 1(5) and 1(B) are an equivalent circuit diagram and a structural sectional view of an input protection device showing an embodiment of the invention. In this figure, all the symbols for the same constituent parts are the same as in the above-mentioned FIG. 2.

The embodiment shown in (5) and (B) of FIG. 1 differs from the conventional example shown in FIG.
) is provided. P well 13 is N well 9
Needless to say, it is included in Furthermore, a heavily doped diffusion region 10 is formed in the P-well 13. Furthermore, the gate polysilicon electrode 14 has four diffused layer regions 10 and one diffused layer region 8.
It is connected to the low potential terminal 6 for the purpose of separation from the

The operation of the above structure will be described below, for example, when a positive static charge is applied to the input terminal 1 with respect to the high potential terminal 5I/c. At this time, the P well 13 and the heavily doped diffusion region 10 are forward biased, and the minority carriers (electrons) injected into the shallow P well 13 are reverse biased and transferred to the fcN well 9 and the shallow P well 13. of the junction due to the strong electric field in the charge region. That is, according to this structure, a low impedance path is quickly formed due to the vertical bipolar operation, and the thin film b i 02 of the protected M (J8) is sufficiently protected.

Figure 1 0. (Hitoshi is another embodiment of the present invention. The figure shows N
e, MOf! formed by forming a P-well on a mold substrate. (This is an example of an input protection configuration. Such a C-MOS human protection device has a shallow N with a concentration of about 1×10 cIIL in the deep P well 9.
- the well 13 is formed by means such as ion implantation;
This is the starting point for vertical high-speed bipolar transistors. Particularly, there is a protective effect when an electrostatic charge of θ is applied to the low potential terminal 5.

〔Effect of the invention〕

Next, effects produced by the configuration described in the present invention will be described. First of all, the vertical bipolar transistor of this structure operates at high speed, that is, the effective base width is small, and the emitter area is small, so that the parasitic capacitance (between emitter and paste) and parasitic resistance (inside) is small. Therefore, the response time delay tDni (<tDDi) can be made smaller. Second, the internal equivalent resistance ratio Bi is reduced to about 100Ω. Therefore, the effect of absorbing static charges is greater than in the case of a diode, as shown in FIG. 1 (q).

What is important here is that, for example, in the embodiment shown in FIG. 1, the P-well 13 in the leaky space area.

Boron atom with energy 150 keV and dose L5X
IO (Ion implantation with a thickness of about 1 m) is easily formed by subsequent heat treatment, and there is no need to add any special steps to the standard 0MOS process, making it possible to realize a low-cost, high-performance protection element. Ruru.

As described above, the present invention uses existing processes in combination to provide a high-performance input protection device including a high-speed vertical bipolar transistor at a low cost.

[Brief explanation of drawings]

1ll(5), (B) is an equivalent circuit of an embodiment of the present invention and its sectional view, FIG. 1 (CJ is a graph of transient response characteristics showing the effect of the present invention, FIG. 1(D), ( EJ is an equivalent circuit diagram and its sectional view of another embodiment of the present invention, the second edition. EJ is an equivalent circuit diagram and its sectional diagram of a conventional input protection device, and Figure 2 (C) is a human power protection resistor. and a graph showing the correlation between the area of the diode and the breakdown voltage, Figure 2 (the slope is a graph showing the transient response characteristics of the breakdown voltage of a conventional diode. 1... input terminal, 2... input protection resistor, 3) ... first diode, 4... second diode, low potential terminal, 6... high potential terminal, 7... input terminal of protected IC, 8... 2 diffusion region, 9...N well, 10
...N Asahi scattering region, 11...Thick oxide film, 12...
P type substrate, 13... Shallow P well, 14... Isolation gate polysilicon electrode, 15... Box well, 16...
N-type substrate 15 shallow °C/N-') Figure 2 (B) Figure 2 (C) Figure 2 CD) Diode fl 1 vs. Target!
Compared to a diode mask Diode's response characteristics Yu'i#-)'/8
屓-1,1'-.

Claims (1)

[Claims] Having a well region of an opposite conductivity type in a semiconductor substrate of one conductivity type,
The diffusion layer of one conductivity type is provided in the well region, and the semiconductor substrate, the well region, and the diffusion layer form a bipolar transistor, thereby connecting the collector and base of the bipolar transistor to the protected portion of the MOS integrated circuit. A protection device for a MOS integrated circuit, which is characterized by: