JPH0358027A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the electrolytic corrosion of terminal parts by positioning the tip parts of the terminals for measurement on the inner side of a sealing material. CONSTITUTION:The tip parts of the terminals MT for measurement exist on the inner side of the sealing material SL and the outer edge part of a protective film PSV1 exists on the inner side of the sealing material SL to cover the tips of the terminals MT. Since the outer edges mentioned above do not project to the outer side of a transparent glass substrate SUB2, the distance between the terminals existing on the inner side increases triple fold and the electric field intensity decreases to 1/3. While the wirings are driven by the signals inverted in polarity by each one piece, only he terminals CT for connection exist on the outer side and the potential thereof attains the potential of the same polarity and, therefore, the potential difference can be decreased. The sealing material SL shuts off and protects the tip parts of the terminals MT from external humidity. The outer edges of the protective film PSV1 weakest to the electrolytic corrosion exist on the inner side of the sealing material SL and cover the tip parts of the terminals MT; therefore, the leak current between the terminals is further decreased. The electrolytic corrosion is thereby suppressed.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a liquid crystal display device, and particularly to the structure of a connection terminal and a measurement terminal between a liquid crystal display portion of a liquid crystal display device and an external drive circuit. [Prior Art] For example, an active matrix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Theoretically, the liquid crystal in each pixel is constantly driven (duty ratio 1.0), so the active method has better contrast than the so-called simple matrix method, which uses a time-division drive method, especially in color. It is becoming an indispensable technology. A typical example of a switching element is a thin film transistor (TPT). A liquid crystal display device in which TPT and element electrodes constitute one element of a pixel has a liquid crystal display section (liquid crystal display panel) in which a plurality of pixels are arranged in a matrix. Each pixel of the liquid crystal display section is formed by the intersection of two adjacent scanning signal lines (also referred to as gate signal lines or horizontal signal lines) and two adjacent video signal lines (also referred to as drain signal lines or vertical signal lines). located within the area. The scanning signal lines extend in the column direction (horizontal direction) and are arranged in plural in the row direction (vertical direction). On the other hand, the video signal lines extend in the row direction intersecting the scanning signal lines, and are arranged in plural in the column direction. The liquid crystal display section includes a lower transparent glass substrate on which a thin film transistor, a transparent pixel electrode, a protective film for the thin film transistor, and an alignment film are sequentially provided, a color filter, a protective film for the color filter, a common transparent pixel electrode, and an alignment film are sequentially provided. It consists of an upper transparent glass substrate, a liquid crystal enclosed and sealed between both substrates, and a sealing material that seals the liquid crystal. Active matrix liquid display devices using TPT include, for example, "12.5-inch active matrix color liquid crystal display with redundant structure",
It is known from Nikkei Electronics, pages 193-210, December 15, 1986, published by Nikkei McGraw-Hill. [Problems to be Solved by the Invention] In a conventional liquid crystal display device, among the scanning signal lines and video signal lines formed on the lower transparent glass substrate, the video signal lines are bowed out on both sides of the lower transparent glass substrate. , each end is alternately provided with connection terminals and measurement terminals for checking wiring resistance, disconnections, etc. FIGS. 12(A) and 12(B) are a plan view and a sectional view, respectively, showing the structure of a conventional terminal. Figure 12 (C) is
FIG. 3 is a plan view showing how signal lines are drawn out to both sides of the board, and connection terminals and measurement terminals are alternately provided. SOBl is the lower transparent glass substrate, SUB2 is the upper transparent glass substrate, CT is the connection terminal, MT is the measurement terminal, SL
is the liquid crystal sealing material, and EC is the location where electrolytic corrosion occurs. Also,
In the figure (C), DL is a video signal line and GL is a scanning signal line. Conventionally, by providing the measurement terminal MT, the pitch between the terminals (the pitch between CT and ME) is 172 times the pitch between the connection terminals, and therefore the electric field strength is doubled. In addition, for flickerless operation, adjacent terminals have a phase difference of l8.
◇Adding different signals. This further doubles the potential difference between adjacent terminals. Under these circumstances, in the past, the problem of electrical corrosion due to leakage current between terminals caused by attached water droplets, etc., especially in hot and humid environments, was not considered, and wiring caused by electrical corrosion was not considered. There was a problem with the wire being disconnected. An object of the present invention is to suppress leakage current between terminals and suppress electrolytic corrosion. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] In order to achieve the above-mentioned problems, the liquid crystal display device of the present invention has first and second liquid crystal display devices superimposed at a predetermined interval.
a transparent substrate, a sealing material provided along the periphery between the two substrates, a liquid crystal sealed between the two substrates and sealed by the sealing material, and a plurality of liquid crystals arranged on one of the substrates. A connecting terminal is provided at one end of the wiring and a measuring terminal is provided at the other end, and the connecting terminal and the measuring terminal are arranged in the direction in which the wiring extends. The measuring terminals are arranged alternately in a direction perpendicular to the measuring terminals, and the tips of the measuring terminals are located inside the sealing material. Moreover, the tip of the measurement terminal is covered with a protective film, and the outer edge of the protective film is located inside the sealing material. Figure 1 (A). (B) is a plan view and a sectional view showing an example of the structure of the present invention, respectively. SUB1 is the lower transparent glass substrate, SUB2 is the upper transparent glass substrate, CT is the connection terminal, MT is the measurement terminal, SL
is a liquid crystal sealant, and PSVI is a protective film. The tip of the measurement terminal MT is inside the sealing material SL, and the protective film P
The outer edge of SVI is located inside the sealing material SL, and the protective film PSVI covers the tip of the measurement terminal MT. [Function] Since the tip of the measurement terminal is located inside the sealing material, electrolytic corrosion can be prevented. In other words, the tips of the measurement terminals are inside the sealing material and do not protrude outside the upper transparent glass substrate, so the distance between the terminals on the outside is 3.
The electric field strength is doubled and the electric field strength is reduced to 1/3. In addition, although each wiring is moved with a double sign whose polarity is reversed, there are only connection terminals on the outside, and their potentials have the same polarity, so the potential difference can be further reduced. The sealing material blocks and protects the tip of the measurement terminal from external humidity. In addition, the outer edge of the protective film, which is the part most vulnerable to electrolytic corrosion, is located inside the sealing material, and this protective film covers the tip of the measurement terminal, further reducing leakage current between the terminals. and can suppress electrolytic corrosion. Note that since it has a measurement terminal, it is also possible to measure wiring resistance. [Example] The configuration of the present invention will be explained below along with an example in which the present invention is applied to an active matrix color liquid crystal display device. In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 11 is a partially cutaway plan view of a liquid crystal display module to which the present invention is applied. 5 is an upper shield case, 6 is a lower shield case, 7 is a liquid crystal display window provided in the upper shield case 5, 1 is a liquid crystal display panel attached to the liquid crystal display window 7, and 19 is an FPC for inputting external signals. (Flexible printed wiring board), 18 is a positioning hole, 16 is a rivet, 15
is a hole for a rivet, and 17 is a recess provided in the shield cases 5 and 6 at the rivet attachment part. The upper and lower two shield cases 5 and 6 are combined, and a plurality of rivets 16
and fixed by soldering. 2 is an operation IC for moving the liquid crystal display panel 1, and 3 is a drive IC 2.
TAB (Tape Automated Bonding) is mounted, and 4 is a printed wiring board (Tape Automated Bonding) on which TAB3 is mounted.
P'CB), 9 is a connection terminal (input terminal) of the liquid crystal display panel 1, and is connected to the output terminal of TAB3. FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section taken along the line nB-■B in FIG. 2A and the display panel. FIG. 2C is a cross-sectional view taken along the NC-NC cutting line in FIG. 2A. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged. <Pixel Arrangement> As shown in Figure 2A, each pixel is connected to two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines). Signal line)
Within the intersection area with DL (within the area surrounded by four signal lines)
It is located in Each pixel has a thin film transistor TPT.
Including pixel electrode ITO1 and additional capacitance C add. The scanning signals @GL extend in the column direction, and a plurality of scanning signals @GL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. <Overall Structure of Panel Cross Section> As shown in Figure 2B, a thin film transistor TPT and a transparent pixel electrode ITOI are formed on the lower transparent glass substrate SUBI side with respect to the liquid crystal layer LC, and the upper transparent glass substrate S
On the UB2 side, a color filter FIL and a black matrix pattern BM for shielding light are formed. The lower transparent glass substrate SUB1 side has a thickness of, for example, about 1.1 [mm]. The central part of Figure 2B shows a cross section of one pixel,
The left side shows the left edge part of the transparent glass substrates SUBI and SUB2, and the right side shows the right side edge part of the transparent glass substrates SUBI and SUB2, and each shows a cross section of the part of the external wiring where the measurement terminal is present. There is. The sealing material SL shown on the left and right sides of FIG. 2B is as follows:
It is configured to seal the liquid crystal LC, and is formed along the entire green periphery of the transparent glass substrates SUBI and SUB2 except for the liquid crystal sealing opening (not shown). The sealing material SL is made of, for example, epoxy resin. On the lower transparent glass substrate SUBI, a plurality of video signal lines DL and scanning signal lines GL are arranged in the vertical and horizontal directions corresponding to each pixel (see the equivalent circuit diagram in FIG. 8). One end of each video signal line DL is provided with a connection terminal (not shown, see Figure 1(A)), and the other end is provided with a wiring resistance measurement terminal MT. is video signal line D
They are arranged alternately in the direction perpendicular to the direction in which L extends.
As shown in the figure, the tips of the measurement terminals MT are located inside the sealing material SL and do not protrude outside the upper transparent glass substrate SUB2, so the distance between the terminals (connection terminals) on the outside is The electric field strength is 3 times that of the conventional one, and the electric field strength is 1
/3. In addition, the video signal lines DL are driven by a signal whose polarity is inverted for each line, but since there are only connection terminals on the outside and their potentials are of the same polarity, the potential difference is further reduced. Can be reduced. The sealing material SL shields and protects the tip of the measurement terminal MT from external humidity. Further, the outer edge of the protective film PSV1, which is the most vulnerable part to electrolytic corrosion, is located inside the sealing material SL, and this protective film PSV
Since the tip of the measurement terminal MT is covered with I, the leakage current between the terminals can be further reduced. Therefore, electrolytic corrosion can be prevented between adjacent measurement terminals, and since the outer connection terminals have the same polarity potential and are separated by a large distance, electrolytic corrosion can be suppressed. Note that since the measuring terminal MT is provided, it is possible to measure the wiring resistance of the video signal line DL and check for disconnection before assembling the lower transparent glass substrate SUBI and the upper transparent glass substrate SUB2. The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate SUBZ is connected at least in one place to an external lead wiring formed on the side of the lower transparent glass substrate SBI by a silver paste material SIL. This external lead wiring is formed in the same manufacturing process as each of the gate electrode GT, source electrode SD1, and drain electrode SD2 described above. Orientation films ORII and ORI2, transparent pixel electrode TO, common transparent pixel electrode ITO, protective films PSVI and PSV2,
[Each layer of GI is formed inside the sealing material SL. The polarizing plate POL has a lower transparent glass substrate SUB
I and the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is sealed between a lower alignment film ORII and an upper alignment film ORI2 that set the orientation of liquid crystal molecules, and is sealed by a sealing part SL. The lower alignment film ORII is formed on the protective film PSVI on the lower transparent glass substrate SUB1 side. Upper transparent glass substrate S
On the inner surface (liquid crystal side) of UB2, a light shielding film BM, a color filter FIL, a protective film PSV2, a common transparent pixel electrode (COM) IT02, and an upper alignment film ORI2 are sequentially laminated. This liquid crystal display device has a lower transparent glass substrate SUBl side,
Each layer on the upper transparent glass substrate SUBZ side is formed separately, and then the upper and lower transparent glass substrates SUB1 and SUB2 are formed.
It is assembled by overlapping the two and sealing the liquid crystal LC between them. <Thin Film Transistor TFT> The thin film transistor TPT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large. The thin film transistor TPT of each pixel has three
It is divided into two (multiple) thin film transistors (divided thin film transistors) TFTI, TFT2, and TFT3. Each of the thin film transistors TFTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPTI to TFT3 mainly has a gate electrode GT, a gate insulator [1iGI
, an i-type (intrinsic, not doped with conductivity type determining impurities) amorphous Si semiconductor layer As, and a pair of source electrode SD1 and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following explanation, for convenience, one side will be fixed as the source and the other as the drain. 《
Gate electrode GT> As shown in detail in FIG. 4 (a plan view depicting only the layers g1, g2, and As in FIG. 2A), the gate electrode GT is arranged vertically from the scanning signal line GL (in FIG. 2A and FIG. 2A). It is structured in a shape that protrudes upward (in Fig. 4) (branched into a T-shape). The gate electrode GT is configured to protrude to the shape region of each of the thin film transistors TPTI to TFT3. Thin film transistor TPT1~TF
The respective gate electrodes GT of T3 are formed integrally (as a common gate electrode) and are formed continuously to the scanning signal line OL. The gate electrode GT is composed of a single-layer first conductive film g1 so as not to form a large step in a certain region of the thin film transistor TFTO type. The first conductive film g1 is formed using, for example, a chromium (Cr) film formed by sputtering, and is formed to a thickness of about 1000 [A]. As shown in FIGS. 2A, 2B, and 4, the gate electrode GT is shaped to be thicker than the semiconductor layer As (as viewed from below) so as to completely cover the semiconductor layer As. Therefore, when a backlight BL such as a fluorescent lamp is attached below the substrate SUBI, the opaque Cr gate electrode GT casts a shadow, and the semiconductor layer AS is not illuminated by the backlight.
A conductive phenomenon, that is, deterioration of the off-characteristics of TPT due to light irradiation becomes less likely to occur. The original size of the gate electrode GT is the minimum width required to span between the source/drain electrodes SDI and SD2 (including the alignment margin between the gate electrode and the source/drain electrodes), and the channel width. W
The depth length that determines the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance gm, is determined by the ratio. The size of the gate electrode in this embodiment is of course larger than the original size mentioned above. Considering only the function of the gate and light shielding of the gate electrode GT, the gate electrode and its arrangement i11GL may be integrally formed in a single layer, and in this case, Si-containing At, Pure Al. and A1 containing Pd. <<Scanning Signal Line GL>> The scanning signal line GL is composed of a composite film including a first conductive film g1 and a second conductive film g2 provided on the first conductive film g1. The first conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally constructed. Second conductive MA g 2
For example, sputtered aluminum (Af
i) Using a film, form the film to a thickness of about 2,000 to 4,000 CA. The second conductive film g2 is designed to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (improve the writing characteristics of pixel information). Further, in the scanning signal line GL, the width of the second conductive film g2 is made smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gradual step shape on its side wall. <Gate Insulating Film aX> The insulating film GI is used as a gate insulating film for each of the thin film transistors TPTI to TFT3. Zetsuryokumei G Engineering is
It is formed in the upper layer of the gate electrode GT and the scanning signal line GL. The insulating film GI is formed using, for example, a silicon nitride film formed by plasma CVD to a thickness of about 3000 [A]. <Semiconductor Layer As> As shown in FIG. 4, the i-type semiconductor layer AS is used as a channel type region of each of the plurality of thin film transistors TPTI to TFT3. The i-type semiconductor layer As is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of about 1800 [A]. This i-type semiconductor layer AS is made of Si by changing the supply gas.
,N. Continuing with the shaping of the gate insulating film GI, it is shaped using the same plasma CVD equipment without being exposed to the outside from the equipment. Also, P for ohmic contact
A doped N" layer do (FIG. 2B) is similarly formed continuously to a thickness of approximately 400 μm. After that, the lower substrate SUB1 is taken out from the cVD apparatus and is processed by photoprocessing technology. , N+ layer DO and i layer AS are shown in FIGS. 2A and 2B.
It is patterned into independent islands as shown in Figures and Figure 4. As shown in detail in FIGS. 2A and 4, the i-type semiconductor layer AS is located at the intersection of the scanning signal line GL and the video signal line DL (
It is also provided between the two (crossover section). This intersection i-type semiconductor IAs is connected to the scanning signal line G at the intersection.
It is designed to reduce short circuits between L and the video signal line DL. <<Source/drain electrodes SD1, SD2:) The respective source electrodes SD1 and drain electrodes SD2 of the thin film transistors TPTI to TFT3 divided into a plurality of parts are shown in FIG. 2A,
As shown in detail in FIGS. 2B and 5 (a plan view depicting only the layers d1 to d3 in FIG. 2A), they are provided separately on the semiconductor layer AS. Each of the source electrode SD1 and the drain electrode SD2 is N+
The first conductive film di
．． The second conductive film d2 and the third conductive film d3 are sequentially stacked on top of each other. the first conductive film d1 of the source electrode SDI;
The second conductive film d2 and the third conductive film d3 are the drain electrode S
They are formed in the same manufacturing process as each of D2. The first conductive film di is a chromium film formed by sputtering, and has a film thickness of 500 to 1000 [λ (in this example, 60
0 [film thickness of about λ]. The thicker the chromium film, the greater the stress.
The thickness of the film does not exceed that of a human. The chromium film has good contact with the N0 type semiconductor JildO. The chromium film has a second conductivity [d2, which will be described later, to prevent aluminum from diffusing into the N+ type semiconductor layer do.
In addition to the chromium film, the first conductive film d1 constituting the so-called Paris 7 layer includes a high melting point metal (MotTLTa-W) film,
Refractory metal silicide (MoSi, , TiSi, , Ta
It may also be formed using a Si, WSi, ) film. After patterning the first conductive film d1 by photo processing, the N+ layer dO is removed using the same photo processing mask or using the first conductive film d1 as a mask. In other words, the portions of the N+ layer do remaining on the i MAS other than the first conductive film d1 are removed by the self-alignment. At this time, since the N" layer do is etched so that its entire thickness is removed, the i layer As is also slightly etched on its surface, but the extent can be controlled by the etching time. 2 conductive film d2 is formed by aluminum sputtering to a film thickness of 3000 to 4000 [A] (in this example, a film thickness of about 3000 [λ]).The aluminum film is more susceptible to stress than the chromium film. The second conductive film d2 is made of aluminum.The second conductive film d2 is made of aluminum. In addition to the film, an aluminum film containing silicon (Si) or copper (Cu) as an additive may be formed.After the second conductive film d2 is patterned by photoprocessing technology, the third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-T) formed by sputtering.
from in-Oxide ITO: Nesa membrane),
1000 to 2000 [human film thickness (in this example, 1
200 (film thickness about A)). This third
The conductor 1ld3 is a source electrode SDI, a drain electrode SD
2 and a video signal line DL, and also constitutes a transparent pixel electrode ITOI. First conductive film d1 of source electrode SD1, drain electrode SD
Each of the first conductive films di of No. 2 extends further inside (into the channel region) than the upper second conductive film d2 and the third conductive film d3. In other words, the first conductive film di in these parts is /l
d2. The configuration is such that the gate length L of the thin film transistor TPT can be defined independently of d3. As described above, the source electrode SDI is connected to the transparent pixel electrode IT.
Connected to OI. The source electrode SDI has a step shape of the i-type semiconductor layer AS (a step corresponding to the sum of the thickness of the first conductive W1 film g1, the thickness of the N+ layer do, and the thickness of the i-type semiconductor layer As). It is structured according to the following. Specifically, the source electrode SDI includes a first conductive film d1 formed along the step shape of the i-type semiconductor layer As, and a transparent pixel electrode iITO1 connected to the upper part of the first conductive film d1. a second conductive film d2 whose side is smaller in size;
Ifi is established between the third conductive film d3 connected to the l-th conductive film d1 exposed from the second conductive film. Source electrode S
The second conductive film d2 of DI cannot be formed thickly because the chromium film of the first conductive film di cannot be formed thickly due to increased stress, and the i-type semiconductor layer AS
Since the step shape cannot be overcome, the structure is designed to overcome this i-type semiconductor layer As. In other words, the second
The conductive film d2 is thick and shaped to improve the stepping force barrier. Since the second conductive film d2 can be formed thickly, it greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). Since the third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer AS of the second conductive film d2, the first conductive film d1 is exposed by reducing the size of the second conductive film d2. is configured to connect to. The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connecting portion between them, so that they can be reliably connected. <Pixel Electrode I To 1> The transparent pixel electrode ITOI is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode IT○1 is divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of the thin film transistors TPTI to TFT3 divided into a plurality of pixels. The transparent pixel electrodes E1 to E3 are each connected to the source electrode SD1 of the thin film transistor TPT. Each of the transparent pixel electrodes E1 to E3 is patterned to have substantially the same area. In this way, by dividing the thin film transistor TPT of one pixel into a plurality of thin film transistors TPTI to TFT3, and connecting each of the plurality of divided transparent pixel electrodes El-E3 to each of the plurality of divided thin film transistors TPTI to TFT3. , a divided portion (e.g. TF
Even if T1) becomes a point defect, it is no longer a point defect when looking at the entire pixel (TFT2 and TFT3 are not defective), so
The probability of point defects can be reduced, and defects can be made difficult to see. Further, by configuring each of the divided transparent pixel electrodes E1 to E3 of the pixel to have substantially the same area, each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode ITO2 can be separated. The liquid crystal capacitance (Cpix) can be made uniform. <<Protective Film PSV1> A protective vAPsVI is provided over the thin film transistor TPT and the transparent pixel electrode IT○1. Protective film PSV
I is mainly used to protect the thin film transistor TPT from moisture, etc., and a material having high transparency and good moisture resistance is used. The protective film PSVI is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a film thickness of 8000 [
Formed with a film thickness of approximately A. <<Light-shielding film BM>> On the upper substrate SUB2 side, a shielding film BM fJ<
The pattern is as shown in the hunting pattern in FIG. Note that FIG. 6 is a plan view depicting only the ITO film layer d3, filter layer FIL, and light shielding film BM in FIG. 2A. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film that has a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300 [A]. Therefore, the common semiconductor layer AS of TPTI-3 is made into a sandwich by the upper and lower light shielding films BM and the large gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding film BM is shaped around the pixel as shown by the hatched area in FIG. 6, that is, the light shielding film BM is shaped like a grid (black matrix).
The effective display area of one pixel is partitioned by this grid. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM has two functions: shielding the semiconductor layer As from light and serving as a black matrix. In addition, attach the pack light to the SUB2 side and
@: Il! It can also be set to the opposite side (externally exposed side). <<Common electrode ITO2)) The common transparent pixel electrode IT○2 is connected to the lower transparent glass substrate SU
Opposing the transparent pixel electrode ITOI provided for each pixel on the BI side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode ITO1 and the common electrode ITOZ. This common transparent pixel electrode ITO2 has a common voltage V c
It is configured so that ow is applied. Common voltage V
cow is a low-level fighting voltage V d win and a high-level fighting voltage V d applied to the video signal line DL.
This is the intermediate potential between wax and wax. <<Color Filter FIL> The color filter FIL is constructed by coloring a dyed base material made of a resin material such as an acrylic resin with a dye. The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (Fig. 7), and is dyed differently (Fig. 7 shows the third conductive film layer d3 in Fig. 3 and the color filter, IFIL). (The R, G, and B filters are each 45' 135° with cross hatching). As shown in FIG. 6, the color filter FIL has a thick shape so as to cover all of the pixel electrodes ITOI (El to E3), and the light shielding film BM is formed between the color filter FIL and the edge portion of the pixel electrode IT○1. They are formed inside the peripheral edge of the pixel electrode IT○1 so as to overlap with each other. Color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter shaped area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps. The protective film PSV2 is provided to prevent the dyes used to dye the color filters FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of, for example, a transparent resin material such as acrylic resin or epoxy resin. <<Pixel Arrangement>> As shown in FIGS. 3 and 7, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal line GL extends, and are arranged in pixel columns Xi, X2, X3. , X4,... Each pixel row X1, X2, X3, X4
, . . . each pixel is a thin film transistor TFTI~
The TFT 3 and the transparent pixel electrodes E1 to E3 are arranged in the same position. In other words, odd pixel columns Xi, X3,...
・Each pixel is a thin film transistor TPT1 to TFT.
The transparent pixel electrodes E1 to E3 are arranged on the left side, and the transparent pixel electrodes E1 to E3 are arranged on the right side. Odd pixel rows Xi, X3,...
・Adjacent even-numbered pixel columns X2, X4, . . . in the row direction
Each pixel is formed by inverting each pixel of the odd-numbered pixel columns Xi, X3, . . . symmetrically with respect to the extending direction of the video signal line DL. That is, in each pixel of the pixel columns X2, X4, . Then, each pixel in the pixel rows X2, X4,...
Each pixel in the pixel columns Xi, X3, . . . is shifted (shifted) by half a pixel interval in the column direction.
In other words, if each pixel interval of pixel row X is 1.0 (1.0 pitch), then the next pixel row 0.5 pixel interval (
0.5 pitch) shifted. The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X. As a result, as shown in FIG. 7, a pixel on which a predetermined color filter is formed in the previous pixel row The pixels on which the same color filter is formed (for example, the pixel on which the red filter R of pixel row X4 is formed) are separated by 1.5 pixel intervals (1.5 pitch), and the RGB color filter FIL is It will be a triangular arrangement. Color filter FIL
The RGB triangular arrangement structure can improve the mixing of each color, so it can improve the resolution of color images. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. <<Equivalent circuit of entire display panel>> The equivalent circuit of this liquid crystal display device is shown in Figure 8. XiG
, Xi+IG,... is iI where the green filter G is applied! This is the video signal line DL connected to il. XiB
, Xi+IB, . . . are video signal lines DL connected to the iI element on which the blue filter B is applied. Xi+IR
, Xi+2R, . . . are video signal lines DL connected to the pixels on which the red filter R is applied. These video signal lines DL are alternately drawn out to both sides and selected by two video signal driving circuits. Yi is a scanning signal line OL that selects the pixel column X1 shown in FIGS. 3 and 7. Similarly, each of Yi+1, Yi+2, . . .
This is a scanning signal line GL that selects each of X3, . These scanning signal lines GL are connected to a vertical scanning circuit, Cadd indicates an additional capacitance, and Vcom indicates a common voltage. <Structure of additional capacitance C add> Each of the transparent pixel electrodes E1 to E3 is a thin film transistor T.
At the end opposite to the end connected to PT, it is bent into an L-shape so as to overlap the adjacent scanning signal line GL. As is clear from FIG. 2C, this superposition is such that each of the transparent pixel electrodes E1 to E3 is connected to one electrode PL.
2, and a storage capacitor element (electrostatic capacitor element) Cadd is constructed in which the adjacent scanning signal line OL is the other electrode PLI. The dielectric film of this storage capacitor element C add is an insulating film G used as a gate insulating film of the thin film transistor TPT.
It is composed of the same layer as I. As is clear from FIG. 4, the holding capacitance C add is
It is formed in the part where the width of the first layer g1 of the gate line GL is widened. Note that the layer g1 in the portion intersecting with the drain line DL
is thinned to reduce the probability of shorting with the drain line. Similar to the source electrode SDI, a portion between the capacitor electrode line (g1) and each of the transparent pixel electrodes E1 to E3 that are overlapped to form the storage capacitor element Cadd is provided with In order to prevent the transparent pixel electrode ITOI from being disconnected, an island region is provided which is constituted by the first conductive film di and the second conductive film d2. This island area is transparent ii
The area (aperture ratio) of the i*den FAXT01 should be made as small as possible without decreasing its area (aperture ratio). <<Equivalent circuit of additional capacitance C add and its operation>> The equivalent circuit of the pixel shown in Fig. 2A is shown in Fig. 9. In FIG. 9, Cgs is the gate electrode G of the thin film transistor TPT.
This is a parasitic capacitance formed between T and the source electrode SDI. The dielectric film of the parasitic capacitance Cgs is an insulating film GI. C
pix is the liquid crystal capacitance formed between the transparent pixel electrode ITOI (FIX) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitor tcpix is the liquid crystal LC, protection [
These are PSV1 and alignment films ORII and ORI2. Vlc
is the midpoint potential. The storage capacitor element C add functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TFT switches. Expressing this situation with the formula, ΔV lc = ((Cgs/ (Cgs+Cadd
+Cpix)) XΔWg. Here, ΔVlc is Δ
It represents the change in midpoint potential due to Vg. This change ΔV
lc is a cause of direct current applied to the liquid crystal, but the thicker the holding capacitance Cadd, the smaller its value can be. In addition, the holding capacitance C add has the effect of lengthening the discharge time. Stores video information for a long time after TPT is turned off. A certain reduction in the direct current applied to the liquid crystal LC is
It is possible to improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens. As mentioned above, since the gate electrode GT is made large enough to completely cover the semiconductor layer AS, the overlapping area with the source/drain electrodes SD1 and SD2 increases, and therefore the parasitic capacitance Cgs increases and the midpoint potential Vlc is the gate (
This has the opposite effect of becoming more susceptible to the influence of the scanning signal Vg. However, this disadvantage can also be eliminated by providing the holding capacitor C add. The storage capacitance of the storage capacitance element C add is 4 to 8 times (4.
Cpix<Cadd<8・Cpix), superposition capacitance C
8 to 32 times that of gs (LCgs<Cadd<32・
Cgs). <Connection method of additional capacitance C add electrode line> As shown in FIG. Vcom) Connect to ITO2. As shown in FIG. 2B, the common transparent pixel electrode ITO2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Moreover, some of the conductive layers (gl and g2) of this external lead wiring are constructed in the same manufacturing process as the scanning signal line GL. As a result, the final stage capacitor electrode line GL can be easily connected to the common transparent pixel electrode IT○2. Alternatively, as shown by the dotted line in FIG. 8, the capacitor electrode line GL at the final stage (first stage) may be connected to the scanning signal line GL at the first stage (last stage). Note that this connection can be made using internal wiring within the liquid crystal display section or external wiring. <DC cancellation by additional capacitance C add scanning signal> This liquid crystal display device uses the DC cancellation method (DC
As shown in FIG. 10 (time chart), the DC component applied to the liquid crystal LC can be further reduced by controlling the drive voltage of the scanning signal line DL. In FIG. 10, vi is the drive voltage of an arbitrary scanning signal line OL, and Vi+1 is the drive voltage of the scanning signal line GL at the next stage. Vea is a low-level drive voltage Vdmin. applied to the scanning compensation line GL. Vdd is a high-level drive voltage V d applied to the scanning signal @GL
It is wax. The voltage changes Δ■ and Δv4 of the midpoint potential Vie (see FIG. 9) at each time 1=1 and t4 are as follows. 1=1, :ΔVz=−(C
gs/C) -V2t-tz: ΔV*
=+ (Cgs/C) {V 1 + V 2 )
−(Cadd/C)・V 2 1=1, :ΔV3=−(Cgs/C)”V1+(Cad
d/C)・(V1+V2) 1=14:ΔV4=(Cadd/C)・V1 However, total capacitance of pixels: C=Cgs+Cpix+Cadd Here, if the collapsing voltage applied to the scanning signal line GL is sufficient (see below)

〔Effect of the invention〕

As described above, according to the present invention, electrical corrosion of the terminal portion can be prevented, so reliability can be improved. Further, since the conventional terminal cleaning process and resin coating process for protecting the terminal parts can be omitted, there is also an effect of cost reduction.

[Brief explanation of drawings]

FIGS. 1(A) and (B) are a plan view and a sectional view showing an example of the structure of the present invention, respectively. FIG. 2A is an active matrix color liquid crystal display device which is Embodiment 2 of the present invention. FIG. 2B is a sectional view of the portion taken along the nB-IIB cutting line in FIG. 2A and the vicinity of the sealing part; FIG.
FIG. 3 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2A are arranged; FIGS. 7 is a plan view depicting only a predetermined layer of the pixel shown in FIG. FIG. 9 is an equivalent circuit diagram showing the liquid crystal display section of a matrix type color liquid crystal display device.
Figure A is an equivalent circuit diagram of the pixel shown in Figure 10. Figure 10 is a time chart diagram showing the driving voltage of the scanning signal line using the DC cancellation method. Figure 11 is an example of a liquid crystal display module to which the present invention is applied. FIGS. 12(A) and 12(B) are a plan view and a sectional view showing the structure of a conventional terminal, respectively. FIG. 12(C) is a partially cutaway plan view, with signal lines drawn out to both sides of the board.
It is a top view which shows a mode that the connection terminal and the measurement terminal are provided alternately. In the figure, SUBI, 2...transparent glass substrate. CT...
Connection terminal, MT...measurement terminal, SL...sealing material, PSVI...protective film, GL...scanning signal line, D
L...Video signal line, GI...Insulating film, GT...Gate IT pole, AS...I-type semiconductor layer, SD...Source electrode or drain electrode, psv...Protective film, LS・
...light shielding film, LC...liquid crystal, TPT...thin film transistor, ITO...transparent electrode, gpd...conductive film, C add...holding capacitor element, Cgs...superimposed capacitance, C pix...Liquid crystal capacity (numerical subscripts after alphabetic characters are omitted).

Claims (1)

[Claims] 1. First and second transparent substrates stacked on top of each other at a predetermined interval, a sealing material provided along the edge between the two substrates, and a sealing material between the two substrates. The liquid crystal is enclosed and sealed with the sealing material, and a plurality of wirings for driving each pixel are arranged on one of the substrates, and one end of the wiring has a connecting terminal, and the other end has a connecting terminal. A measurement terminal is provided,
The connection terminal and the measurement terminal are arranged alternately in a direction perpendicular to the direction in which the wiring extends, and the tip of the measurement terminal is located inside the sealing material. LCD display device. 2. A liquid crystal display device, wherein the tip of the measurement terminal is covered with a protective film, and the outer edge of the protective film is located inside the sealing material.