JPH0357246A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To satisfy both a request from a maker's side and a request from a user's side by a method wherein an interconnection region is formed between I/O cells and outside pads and the cells and the pads are connected by the interconnection region by arbitrarily combining them. CONSTITUTION:An interconnection region 6 of a two-layer structure which can realize an interconnection in a right-angled direction is formed between I/O cells 3, 3a, 3b and outside pads 1, 1a, 1b. The cell 3a and the pad 1a which are not situated in opposite positions are connected by an interconnection 2a and the cell 3b and the pad 1b which are situated in opposite positions are connected by an interconnection 2b, respectively. Thereby, even when an optimum cell position requested on a maker's side and an optimum pad position requested on a user's side are not almost opposite, the cells 3, 3a, 3b and the pads 1, 1a, 1b can be connected by the region 6. That is to say, both the request from makers and the request from the users can be satisfied without changing these requests.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, for example, a technology that is effective when applied to a semiconductor integrated circuit device such as a Bi-CMOS gate array. It is about effective techniques. [Prior art] Bi-CMOS gate array technology is described in, for example, "Nikkei Electronics 4, August 12, 1985, p.
7 to p. 208.

By the way, in a semi-custom semiconductor integrated circuit device such as a gate array, a structure has been considered in which a plurality of I/O cells and external pads are respectively provided in roughly one-to-one correspondence. The third example shows an example of a semiconductor integrated circuit device that includes a plurality of I/O cells and external pads that roughly correspond to one pair.
It is a diagram.

In the figure, reference numeral 4 indicates an internal circuit composed of a gate array, and this internal circuit 4 includes, for example, Bi-
CMOS circuits etc. are formed. Reference numeral 1 indicates an external bathode connected to a lead (not shown), and 3 indicates an I/O cell (
These I/O cells 3, 3-3 and external pads 1, 1-l are respectively arranged so as to be roughly opposed to each other, and external pad 1 and external pad l are connected to each other. The cell 3 located approximately opposite to the cell 3 is connected to the cell 3 by a wiring 2 made of, for example, aluminum.

That is, in the above semiconductor integrated circuit device, ■/○
Cells 3.3-3 and external pads 1, 1-1 are each approximately 1
It is configured to correspond to one-on-one.

In FIG. 3, in order to avoid complication of the drawing, the I/O cells 3, 3-3 and the external pads 1, 1-↓ are arranged in a one-to-one correspondence.

[Problems to be Solved by the Invention] However, the semiconductor integrated circuit device having the above configuration has the following problems.

That is, on the manufacturer's side, I/O cells 3, 3 to 1, which roughly correspond to the external pads 1 to 1,
The position of 3 is determined by giving priority to improving characteristics such as noise, but on the user side, the position of the printed circuit board on which lead pins are mounted in one-to-one correspondence with the external pads 1. Since the upper position is determined by giving top priority to the wiring layout of the printed circuit board, there is a problem that the positions of the external pads requested by the manufacturer and the user do not match.

When such a problem occurs, the user usually has to change the design of the printed circuit board to accommodate the optimal external pad (I/O cell) position requested by the manufacturer, so the user It will cause trouble.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor integrated circuit device that satisfies both the manufacturer's and user's requirements (specifications) without changing them. [Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, it is equipped with a large number of I/O cells and external pads arranged at positions roughly opposite to this I/O cell.
A semiconductor integrated circuit device in which a cell and an external pad arranged approximately opposite to the I/O cell are respectively connected, and a wiring region is formed between the I/O cell and the external pad. It is. [Function] According to the above-mentioned means, since a wiring area is formed between the I/O cell and the external pad, the optimum I/O cell position required by the manufacturer and the optimum I/O cell position required by the user can be adjusted. Even if the optimal external pad positions are not roughly opposed to each other, the wiring area allows the I/O cell required on the manufacturer's side to be connected to the external pad required on the user side that is not located at the opposite position of this I/O cell. As a result, the above objective of satisfying both the manufacturer's and user's requirements (specifications) without changing them will be achieved.

[Examples] Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a semiconductor integrated circuit device according to the present invention. The outline is as follows. In the figure, reference numeral 4 indicates an internal circuit comprised of a gate array, and this internal circuit 4 includes, for example, Bi-
CMOS circuits and the like are formed.

Reference numerals 1, la, and lb indicate external pads connected to leads not shown, and 3.3a and 3b indicate I/O cells (external interface circuits), respectively. The external pads 1, la, and lb are placed at the optimum positions required by the manufacturer, while the external pads 1, la, and lb are placed at the optimum positions required by the user. The I/O cell 3 and the external pad 1 that corresponds to (must be connected to) this I/O cell 3 are placed at roughly opposing positions as in the past, but the I/O
The cell 3a and the external pad 1a that corresponds to (must be connected to) this I/O cell 3a, the I/O cell 3b and the external pad 1b that corresponds to (must be connected to) this I/O cell 3b, In this embodiment, they are arranged at positions that do not face each other.

Here, in the semiconductor integrated circuit device of this embodiment. I
Between the /O cells 3, 3a, 3b and the external pads 1, la, lb, there is a wiring region 6 of a two-layer structure made of, for example, aluminum, which enables wiring in the perpendicular direction (vertical and horizontal directions in the figure). The external pad 1 is formed and is not placed at a position facing the I/O cell 3a and this cell 3a.
a refers to the wiring 2a formed in the wiring area 6,
The I/O cell 3b and the external pad 1b which is not placed opposite the I/O cell 3b are connected to each other by a wiring 2b formed in the wiring region 6.

In addition, the I/O cell 3 and the external pad 1 arranged opposite to the I/O cell 3 are connected by the same arrangement as in the past. According to the semiconductor integrated circuit device, the following effects can be obtained.

That is, yI/O cells 3, 3a, 3b and external pad 1,
Since the wiring area 6 is formed between la and lb, the optimum I/O cell position required on the manufacturer side and the optimum external pad position required on the user side do not have to be roughly opposite. Due to the wiring area 6, the required work on the manufacturer side/○ cell 3a
, 3b and the external pads la, lb required on the user side that are not placed opposite the I/O cells 3a, 3b can be connected, thereby meeting the requirements (specifications) of the manufacturer side and the user side. It becomes possible to satisfy both without changing. FIG. 2 shows another embodiment of the semiconductor integrated circuit device according to the present invention. In the same figure, symbols 11.11 to 11 indicate external pads,
11a is an external pad for input in the external pad ll,
llb indicates the external pad for output in the external pad 1↓, and these external pads 11, lla, l
A large number of I/O cells are arranged inside the lb. Reference numeral 20 designates an I/O cell for input corresponding to (must be connected to) the external pad lla for input, and 21
indicate output I/O cells that correspond to (must be connected to) the above-mentioned output external pad llb, and inside these I/O cells 20 and 21 are gate arrays indicated by dotted lines. An internal circuit 33 is formed. The I/O cells 20, 21 are placed at optimal positions required by the manufacturer, and the external pads 11, 1la, and llb are placed at optimal positions required by the user. A wiring area 16 similar to that in the above embodiment is formed between the I/O cells 20, 21 and the external pads 11, lla, 11b, and the input external pad l1a and the input I/O The cell 2o is defined by the wiring 12 formed in the wiring region 16.
The above external pad llb for output and I/O cell 2 for output
1 are connected to each other by a wiring 14 formed in the wiring region l6, and the input I/O cell 20 and the output I/O cell 21 are connected to each other by a wiring 22 formed in the internal circuit 33. connected by.

As described above, in this embodiment, the position of the optimum I/O cell 21 required on the manufacturer side and the position of the optimum external pad llb required on the user side are not approximately opposed to each other; 16,
The I/O cell 21 required on the manufacturer side can be connected to the external pad llb required on the user side which is not placed in the opposite position to this I/O cell 21, as in the above embodiment. This makes it possible to satisfy both the manufacturer's and user's requirements (specifications) without changing them.

Moreover, in this embodiment, since the length of the wiring II22 formed in the internal circuit 33 can be made as short as possible, the external pad lla for input, the wiring 12, Cell 20. Wiring 22, I/O cell 2 for output
1. If the output external pad llb line is used for monitoring, it can be expected that the bus delay can be made extremely small.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the above embodiment, the wiring area has a two-layer wiring structure, but it is also possible to adopt a wiring structure of three or more layers. .

Further, in the above embodiment, an example of application to a semiconductor integrated circuit device configured with a gate array is described, but the present invention can also be applied to, for example, a semi-custom type semiconductor integrated circuit device. In short, it is applicable to all semiconductor integrated circuit devices that are configured so that a plurality of I/O cells and external pads correspond approximately one-to-one. Further, in the above embodiment, an example of application to a semiconductor integrated circuit device including a Bi-CMOS circuit is described, but the present invention also applies to a semiconductor integrated circuit device including other circuit elements. Needless to say, it is applicable.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, it is equipped with a large number of I/O cells and external pads arranged at positions roughly opposite to this work/○ cell, and this work/○
In a semiconductor integrated circuit device in which a cell and an external pad arranged at a position roughly opposite to the I/O cell are respectively connected, an interconnection area is formed between the I/O cell and the external pad. As a result, even if the optimum I/O cell position required by the manufacturer side and the optimum external pad position required by the user side are not roughly opposed, the wiring area allows the required processing/processing time to be achieved by the manufacturer side. ○ It becomes possible to connect the cell to an external pad required on the user side that is not placed opposite the I/O cell. As a result, it becomes possible to satisfy both the manufacturer's and user's requirements (specifications) without changing them.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part of an embodiment of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a plan view of another embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 3 is a plan view of a prior art. FIG. 2 is a plan view of the main parts of such a semiconductor integrated circuit device. 1 v 1 a r l b + 1 1 + 1 1
a + 1 l b ...external pad. 2.2a
, 2b, 12.14 = wiring, 3.3a, 3b, 20
．． 21” I/O cell, 6, 16... wiring area, Fig. 1

Claims (1)

[Claims] 1. An I/O cell and a large number of external pads arranged at positions approximately opposite to the I/O cell, the I/O cell and the I/O cell at positions approximately opposite to each other. 1. A semiconductor integrated circuit device, wherein a wiring region is formed between the I/O cell and the external pad, in the semiconductor integrated circuit device, the I/O cell and the external pad being connected to each other. 2. The semiconductor integrated circuit device according to claim 1, wherein the connection between the I/O cell and the external pad can be made in any combination using the wiring area. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein a gate array is formed in the semiconductor integrated circuit device.