JPH0355885A - Light emitting and receiving module - Google Patents

Light emitting and receiving module

Info

Publication number
JPH0355885A
JPH0355885A JP1192162A JP19216289A JPH0355885A JP H0355885 A JPH0355885 A JP H0355885A JP 1192162 A JP1192162 A JP 1192162A JP 19216289 A JP19216289 A JP 19216289A JP H0355885 A JPH0355885 A JP H0355885A
Authority
JP
Japan
Prior art keywords
light emitting
light
emitting element
array
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1192162A
Other languages
Japanese (ja)
Other versions
JP2859649B2 (en
Inventor
Yukihisa Kusuda
幸久 楠田
Hisao Nagata
久雄 永田
Yasuhisa Kuroda
黒田 靖尚
Shuhei Tanaka
修平 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Sheet Glass Co Ltd
Original Assignee
Nippon Sheet Glass Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Sheet Glass Co Ltd filed Critical Nippon Sheet Glass Co Ltd
Priority to JP19216289A priority Critical patent/JP2859649B2/en
Publication of JPH0355885A publication Critical patent/JPH0355885A/en
Application granted granted Critical
Publication of JP2859649B2 publication Critical patent/JP2859649B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Optical Integrated Circuits (AREA)
  • Led Devices (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Abstract

PURPOSE:To simplify the structure of an element which makes an integrated element to carry the function of a channel selector so as to simplify the manufacturing process of the title module by using a light emitting element array having self scanning function as a plurality of light emitting elements. CONSTITUTION:A P-type semiconductor layer 23, an N-type semiconductor layer 22, and a P-type semiconductor layer 21 are formed on a grounded N-type GaAs substrate 1. A light emitting element array 101 on which the layers 23, 22, and 21 are separated into single light emitting elements (T-2)-(T+1) and which has self-scanning function is used and an arbitrary one is used as a light receiving element 102. A negative resistance element composed of a laminated body of compound semiconductors such as GaAs, AlGaAs, etc., can be used as the light emitting element to be used for the array 101. Therefore, even a light emitting or receiving module which requires numerous photocouplers such as channel selectors, can be formed as an integrated element, because no additional complicated scanning circuit is required. Moreover, since no complicated wiring is used, manufacturing process can be simplified and manufacturing yield can be improved.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

本発明は、発光素子と受光素子とを用いて電気信号を一
旦光信号に変換して伝達させるホトカブラを用いた発光
・受光モジュールに関し、特に発光素子として自己走査
機能を有する発光素子アレイを用いた、集積化可能でか
つチャネルセレクタとして使用可能な発光・受光モジュ
ールに間する.
The present invention relates to a light-emitting/light-receiving module using a photocoupler that uses a light-emitting element and a light-receiving element to convert an electrical signal into an optical signal and then transmitting the signal, and in particular uses a light-emitting element array having a self-scanning function as the light-emitting element. , a light-emitting/light-receiving module that can be integrated and used as a channel selector.

【従来の技術】[Conventional technology]

従来、発光素子と受光素子を組み合わせたホトカブラが
よく知られている. 第12図に従来のホトカブラの構成例を示す。 ホトカブラは発光ダイオード(101)と受光素子(こ
こではホトトランジスタ)(102)が空間的に分離さ
れバッケージングされている.発光ダイオード(lOf
)の端子(+),  (2)間に加えられた電流で発光
ダイオード(101)が発光し、この光がホトトランジ
スタ(102)に入る。そしてホトトランジスタ( 1
 02)の端子(3),  (4)間に電流をながすこ
とができ、スイッチが入る.これにより端子(1), 
 (2)間の電気信号を端子(3).  (4)間に伝
達することができる.このホトカブラの特徴は人力、出
力間が完全に電気的に分離されているため、電源、外来
ノイズの伝送を妨げる働きがあり、システムの分離等に
使用される。
Conventionally, photocouplers that combine a light emitting element and a light receiving element are well known. FIG. 12 shows an example of the configuration of a conventional photocoupler. In a photocoupler, a light emitting diode (101) and a light receiving element (here, a phototransistor) (102) are spatially separated and packaged. Light emitting diode (lOf
) The light emitting diode (101) emits light due to the current applied between the terminals (+) and (2), and this light enters the phototransistor (102). And phototransistor (1
Current can flow between terminals (3) and (4) of 02), and the switch is turned on. As a result, terminal (1),
(2) and the electrical signal between terminals (3) and (3). (4) It is possible to communicate between The feature of this photocoupler is that human power and output are completely electrically separated, so it works to prevent the transmission of power and external noise, and is used for system isolation.

【発明が解決しようとする課H】[Question H that the invention attempts to solve]

上記ホトカブラは、信号の伝達経路途中にいれてノイズ
の分離に使用するものであるが、機能としてはこれ以上
のものではない.従ってホトカブラ自身に種々の機能を
もたせるのは無理で、外部で処理しなければならなかっ
た。 また、上記ホトカブラを複数個使用し、チャンネルセレ
クタとして使用することが考えられるが、上記の様なホ
トカブラを複数個並べると、それだけでかなりの体積を
しめ、また各々の配線等を行なう必要があった. また、発光素子および受光素子をアレイ状に配列し、機
能させることも考えられるが、該発光素子アレイを機能
させるには、発光素子の走査回路が必要とされ、該走査
回路の配線等を行なう必要があった。
The above-mentioned photocoupler is placed in the middle of the signal transmission path and is used to separate noise, but its functionality does not exceed this. Therefore, it was impossible to provide various functions to the photocoupler itself, and the processing had to be done externally. Also, it is possible to use multiple photocouplers as described above and use them as channel selectors, but if multiple photocouplers like the one above are lined up, it would take up a considerable amount of space and would require wiring for each one. Ta. It is also conceivable to arrange light emitting elements and light receiving elements in an array and make them function, but in order to make the light emitting element array function, a scanning circuit for the light emitting elements is required, and wiring of the scanning circuit etc. is required. There was a need.

【課題を解決するための手段】[Means to solve the problem]

本発明は、上記従来の問題点を解決するために、複数の
発光素子と複数の受光素子とを用いて、電気信号を一旦
光の信号に変換して伝達させる発光・受光モジュールに
おいて、該複数の発光素子として自己走査機能を有する
発光素子アレイを用いている。 該自己走査機能を有する発光素子アレイとじては、 (a)しきい電圧もしくはしきい電流が外部から制御可
能な発光素子を多数個、一次元,二次元,もしくは三次
元的に配列し,、互いに近傍に位置する少なくとも2つ
の発光素子を光学的手段で接続するか、または互いに近
傍に位置する少なくとも2つの発光素子の、しきい電圧
もしくはしきい電流を制御する制御電極を互いに電気的
手段にて接続し、各発光素子に電源ラインを電気的手段
を用いて接続すると共に、クロックパルスと該電気信号
とを印加させるクロックラインを接続しk発光素子アレ
イ、および (b)しきい電圧もしくはしきい電流が外部から制御可
能な制御電極を有するスイッチ素子多数個を配列したス
イッチ素子アレイの各スイッチ素子の制御電極を互いに
電気的手段もしくは光学的手段にて接続し、かつ各スイ
ッチ素子に電源ラインを電気的手段を用いて接続すると
共にクロックラインを接続して形成した自己走査アレイ
と、しきい電圧もしくは(ノきい電流が外部から制御可
能な制御電極を有する発光素子多数個を配列した発光素
子アレイの各しきい電圧もしくはしきい電流を制御する
電極を前記スイッチ素子の制御電極と電気的手段にて接
続し、各発光素子に該電気信号を印加するラインを設け
た発光素子アレイ、 等が例示できる。 本発明は、複数の発光素子として自己走査機能を有する
発光素子アレイを用いたものであって、受光素子として
は、任意の物が使用できる。 また、発光素子プレイと受光素子との光学的結合方法も
、レンズ等を介する方法,遮蔽板を介する方法,ファイ
バーアレイ等を介する方法等任意の方法が使用出来る. また、発光素子の数および受光素子の数も1対lに限ら
ず、機械的手段または光学的手段により、多対1.  
1対多の対応および/またはその選択機能を有する物で
あってもかまわない。 自己走査機能を有する発光素子アレイに用いる発光素子
としては、GaAs,AIG.aAs等の化合物半導体
を積層した負性抵抗素子が例示出来る.また、発光機能
を有するものであれば、レーザーサイリスタであっても
かまわない。
In order to solve the above conventional problems, the present invention provides a light emitting/light receiving module that uses a plurality of light emitting elements and a plurality of light receiving elements to convert an electrical signal into a light signal and then transmit the light signal. A light emitting element array having a self-scanning function is used as the light emitting element. The light-emitting element array having the self-scanning function includes: (a) a large number of light-emitting elements whose threshold voltages or threshold currents can be externally controlled are arranged one-dimensionally, two-dimensionally, or three-dimensionally; At least two light emitting elements located close to each other are connected by optical means, or control electrodes for controlling the threshold voltage or threshold current of at least two light emitting elements located close to each other are connected to each other by electrical means. (b) A power supply line is connected to each light emitting element using electrical means, and a clock line for applying a clock pulse and the electric signal is connected to the light emitting element array, and (b) a threshold voltage or threshold voltage. The control electrodes of each switch element of a switch element array, which has a large number of switch elements each having a control electrode whose threshold current can be controlled from the outside, are connected to each other by electrical means or optical means, and each switch element is connected to a power supply line. A self-scanning array is formed by connecting both using electrical means and a clock line, and a light-emitting element is an array of a large number of light-emitting elements each having a control electrode whose threshold voltage or current can be controlled from the outside. A light emitting element array in which an electrode for controlling each threshold voltage or threshold current of the array is connected to a control electrode of the switch element by electrical means, and a line for applying the electric signal to each light emitting element is provided. The present invention uses a light emitting element array having a self-scanning function as a plurality of light emitting elements, and any arbitrary thing can be used as a light receiving element. Any optical coupling method can be used, such as a method using a lens, a method using a shielding plate, a method using a fiber array, etc. Also, the number of light emitting elements and the number of light receiving elements is not limited to 1:1. , many to one by mechanical or optical means.
It does not matter if it has a one-to-many correspondence and/or a selection function. Examples of light emitting elements used in the light emitting element array having a self-scanning function include GaAs, AIG. An example is a negative resistance element made of layered compound semiconductors such as aAs. Further, a laser thyristor may be used as long as it has a light emitting function.

【作用】[Effect]

本発明は、従来問題であったホトカブラ等の発光・受光
モジュールの光源として自己走査機能を有する発光素子
アレイを使用することによって、高機能化,多機能化,
集積化をはかるものである.本発明では、上記のように
発光素子として、発光点の転送機能,発光点の発光強度
変調機能を合わせ持たせることの出来る自己走査型発光
素子アレイを用いているため、チャンネルセレクタ等の
多数のホトカブラを必要とする発光・受光モジュールで
あっても、複雑な付加的走査回路が必要ないため、集積
化した素子として形成できる.また、複雑な配線が必要
ないため、製造工程の簡略化および製造歩留の向上をは
かることが出来
The present invention uses a light emitting element array with a self-scanning function as a light source for a light emitting/light receiving module such as a photocoupler, which has been a problem in the past.
This is intended to promote integration. In the present invention, a self-scanning light emitting element array is used as the light emitting element as described above, which can have both the function of transferring light emitting points and the function of modulating the light emission intensity of the light emitting points. Even light-emitting/light-receiving modules that require a photocoupler can be formed as integrated elements because no complicated additional scanning circuit is required. Additionally, since no complicated wiring is required, the manufacturing process can be simplified and manufacturing yields can be improved.

【実施例】【Example】

実施例−1 本発明の第一実施例の概念図を第l図に示す。 本実施例の発光・受光モジュールは、発光素子(101
)のアレイと、受光センサ(102)のアレイと、発光
素子(101)の発光点と受光センサ(102)の受光
点を光学的に1対1に対応させる結像レンズ(l00)
とからなる. まず、本実施例に使用する発光素子(101)のアレイ
の構造および製造工程を説明する. 第2図および第3図に示す様に、接地されたN形GaA
s基板(1)上にP形半導体層(23)、N形半導体層
(22)、P形半導体層(2I〉の各層を形成する。 そしてホトリソグラフィ等及びエッチングにより、各単
体発光素子T (−2)〜T (+1)に分離する(分
離溝(50))。 (単体発光素子T (−2)〜T 
(+1)はこれらの発光素子アレイの一部を代表する。 )アノード電極(40〉はP形半導体層(21)とオー
ミック接触を有し、ゲート電極(41)はn形半導体層
(22)とオーミック接触を有する。絶縁層(30)は
素子と配線との短絡を防ぐためのものであり、同時に特
性劣化を防ぐための保護膜でもあるう 絶縁Fl’ (30)は発光サイリスタの発光波長の光
がよく通る材質をもちいることが望ましノい.N形Ga
As基板(1)はこのサイリスタのカソードとして働く
。 各単体発光素子の7,昌一ド@ 4 <40)は、転送
クロックライン(φ号、φ2、,φ3)l:7)いずれ
か1本が、長平方向にφ1、φ2、φ3のII1番″e
繰り返す様に接続される。またゲート電極には負荷抵抗
RLが接続される.一方各素子間に光結合が発生ずると
本実施例の転送動作が影響されることがある.これを防
止するため、ゲート電極のー・部を発光素子間の分離溝
のなかに入れ、光結合を防止する構造としている. 上記発光素子アレイの動作を説明すると、まず転送クロ
ックφ3がハイレベルとなり、発光素子T(0)がO 
Nする.この時、3端子サイリスタの特性から発光素子
T(0)のゲ・一ト電極Gθは零ボルト近くまで引き下
げられる. (シリコンサイリスタの場合約1ボルトで
ある) また、上記発光サイリスタは光を感じてそのターンオン
電圧が低下する特性を持つ。発光サイリスタをその発光
が近隣の素子にk射するよう構成してあるので、発光素
子に距離的に近い素子、または光がよくあたるよう配置
された素子はそのターンオン電圧が下がることになる.
, 電源電圧をVaκとすると,発光素子T (0)に近く
、入射光の光量の多い素子のゲ・一ト電圧が最も低下し
、以降順に発光素子T(0)から離れるに従いゲート電
圧は上昇していく. 次の転送クロックバルスφ1は最近接の発光素子T(1
)、T (−2)及びT(4)、T (−5)等に加わ
るが、これらの中で最もON電圧が低い素子は発光素子
T(!)である.次に低い素子は発光素子T (−2)
となる. そこで転送クロックパルスφlのハイレベル電圧を、発
光素子T (1)のゲート電圧Glと発光素子T(−2
)のゲート電圧G”2との間に段定1,ておけば、発光
素子T (1)のみONさせることができ、転送クロッ
クφ1、φ2、φ3のハイレベル電圧を交互に互いに少
しづつ重なるように設定すれば、転送動作(3相駆動自
己走査)を行なうことができる。 次に受光センサ(102)のアレイの構造と製造工程を
説明する。 燐等がドウブされたN形シリコン基板上に熱酸化膜を形
成する.ホトリソグラフィによりこの熱酸化膜の一部t
ご穴をあけ、この部分にホウ素等のP形不純物をドウブ
する,,さらにこの表面を再度酸化した後、P形不純物
上の酸化膜に穴をあけ、基板全体上に金属膜を蒸着等の
方法により形成する● この金属膜をホトリソグラフィ
およびエッチングによりバター二冫グして上側電極を作
製し、PN接合.を有するシリコン受光センサアレイが
作製される。 発光素子のアレイと受光センサのアレイとは、同数の素
子数を有する様に形成され、結像レンズ(+00)を介
して対面ざれ、発光素子(101)の発光点と受光セン
サ(IQ2)の受光点が、光学的に1対lに対応ずる様
固定されモジュール化される。 次に上記発光・受光モジールの動作を説明すると、発光
素子部にスタートバルスφSがかかり発光の転送がスタ
ートし、転送クロックφ1、φ2、φ3によって発光が
運ばれていく。このときの駆動パルスの状況例を第4図
に示す。 転送クロ・・7クφ1はφSと同じタイミングでハイレ
ベルになっており、このとき発光素子T(1)がON状
態(発光状態)となる。そして次のφ2で発光素子T(
2)に転送される。この順で次々と移動していくが,、
この図では発光素子T(4)の場所でいったん転送がス
トップする, このとき、転送クロックφ1に伝送する信号φを乗せる
と、第4図に示すように発光素子T(5)の出力Lは変
化する。このとき発光素子T(5)&光学的に対応する
位置の受光素子上に入射する光も変化し、受光素子の端
子A 2 − K 2の出力として信号φ1が取り出さ
れるウ この一時停止するビットを変化させれば伝送させたビッ
トをC4由に選択することができ、チャネルセレクタと
しての機能を果たすことができる。 このときホトカブラとしての機能は全く損なわれず、ホ
トカブラの高機能化が達成できる。 上記の様ζ乙、本実施例の発光・受光モジュールによれ
ば、複数のホトカブラを用いなければ、伝達出来なかっ
た信号を、3本の転送クロックライン(φ1、φ2..
φ3)と、変調電源電圧V6Kを用いて容易に伝達する
ことが出来る。 本実施例の発光・受光モジュールは、複数のホトカブラ
を用いた伝達装置と較べて、集積化され、かつ走査li
i置および走査用配線等が簡略化されているkめ信頼性
の高い伝達装置となっている.上記実施例においては、
発光素子のアレイと受光センサのアレイとの光学的結合
に、結像レンズを用いているが、該結合は結像レンズに
よる結合に限らず、ファイバーアレイによる結合、遮蔽
板を有するスペーサーを用いた結合、等任意の結合方法
であってかまわない。特にノイズ等を防止し、コンパク
ト化のために、隣接素子の光の影響を遮断する薄板状遮
蔽板を用いた結合が好ましい。 また、上記実施例においては、発光素子の数と受光セン
サの数を同数として全体を固定しモジュール化している
が、該構造は上記に限らず、例えば受光センサの数を発
光素子の数の倍数として、機械的手段を用いで切り替え
が出来るようにしてもかまわない. また、上記実施例では転送クロックパルスとして、φ富
、φ2、φ3の3相を想定したが、より安定な転送動作
を求める場合ζこはこれを4相以丘に増加させてもよい
。 また本実施例では発光サイリスタの構造を最4}簡単な
場合について示したが、発光効率を上げるために、例え
ばダブルへテロ構造の様なより複雑な構造,屡構成を導
入してもよい。 またここではPNPNのサイリスタ構成を例に説明した
が,この電位を検知し、しきい電圧が低下し、これを利
用して転送動作を行なわせるという構成は、PNPN構
成のみに限られず、その機能が達成できる素子であれば
特に限定されない。 例えば、PNPN4層構成でなく、6層以上の構成でも
同様な効果を期待でき、まったく同様な自己走査機能を
達成することが可能である。さらには静電誘導(Sl)
サイリスタまたは電界制御サイリスタ(FCT)と呼ば
れるサイリスタを用いてもまったく同様である。 また、上記実施例においては、転送方向の発光素子のゲ
ート電圧を低下させる手段として、光を用いているが、
各発光素子のしきい電圧もしくはしきい電流を制御する
電極を互いに電気的手段にて接続しても実施できる. 該電気的接続手段としては、抵抗素子,ダイオード,ト
ランジスタ等の一方向性を持つ素子等の手段であってよ
く、特にダイオード等の一方向性素子を用いると、2相
の転送クロックパルスを用いて自己走査できるので好ま
しい。 該電気的接続手段として、ダイオードを用いた発光素子
アレイの構造例を第5図,第6図,第7図,および第8
図に基づき以下に例示する。 第6図および第7図に示す様に、接地されたN形GaA
s基板(1)上にN形GaAs層(24b)、N形AI
GaAs層( 2 4 b)、P形GaAs層(23)
、N形GaAs層(22)、P形AIGaAs層(2l
b)、P形GaAs層(21a)の各層を順次形成する
。 そしてホトリソグラフィ等及びエッチングにより分離溝
(50)を形成し、各単体発光サイリスタT(一1)〜
T (+1)に分離する. (単体発光素子T (−1
)〜T (+1)はこれらの発光素子アレイの一部を代
表する。)次に、P形G a A s N (21a)
、P形AIGa A s N (2lb)の一部を除去
し分M l (51)を形成し発光サイリスタと結合用
ダイオード間の分離を行なう.絶縁膜(30)を全体に
被覆し、電極上にコンタクト孔C1を設け、金属薄膜配
線で電極接続(40)および転送クロックラインφ1、
φ2を接続する。 ここで転送クロックラインφ1、φ2はそれぞれ1素子
おきに接続する。 第8図に上記発光素子アレイの等価回路図を示す. 発光サイリスタT (−2)〜丁(+2)は、それらが
一列に並べられた構成となっている,、それぞれの発光
サイリスタT (−2)〜T (+2)にはゲート電極
G−2〜Gや2が設けられ、ダイオードD−2〜D2に
より各々隣接ゲート電極同士が電気的に接続されている
.ダイオードD−2〜D2は、発光サイリスタT (−
2)〜T (+2)の並びに対して一方向に対して電流
を流す様に配置されている。 上記発光素子アレイの動作を説明すると、まず転送クロ
ックφ2がハイレベルとなり、発光サイリスタT(0)
がONしているとする.この時、3端子サイリスタの特
性から発光サイリスタT (0)のゲート電極GI1は
零ボルト近くまで引き下げられる(シリコンサイリスタ
の場合約1ボルトである).電譚電圧VGKを5Vとす
ると、負荷抵抗RL.  ダイオードD−2〜D2のネ
ットワークから各発光サイリスタのゲート電圧が決まる
.そして発光サイリスタT (0)に近い素子のゲート
電圧が最も低下し、以降順に発光サイリスタT(0)か
ら離れるに従いゲート電圧は上昇していく。しかしなが
ら、ダイオード特性の一方向性、非対象性から電圧を下
げる効果は発光サイリスタT (0)の片側(第8図で
は右半分)にしか働かない。即ち発光サイリスタT(1
)のゲート電極GIは発光サイリスタT(0)のゲート
電極G8に対し、ダイオードの順方向立ち上がり電圧V
d『だけ高い電圧に設定され、発光サイリスタT(2)
のゲート電極G2はゲート電極GIに対し、さらにダイ
オードの順方向立ち上がり電圧Vdrだけ高い電圧に設
定される。一方反対側(第8図では左半分)に相当する
発光サイリスタT (−1)のゲート電極G−+はダイ
オードD−+が逆バイアスとなっているため電流が流れ
ず、従って電源電圧VGKと同電位となる.次の転送ク
ロツクバルヌφ1は最近接の発光サイリスタT(1)、
T (−1)及びT(3)、T (−3)等に加わるが
、これらの中で最もON電圧が低い素子は発光サイリス
タT(1)で、約2Vd+である。 次に低い素子は発光サイリスタT(3)であり、約4V
arとなる。発光サイリスタT (−1)、T (−3
)のON電圧は約VoK+Vdrとなる.以上から転送
クロックパルスのハイレベル電圧を2Va+から4Vd
+の間に設定しておけば発光サイリスタT(1)のみO
Nさせることができ、転送動作を行なうことができる. 上記例においては、負荷抵抗(63)R Lとして発光
素子のN形GaAs層(22〉を用いているが、これは
別の層を用いてもよい。例えばp層(23)を用いる、
あるいは別の抵抗領域を設け、これを用いてもよい。 また、本発明に用いる自己走査型発光素子アレイは、上
記例に限らず以下に示す様なブロックを形成した改良構
造であってもかまわない。 第3構造例を第9図および第10図を用いて以下に説明
する。第9図は本実施例の発光素子アレイの平面図を示
し、第10図は等価回路図である.まず、 n形GaA
s基板(1)上に、 n形GaAs層(24b)、 n
形AIGaAs層(24a)、 p形GaAs層(23
a)、n形GaAs層(22a)、 p形AIGaAs
層( 2 l b)、およびp形G aA sN (2
1a)を順次積層する。 積層された半導体層は、分離溝(50)により各発光素
子Tに分離される。また、各発光素子TOp形G aA
 s層(21a)およびp形AIGaAs層(2lb)
は、6つの島状にn形GaAs層(22a)上に残留す
る様、ゲート電極および一方向性結合素子作製のために
一部削除される。該5つの島は、2つの小さな島と連続
する3つの比較的大きな島とされ、3つの比較的大きな
島は、発光素子アレイの長手方向に、並ぶ様に配置され
る。2つの小さな島は、発光素子アレイの長手方向に、
島,島,谷、島,島,谷、島,島,谷と繰り返す様に配
置される。ここで、1つの比較的大きな島は1つの発光
素子に対応し、島,島,谷は3つの発光素子に結合され
た1つの走査回路素子に対応し、谷とは露出したn形G
aAS層(22a)のゲート電極部分を示す.次に基板
上全体に絶縁被膜(30)を被覆する。 そして、該絶縁被膜(30)の、前記削除操作されたn
形GaAs層(22a)上および5箇所のp形GaAS
層(21a)上の位置に接続用コンタクトホールC1を
開ける. 次に、該絶縁被膜(30)上に、各走査回路素子のn形
GaAs層(22a)と隣接する走査回路素子のp形G
aAs層(21a)とをコンタクトホールCIを用いて
接続し、かつの電源電極およびゲート電極結合用T字型
金属薄膜配線(45〉、発光素子の3つの太きな、島状
p形GaAs層(21a)へコンタクトホールC1を介
してクロックパルスをつたえる金属薄膜配線(44)、
発光素子の残りの島状p形GaAs層(21a)へコシ
タクトホールC1を介して駆動電圧をつkえる金属薄膜
配線(42)、をそれぞれ設ける.次に該金属薄膜配線
(45)上の一部に、ゲート電極一電源電極間の抵抗R
1−として使用する燐をドウブした非品質シリコン(1
63)を約1μmの厚さで被覆する.該非品質シリコン
(163)は、各発光素子に対して1つづつになるよう
分離される.次に基板上全体に絶縁被膜(3l)を被覆
する.そして、該絶縁被膜(31)の、前記非品質シリ
コン(+63)、金属薄膜配線02)、および金属薄膜
配線(44)の上の位置に接続用コンタクトホールC2
を間ける。 次に、該絶縁被膜(3l)上に、コンタクトホールC2
を介して金属薄膜配線(44) (発光素子のアノード
電極)へクロックパルスをつたえる書き込みライン(S
 in++  S inz.  S in3)、コンタ
クトホールC2(非晶質シリコン(163))を介して
金属薄膜配線(43) (走査回路素子のゲート電極)
へ電源電圧をつたえる電源ライン(4l)、コンタクト
ホールC2を介して金属薄膜配線(40) (走査回路
素子のアノード電極)へクロックパルスをつたえるクロ
ックラインφ1、φ2、を設けた. ここで、クロックライン結合用金属薄膜配線(40b)
上に設ける片側のコンタクト孔C2の位置は、各走査回
路素子のアノード電極が、クロックラインSin+、S
in2、Sin3のいずれか1本に、長さ方向に向かっ
てSinn、Sin2、Sinsの順番で繰り返しすよ
うに調整される. 第10図は上記発光素子アレイの等価回路図であるが、
上記回路が前記実施例と異なるのは、前記発光素子を走
査回路として使用し、該走査回路と同一構造の発光素子
を該走査回路から分離して設けている点と、新たな発光
素子を3つづつのブロックとし、lブロック内の発光素
子は1つの走査回路素子によって制御し、かつ1ブロッ
ク内の発光素子にそれぞれ別々のクロックラインを接続
して、発光素子の発光を制御した点である。 図中、発光素子Ll(−1),  L2(−1),  
L3(−1)、発光素子Ll(0),  L2(の,L
3(の、発光素子し+ ( − 1).  L2 (−
 1),  L3( − 1 )等がブロック化された
発光素子を示している。発光の転送は走査回路素子によ
りブロックごとに行なわれ、各発光素子の発光は各クロ
ックラインにより制御される。 実施例−2 本発明の第2の実施例を第11図に示す。この図は第1
図とほぼ同じ構成であるが、異なる点は発光素子(10
1)のアレイが一つでなく3つになっていることである
。各発光素子アレイ(+1),(12),(13)は実
施例1で述べたように機能するので、第l1図の例では
多入力、マルチチャネルのセレクタができる。 上記実施例においても発光素子(101)と受光センサ
(+02)との結合は必ずしもレンズを介する必要はな
く、物理的な光遮蔽壁を設けてもよい.またマルチチャ
ネルセレクタでは上記の3チャネルのみでなくもっと多
数のチャネルであってもよい.また受光素子は、従来例
にて述べたホトトランジスタに限られずホトダイオード
をはじめなんであっても動作する。
Example-1 A conceptual diagram of a first example of the present invention is shown in FIG. The light emitting/light receiving module of this example has a light emitting element (101
), an array of light-receiving sensors (102), and an imaging lens (l00) that optically makes a one-to-one correspondence between the light-emitting point of the light-emitting element (101) and the light-receiving point of the light-receiving sensor (102).
It consists of. First, the structure and manufacturing process of the array of light emitting elements (101) used in this example will be explained. As shown in Figures 2 and 3, the grounded N-type GaA
A P-type semiconductor layer (23), an N-type semiconductor layer (22), and a P-type semiconductor layer (2I) are formed on the s-substrate (1). Then, by photolithography and etching, each individual light emitting element T ( -2) to T (+1) (separation groove (50)). (Single light emitting element T (-2) to T
(+1) represents a part of these light emitting element arrays. ) The anode electrode (40> has ohmic contact with the P-type semiconductor layer (21), and the gate electrode (41) has ohmic contact with the n-type semiconductor layer (22).The insulating layer (30) has an ohmic contact with the P-type semiconductor layer (21). It is desirable that the insulation Fl' (30), which serves as a protective film to prevent short-circuiting and at the same time prevent property deterioration, be made of a material through which light of the emission wavelength of the light-emitting thyristor can easily pass. N type Ga
The As substrate (1) serves as the cathode of this thyristor. For each single light emitting element, one of the transfer clock lines (φ, φ2, φ3) l: 7) connects φ1, φ2, φ3 II1'' in the horizontal direction. e
Connected repeatedly. A load resistor RL is also connected to the gate electrode. On the other hand, if optical coupling occurs between each element, the transfer operation of this embodiment may be affected. To prevent this, the part of the gate electrode is inserted into the separation groove between the light emitting elements, creating a structure that prevents optical coupling. To explain the operation of the above-mentioned light emitting element array, first, the transfer clock φ3 becomes high level, and the light emitting element T(0) becomes OFF.
Do N. At this time, the gate electrode Gθ of the light emitting element T(0) is pulled down to near zero volts due to the characteristics of the three-terminal thyristor. (In the case of a silicon thyristor, it is about 1 volt.) Furthermore, the light-emitting thyristor has a characteristic that its turn-on voltage decreases when it senses light. Since the light-emitting thyristor is configured so that its emitted light is emitted to neighboring elements, the turn-on voltage of elements that are close to the light-emitting element or elements that are placed so that they are well exposed to light will be reduced.
, When the power supply voltage is Vaκ, the gate voltage of the element closest to the light emitting element T (0) and receiving a large amount of incident light decreases the most, and thereafter the gate voltage increases as the distance from the light emitting element T (0) increases. I will do it. The next transfer clock pulse φ1 is the nearest light emitting element T(1
), T (-2), T (4), T (-5), etc., but among these, the element with the lowest ON voltage is the light emitting element T (!). The next lowest element is the light emitting element T (-2)
becomes. Therefore, the high level voltage of the transfer clock pulse φl is set to the gate voltage Gl of the light emitting element T (1) and the light emitting element T (-2
) and the gate voltage G"2, only the light emitting element T (1) can be turned on, and the high level voltages of the transfer clocks φ1, φ2, φ3 are alternately overlapped slightly with each other. If set as follows, transfer operation (three-phase drive self-scanning) can be performed. Next, the structure and manufacturing process of the array of light receiving sensors (102) will be explained. On an N-type silicon substrate doped with phosphorus etc. A thermal oxide film is formed on the surface of the thermal oxide film.
A hole is made and a P-type impurity such as boron is doped into this part. After this surface is oxidized again, a hole is made in the oxide film on the P-type impurity and a metal film is deposited on the entire substrate. ● This metal film formed by the method is buttered by photolithography and etching to produce an upper electrode, and a PN junction is formed. A silicon light-receiving sensor array is fabricated. The array of light-emitting elements and the array of light-receiving sensors are formed to have the same number of elements, and face each other through an imaging lens (+00), so that the light-emitting points of the light-emitting elements (101) and the array of light-receiving sensors (IQ2) The light receiving points are fixed and modularized in an optical 1:1 correspondence. Next, the operation of the light emitting/light receiving module will be described. A start pulse φS is applied to the light emitting element section to start the transfer of light emission, and the light emission is carried by transfer clocks φ1, φ2, and φ3. An example of the driving pulse situation at this time is shown in FIG. The transfer clock 7 φ1 is at a high level at the same timing as φS, and at this time, the light emitting element T(1) is in the ON state (light emitting state). Then, at the next φ2, the light emitting element T(
2). They move one after another in this order, but...
In this figure, the transfer temporarily stops at the location of the light emitting element T(4).At this time, when the signal φ to be transmitted is added to the transfer clock φ1, the output L of the light emitting element T(5) becomes as shown in FIG. Change. At this time, the light incident on the light-emitting element T(5) & the light-receiving element at the optically corresponding position also changes, and the signal φ1 is taken out as an output from the terminals A2-K2 of the light-receiving element. By changing C4, the transmitted bit can be selected using C4, and it can function as a channel selector. At this time, the function of the photocoupler is not impaired at all, and high functionality of the photocoupler can be achieved. As described above, according to the light emitting/light receiving module of this embodiment, signals that could not be transmitted without using multiple photocouplers can be transmitted through the three transfer clock lines (φ1, φ2, . . .
φ3) and the modulated power supply voltage V6K. The light-emitting/light-receiving module of this embodiment is more integrated than a transmission device using multiple photocouplers, and has a scanning
It is a highly reliable transmission device with simplified wiring for positioning and scanning. In the above example,
An imaging lens is used for optical coupling between the light emitting element array and the light receiving sensor array, but the coupling is not limited to coupling using the imaging lens, but also coupling using a fiber array, spacer with a shielding plate, etc. Any combination method such as combination may be used. In particular, in order to prevent noise and the like and to achieve compactness, it is preferable to combine using a thin plate-shaped shielding plate that blocks the influence of light from adjacent elements. In addition, in the above embodiment, the number of light emitting elements and the number of light receiving sensors are the same and the whole is fixed and modularized, but the structure is not limited to the above. For example, the number of light receiving sensors is a multiple of the number of light emitting elements. However, it may be possible to switch using mechanical means. Further, in the above embodiment, three phases of φ, φ2, and φ3 are assumed as the transfer clock pulse, but if a more stable transfer operation is desired, this may be increased to four phases or more. Further, in this embodiment, the structure of the light emitting thyristor is shown in the simplest case, but in order to increase the light emitting efficiency, a more complicated structure or configuration, such as a double heterostructure, may be introduced. In addition, although the PNPN thyristor configuration has been explained here as an example, the configuration in which this potential is detected, the threshold voltage decreases, and this is used to perform the transfer operation is not limited to the PNPN configuration; There is no particular limitation as long as the element can achieve this. For example, instead of the PNPN four-layer structure, the same effect can be expected with a structure of six or more layers, and it is possible to achieve exactly the same self-scanning function. Furthermore, electrostatic induction (Sl)
The same is true when using a thyristor called a thyristor or a field controlled thyristor (FCT). Furthermore, in the above embodiment, light is used as a means for lowering the gate voltage of the light emitting element in the transfer direction, but
This can also be carried out by electrically connecting the electrodes that control the threshold voltage or threshold current of each light emitting element. The electrical connection means may be a resistive element, a diode, a transistor, or other unidirectional element. In particular, if a unidirectional element such as a diode is used, two-phase transfer clock pulses may be used. This is preferable because it can be used for self-scanning. Examples of structures of light emitting element arrays using diodes as the electrical connection means are shown in FIGS. 5, 6, 7, and 8.
An example is given below based on the figure. As shown in Figures 6 and 7, the grounded N-type GaA
N-type GaAs layer (24b) and N-type AI on the s-substrate (1)
GaAs layer (2 4 b), P-type GaAs layer (23)
, N-type GaAs layer (22), P-type AIGaAs layer (2l
b) Sequentially forming each layer of the P-type GaAs layer (21a). Then, a separation groove (50) is formed by photolithography etc. and etching, and each individual light emitting thyristor T (11) to
Separate into T (+1). (Single light emitting element T (-1
) to T (+1) represent a portion of these light emitting element arrays. ) Next, P type G a A s N (21a)
, a part of the P-type AIGa As N (2 lb) is removed to form a portion M l (51) to provide separation between the light emitting thyristor and the coupling diode. The entire surface is covered with an insulating film (30), a contact hole C1 is provided on the electrode, and an electrode connection (40) and a transfer clock line φ1 are made using metal thin film wiring.
Connect φ2. Here, the transfer clock lines φ1 and φ2 are connected to every other element. Figure 8 shows an equivalent circuit diagram of the above light emitting element array. The light-emitting thyristors T (-2) to T (+2) are arranged in a line. Each of the light-emitting thyristors T (-2) to T (+2) has a gate electrode G-2 to G-2. G and 2 are provided, and adjacent gate electrodes are electrically connected to each other by diodes D-2 to D2. The diodes D-2 and D2 are light emitting thyristors T (-
2) to T (+2) are arranged so that a current flows in one direction. To explain the operation of the above light emitting element array, first, the transfer clock φ2 becomes high level, and the light emitting thyristor T(0)
Suppose that is ON. At this time, due to the characteristics of a three-terminal thyristor, the gate electrode GI1 of the light emitting thyristor T(0) is pulled down to nearly zero volts (in the case of a silicon thyristor, it is approximately 1 volt). When electric voltage VGK is 5V, load resistance RL. The gate voltage of each light emitting thyristor is determined from the network of diodes D-2 to D2. The gate voltage of the element closest to the light emitting thyristor T (0) decreases the most, and thereafter the gate voltage increases as the element moves away from the light emitting thyristor T (0). However, due to the unidirectionality and asymmetric nature of the diode characteristics, the effect of lowering the voltage only works on one side (the right half in FIG. 8) of the light emitting thyristor T (0). That is, the light emitting thyristor T(1
) gate electrode GI of the light emitting thyristor T(0) has a forward rising voltage V of the diode with respect to the gate electrode G8 of the light emitting thyristor T(0).
The light emitting thyristor T(2) is set to a higher voltage by d'.
The gate electrode G2 is set to a voltage higher than the gate electrode GI by the forward rising voltage Vdr of the diode. On the other hand, no current flows through the gate electrode G-+ of the light-emitting thyristor T (-1) corresponding to the opposite side (the left half in FIG. 8) because the diode D-+ is reverse biased, so that the power supply voltage VGK They have the same potential. The next transfer clock valve φ1 is the nearest light emitting thyristor T(1),
Among them, the element with the lowest ON voltage is the light emitting thyristor T(1), which is approximately 2Vd+. The next lowest element is the light emitting thyristor T (3), which is about 4V
It becomes ar. Light emitting thyristor T (-1), T (-3
) is approximately VoK+Vdr. From the above, the high level voltage of the transfer clock pulse should be changed from 2Va+ to 4Vd.
If set between +, only the light-emitting thyristor T(1)
N, and transfer operations can be performed. In the above example, the N-type GaAs layer (22) of the light emitting element is used as the load resistor (63) R L, but another layer may be used. For example, a p-layer (23) may be used.
Alternatively, another resistance region may be provided and used. Further, the self-scanning light emitting element array used in the present invention is not limited to the above example, but may have an improved structure in which blocks as shown below are formed. A third structural example will be explained below using FIGS. 9 and 10. FIG. 9 shows a plan view of the light emitting element array of this example, and FIG. 10 shows an equivalent circuit diagram. First, n-type GaA
On the s substrate (1), an n-type GaAs layer (24b), n
type AIGaAs layer (24a), p-type GaAs layer (23
a), n-type GaAs layer (22a), p-type AIGaAs
layer (2 l b), and p-type GaA sN (2
1a) are sequentially stacked. The stacked semiconductor layers are separated into each light emitting element T by a separation groove (50). In addition, each light emitting element TOp type GaA
S layer (21a) and p-type AIGaAs layer (2lb)
are partially removed so as to remain on the n-type GaAs layer (22a) in the form of six islands in order to fabricate a gate electrode and a unidirectional coupling element. The five islands are two small islands and three relatively large islands that are continuous, and the three relatively large islands are arranged in a line in the longitudinal direction of the light emitting element array. Two small islands are located in the longitudinal direction of the light emitting element array.
They are arranged in a repeating manner: island, island, valley, island, island, valley, island, island, valley. Here, one relatively large island corresponds to one light emitting element, the island, island, valley corresponds to one scanning circuit element coupled to three light emitting elements, and the valley is an exposed n-type G
The gate electrode portion of the aAS layer (22a) is shown. Next, an insulating film (30) is coated over the entire substrate. Then, the deleted n of the insulating coating (30) is
type GaAs layer (22a) and five p-type GaAs layers
A contact hole C1 for connection is opened at a position on the layer (21a). Next, on the insulating film (30), the n-type GaAs layer (22a) of each scanning circuit element and the p-type GaAs layer (22a) of the adjacent scanning circuit element are coated.
The aAs layer (21a) is connected to the T-shaped metal thin film wiring (45) for connecting the power supply electrode and the gate electrode using the contact hole CI, and the three thick island-shaped p-type GaAs layers of the light emitting element are connected to the aAs layer (21a) using the contact hole CI. (21a) a metal thin film wiring (44) that transmits a clock pulse through the contact hole C1;
A metal thin film wiring (42) for supplying a driving voltage to the remaining island-shaped p-type GaAs layer (21a) of the light emitting element via the cositact hole C1 is provided. Next, a resistance R between the gate electrode and the power supply electrode is placed on a part of the metal thin film wiring (45).
Non-quality silicon doped with phosphorus (1
63) to a thickness of approximately 1 μm. The non-quality silicon (163) is separated, one for each light emitting device. Next, cover the entire board with an insulating film (3L). Then, a connection contact hole C2 is formed in the insulating film (31) at a position above the non-quality silicon (+63), the metal thin film wiring 02), and the metal thin film wiring (44).
between. Next, a contact hole C2 is formed on the insulating film (3l).
A write line (S
in++ S inz. S in3), metal thin film wiring (43) (gate electrode of scanning circuit element) via contact hole C2 (amorphous silicon (163))
A power supply line (4l) for transmitting a power supply voltage to the contact hole C2, and clock lines φ1 and φ2 for transmitting clock pulses to the metal thin film wiring (40) (anode electrode of the scanning circuit element) through the contact hole C2 were provided. Here, metal thin film wiring for clock line coupling (40b)
The position of the contact hole C2 on one side provided above is such that the anode electrode of each scanning circuit element is connected to the clock lines Sin+, S
It is adjusted to repeat in the order of Sinn, Sin2, and Sins in the length direction on either one of in2 and Sin3. FIG. 10 is an equivalent circuit diagram of the above light emitting element array.
The above circuit differs from the above embodiment in that the light emitting element is used as a scanning circuit, a light emitting element having the same structure as the scanning circuit is provided separately from the scanning circuit, and three new light emitting elements are provided. The light emitting elements in one block are controlled by one scanning circuit element, and the light emitting elements in one block are connected to separate clock lines to control the light emission of the light emitting elements. In the figure, light emitting elements Ll(-1), L2(-1),
L3(-1), light emitting element Ll(0), L2(of, L
3(, light emitting element + (- 1). L2 (-
1), L3(-1), etc. indicate blocked light emitting elements. Transfer of light emission is performed block by block by the scanning circuit element, and the light emission of each light emitting element is controlled by each clock line. Example-2 A second example of the present invention is shown in FIG. This figure is the first
The configuration is almost the same as in the figure, but the difference is that the light emitting element (10
1) There are three arrays instead of one. Since each light emitting element array (+1), (12), and (13) functions as described in the first embodiment, a multi-input, multi-channel selector is possible in the example shown in FIG. 11. In the above embodiment as well, the light emitting element (101) and the light receiving sensor (+02) do not necessarily need to be coupled through a lens, and a physical light shielding wall may be provided. Also, a multi-channel selector may have more channels than just the three channels mentioned above. Further, the light receiving element is not limited to the phototransistor described in the conventional example, but may be any other type including a photodiode.

【発明の効果】【Effect of the invention】

以上に述べてきたように、本発明では発光素子として自
己走査性機能を持った発光素子アレイを用いることによ
り、信号を送るべきセンサを選択して情報を伝達すると
いうチャネルセレクタの機能を集積化素子に担持させる
ことができる.また、素子の構造は簡略で、複雑な走査
素子を有しないため信頼性が高く、製造工程を簡略化出
来る.
As described above, in the present invention, by using a light emitting element array with a self-scanning function as a light emitting element, the channel selector function of selecting a sensor to send a signal and transmitting information is integrated. It can be supported on the device. In addition, the element has a simple structure and does not have a complicated scanning element, so it is highly reliable and the manufacturing process can be simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第l図は本発明の第1の実施例を示す構成図、第2図お
よび第3図は第1の実施例に用いた自己走査型発光素子
アレイの概略を示す断面図および平面図、第4図は第1
の実施例の動作を説明する駆動波形図、第6図,第6図
,第7図および第8図は自己走査型発光素子アレイの別
構成をしめず平面図,断面図,別方向断面図,および等
価回路図、第9図,第10図はさらに別の自己走査型発
光素子アレイの構成をしめず平面図および断面図、第1
1図は第2の実施例を示す構成図、第12図は従来のホ
トカブラを表す概念図である。 図中、 101  自己走査型発光素子アレイ +02  受光素子アレイ 100  結像レンズ である. 第 1 図 61光障壁 第 4 図 Y 第 5 図 第9図 第10 図
FIG. 1 is a block diagram showing the first embodiment of the present invention, FIGS. 2 and 3 are sectional views and plan views schematically showing the self-scanning light emitting element array used in the first embodiment, Figure 4 is the first
6, 6, 7, and 8 are plan views, cross-sectional views, and cross-sectional views in different directions showing different configurations of the self-scanning light emitting element array. , and equivalent circuit diagrams, FIGS. 9 and 10, which do not show the configuration of yet another self-scanning light emitting element array.
FIG. 1 is a block diagram showing a second embodiment, and FIG. 12 is a conceptual diagram showing a conventional photocoupler. In the figure, 101 self-scanning light emitting element array + 02 light receiving element array 100 imaging lens. Figure 1 Figure 61 Light barrier Figure 4 Figure Y Figure 5 Figure 9 Figure 10

Claims (2)

【特許請求の範囲】[Claims] (1)複数の発光素子と複数の受光素子とを用いて、電
気信号を一旦光の信号に変換して伝達させる発光・受光
モジュールにおいて、該複数の発光素子として自己走査
機能を有する発光素子アレイを用いたことを特徴とする
発光・受光モジュール。
(1) In a light-emitting/light-receiving module that uses a plurality of light-emitting elements and a plurality of light-receiving elements to convert an electrical signal into a light signal and transmit it, a light-emitting element array has a self-scanning function as the plurality of light-emitting elements. A light emitting/light receiving module characterized by using.
(2)該自己走査機能を有する発光素子アレイが、(a
)しきい電圧もしくはしきい電流が外部から制御可能な
発光素子を多数個、一次元、二次元、もしくは三次元的
に配列し、互いに近傍に位置する少なくとも2つの発光
素子を光学的手段で接続するか、または互いに近傍に位
置する少なくとも2つの発光素子の、しきい電圧もしく
はしきい電流を制御する制御電極を互いに電気的手段に
て接続し、各発光素子に電源ラインを電気的手段を用い
て接続すると共に、クロックパルスと該電気信号とを印
加させるクロックラインを接続した発光素子アレイ、ま
たは (b)しきい電圧もしくはしきい電流が外部から制御可
能な制御電極を有するスイッチ素子多数個を配列したス
イッチ素子アレイの各スイッチ素子の制御電極を互いに
電気的手段もしくは光学的手段にて接続し、かつ各スイ
ッチ素子に電源ラインを電気的手段を用いて接続すると
共にクロックラインを接続して形成した自己走査アレイ
と、しきい電圧もしくはしきい電流が外部から制御可能
な制御電極を有する発光素子多数個を配列した発光素子
アレイの各しきい電圧もしくはしきい電流を制御する電
極を前記スイッチ素子の制御電極と電気的手段にて接続
し、各発光素子に該電気信号を印加するラインを設けた
発光素子アレイ、 である請求項1記載の発光・受光モジュール。
(2) The light emitting element array having the self-scanning function is (a
) A large number of light emitting elements whose threshold voltages or threshold currents can be controlled externally are arranged one-dimensionally, two-dimensionally, or three-dimensionally, and at least two light-emitting elements located near each other are connected by optical means. Alternatively, control electrodes for controlling the threshold voltage or threshold current of at least two light emitting elements located near each other may be connected to each other by electrical means, and a power supply line may be connected to each light emitting element using electrical means. or (b) a large number of switch elements each having a control electrode whose threshold voltage or threshold current can be controlled from the outside. It is formed by connecting the control electrodes of each switch element of the arranged switch element array to each other by electrical means or optical means, and by connecting a power line to each switch element using electric means and also connecting a clock line. The switch element controls each threshold voltage or threshold current of a light emitting element array in which a large number of light emitting elements are arranged, each having a self-scanning array and a control electrode whose threshold voltage or threshold current can be controlled from the outside. 2. The light emitting/light receiving module according to claim 1, wherein the light emitting element array is connected to a control electrode of the light emitting element by electrical means and is provided with a line for applying the electric signal to each light emitting element.
JP19216289A 1989-07-25 1989-07-25 Light emitting / receiving module Expired - Fee Related JP2859649B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19216289A JP2859649B2 (en) 1989-07-25 1989-07-25 Light emitting / receiving module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19216289A JP2859649B2 (en) 1989-07-25 1989-07-25 Light emitting / receiving module

Publications (2)

Publication Number Publication Date
JPH0355885A true JPH0355885A (en) 1991-03-11
JP2859649B2 JP2859649B2 (en) 1999-02-17

Family

ID=16286719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19216289A Expired - Fee Related JP2859649B2 (en) 1989-07-25 1989-07-25 Light emitting / receiving module

Country Status (1)

Country Link
JP (1) JP2859649B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997012405A1 (en) * 1995-09-25 1997-04-03 Nippon Sheet Glass Co., Ltd. Surface light-emitting element and self-scanning type light-emitting device
JP2004259724A (en) * 2003-02-24 2004-09-16 Nippon Sheet Glass Co Ltd Light emitting element / light receiving element array and optical write head
US6919583B2 (en) 1998-11-04 2005-07-19 Nippon Sheet Glass Company, Limited End surface light-emitting element having increased external light emission efficiency and self-scanning light-emitting element array using the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4538896B2 (en) * 2000-05-24 2010-09-08 富士ゼロックス株式会社 Self-scanning light emitting device array

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180960B1 (en) 1995-04-12 2001-01-30 Nippon Sheet Glass Co., Ltd. Surface light-emitting element and self-scanning type light-emitting device
WO1997012405A1 (en) * 1995-09-25 1997-04-03 Nippon Sheet Glass Co., Ltd. Surface light-emitting element and self-scanning type light-emitting device
US6614055B1 (en) 1995-09-25 2003-09-02 Nippon Sheet Glass Co., Ltd. Surface light-emitting element and self-scanning type light-emitting device
US6919583B2 (en) 1998-11-04 2005-07-19 Nippon Sheet Glass Company, Limited End surface light-emitting element having increased external light emission efficiency and self-scanning light-emitting element array using the same
JP2004259724A (en) * 2003-02-24 2004-09-16 Nippon Sheet Glass Co Ltd Light emitting element / light receiving element array and optical write head
JP4631248B2 (en) * 2003-02-24 2011-02-16 富士ゼロックス株式会社 Optical writing head, optical printer, and light quantity correction method

Also Published As

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