JP2683781B2 - Light emitting device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a light emitting device having a switch element and a light emitting element that are integrated and formed, and more particularly to a light emitting device in which these elements have a self-scanning function. The present invention relates to a light emitting device applicable to an optical printer or the like.

[Conventional technology]

Previously, the inventors have proposed a light emitting device in which the light emitting element array itself has a self-scanning function, as disclosed in, for example, Japanese Patent Laid-Open No. 1-238962. A conventional example of such a light emitting device will be described below with reference to the drawings.

FIG. 4 is a plan view showing a conventional light emitting device, and FIG. 5 is a sectional view of a portion taken along the line XX 'in FIG. 4th
In FIG. 5 and FIG. 5, a light emitting element (light emitting thyristor)
T denotes an N-type semiconductor layer (N-type GaAs layer) 24b and an N-type semiconductor layer (N-type AlGaA) on the N-type semiconductor substrate (N-type GaAs substrate) 1 in this order.
s layer) 24a, P-type semiconductor layer (P-type GaAs layer) 23a, N-type semiconductor layer (N-type GaAs layer) 22a, P-type semiconductor layer (P-type AlGaAs)
Layer) 21b and a P-type semiconductor layer (P-type GaAs layer) 21a are laminated.

The light emitting element T has a separation groove 50 formed by photolithography, etching, etc.
It is separated into _(-1) , T ₍₀₎ , and T ₍₁₎ .

For each light emitting element T, the N-type GaAs substrate 1 becomes a cathode, the N-type GaAs layer 22a becomes a gate, and the P-type GaAs layers 21a and P
The AlGaAs layer 21b is an anode. The gate 22a of each light emitting element T has a contact hole C ₁ provided in the insulating protective film 30 and a metal thin film 4 for wiring provided on the insulating protective film 30.
1, contact hole C ₃ provided in insulating protection film 30, N-type GaA
s N stacked on the substrate 1 and separated from the light emitting element array
The GaAs layer 22a, the contact hole C ₃ , the metal thin film 41, and the contact hole C ₁ are connected to each other.

The gate 22a of each light emitting element T is connected to the power supply voltage V _GK via the metal thin film 42 for wiring provided on the insulating protection film 30.
Connected to the DC power supply. An insulating protective film 31 is provided on each light emitting element T.

On the other hand, the anode of each light emitting element T is provided in the contact hole C ₁ provided in the insulating protective film 30, the metal thin film 40 for wiring provided on the insulating protective film 30, and the insulating protective film 31 on the metal thin film 40. It is connected to the clock line through the contact hole C ₂ . The clock line, as shown in FIG.
_Three of CL _{1 to} CL 3 are provided. The anode of each light emitting element T is one of the clock lines CL _{1 to} CL _3.
It is connected to the book in the order of CL ₁ , CL ₂ , CL ₃ in the length direction.

Note that the clock line CL ₁ is supplied transfer clocks phi _1, the clock line CL ₂ is supplied transfer clocks phi _2. Further, the transfer clock φ ₃ is supplied to the clock line CL ₃ .

Further, in FIG. 4, the resistor 63 forms a resistor network connecting the respective gates. This resistance 63
Is provided by the light absorption block 62 so that the light from the light emitting element T does not enter the other light emitting elements T.

Furthermore, in FIG. 5, the P-type GaAs layer which is the active layer
23a and N-type GaAs layer 22a for confining carriers,
The active layers 23a and 22a are sandwiched between a P-type AlGaAs layer 21b having a large band width and an N-type AlGaAs layer 24a. With such a configuration, the luminous efficiency of the light emitting element T is improved.

Next, FIG. 6 is an equivalent circuit diagram of the conventional light emitting device shown in FIGS. 4 and 5. In FIG. 6, each light emitting element T
The gates G _{-2 to} G _{2 of (-2) to} T ₍₂₎ are electrically coupled to each other by the coupling resistor R ₁ . Further, the gates G _{-2 to} G ₂ of the light emitting elements T _{(-2) to} T ₍₂₎ are connected to the power supply line via the gate load resistors R _{L-2 to} R _L2 , respectively. A DC power supply with a power supply voltage V _GK is connected to this power supply line.

Note that the gate load resistor R _L2 to R _L2 is a resistor 63 shown in Figure 4, respectively. Gate load resistance R _L-2 ~
R _L2 limits the amount of current in the light emitting state (ON state) of the light emitting element due to the power supply voltage V _GK applied to each of the gates G _{-2 to} G ₂ .

Furthermore, the anode of the light-emitting elements T _(-2) ~T ₍₂₎ is connected to one clock line CL ₁ -CL _3, one of the transfer clock phi ₁ to [phi] ₃ can be applied . The cathodes of the light emitting elements T _{(-2) to} T ₍₂₎ are grounded.

 Next, the operation of the light emitting device having the above structure will be described.

Now, it is assumed that the transfer clock φ ₃ has a high level voltage and the light emitting element T ₍₀₎ is in an on state (that is, a light emitting state). At this time, the gate G ₀ of the light emitting element T ₍₀₎ becomes almost 0 volt. Therefore, a current flows through the resistance network in which the gates of the respective light emitting elements T are coupled. And the light emitting element T
_The gates G ₋₁ and G ₁ closer to ₍₀₎ have the lowest voltage drop, and the gates farther from the gate G ₀ have less influence.

For example, when a high level voltage is set for the next transfer clock φ ₁ , every three light emitting elements T ₍₁₎ and T _(-2) can be turned on. However, the gate G ₁ has a lower voltage than the gate G _-2 . Therefore, when the power supply voltage V _GK is set higher than the threshold voltage at which the light emitting element T ₍₁₎ operates and lower than the threshold voltage at which the light emitting element T _(-2) operates, only the light emitting element T ₍₁₎ is set. Can be turned on.

When this operation is repeated, the three clock lines CL _{1 to} C
The light emitting element T can be scanned (that is, information can be transferred) by using L ₃ .

As described above, the light emitting device shown in FIGS.
The turn-on voltage or current of a light emitting element is configured to be related to the ON state of another light emitting element (that is, to cause an interaction), thereby realizing the self-scanning function of light emission.

Generally, a light emitting device applied to an optical printer or the like needs not only the movement of the light emitting state but also the modulation of the light emission intensity. In the above self-scanning light emitting device, the emission intensity can be modulated by the driving method described below.

The principle of this driving method is shown in FIGS. 7 (a) and 7 (b).
Although not particularly shown in the circuit diagram shown in FIG. 7A, the gates of the respective light emitting elements T are connected by electrical means or optical means as shown in FIG.

Clock lines CL _{1 to} CL ₃ are provided on the anodes of the respective light emitting elements T.
Any one of them is repeatedly connected in the order of CL ₁ , CL ₂ and CL ₃ to the right in the figure. Also, clock line C
Current sources I ₁ , I ₂ , and I ₃ are connected to L ₁ , CL ₂ , and CL ₃ , respectively, and these I _{1 to} I ₃ are configured to be controllable by a control circuit signal φ ₁ . The start pulse φ _S is supplied to the light emitting element T ₍₋₃₎ .

Transfer clocks φ _{1 to} φ are provided on the clock lines CL _{1 to} CL _3.
A rectangular signal ₃ is supplied with a delay t _D for each time t. The transfer clocks φ _{1 to} φ ₃ are set to have a slight time overlap.

A rectangular start pulse φ _S is supplied to the light emitting element T ₍₋₃₎ , and a transfer clock φ ₁ having a slight overlapping time is supplied to the start pulse φ _S. Then, the transfer clocks φ ₂ and φ ₃ are sequentially supplied following the transfer clock φ ₁ . After that, φ _{1 to} φ ₃ are repeatedly supplied, so that the light emitting element array starts self-scanning.

Here, as the control circuit signal φ ₁ , the transfer clock φ ₁ ~
A signal synchronized with φ ₃ is supplied, and transfer clocks φ _{1 to} φ
Respectively superimposes the output current of the current source I ₁ ~I ₃ to _3. As a result, the light emitting element T in the light emitting state can emit light more strongly than the other light emitting elements T.

In FIG. 7 (b), in order to make the luminance L _R of the light emitting element T ₍₀₎ particularly strong, at the time t _{3 to} t ₄ when the light emitting element T ₍₀₎ becomes the light emitting state by self-scanning, the transfer clock φ ₃ current source I ₃ to
The output current I _{T of} is added. The self-scanning light emitting device described above can increase the luminance L _R at any position by such a method. Therefore, when applied to an optical printer or the like, it becomes possible to write image information in the light emitting device.

[Problems to be solved by the invention]

However, according to the above conventional technique, FIG.
As is clear from the light emission intensity (luminance) L _R shown in, the elements other than the light emitting element T ₍₀₎ for writing the image information also emit light to some extent (hereinafter referred to as bias light). This is because, when the on-state is transferred, light emission occurs due to the current for maintaining the on-state. Therefore, when the light emitting device is applied to an optical printer or the like, a certain amount of light is emitted to the whole. Therefore, there is a problem that the quality of image information is deteriorated.

Further, according to the above-mentioned conventional technique, in order to write the image information into the light emitting device, the number of current sources must be provided as many as the number of clock lines, which causes a problem that the driving circuit becomes complicated and expensive. there were.

Furthermore, according to the above-mentioned conventional technique, the average light emission intensity is low because the duty cycle of light emission of the light emitting element T is low. In this case, there is a problem that the life of the light emitting device is shortened if strong light emission is attempted.

That is, in the conventional self-scanning light emitting device, the number of the light emitting elements T in the ON state is always one, except when the transfer clocks overlap. Therefore, for example, if a 2048-bit light emitting device is configured, the light emission time per bit is 1/2048 of the total light emission. Therefore, if you try to get the same amount of light as when the duty cycle is 1, 20
It is necessary to temporarily pass a current of 48 times or more to each light emitting element T, which causes a problem that the life of the single light emitting element T is shortened.

[Means for solving the problem]

In order to solve the above-mentioned problems of the prior art, the light emitting device of the present invention includes a plurality of switch elements each having a first control electrode for externally controlling a threshold voltage or a threshold current for a switching operation. Are arranged,
Each of the first control electrodes is connected to each other by a first electric means, and a power supply line is connected to each of the switch elements by a second electric means, and information is transferred. And a switch element array in which a signal for writing information is supplied to a part of the plurality of switch elements, and a threshold voltage for light emission operation. Alternatively, a plurality of light emitting elements each having a second control electrode for externally controlling a threshold current are arranged, and each of the light emitting elements has a current supply line for supplying a current for causing the light emitting element to emit light. And a third electric hand for individually connecting the light-emitting element array connected to the switch, the first control electrode of the switch element and the second control electrode of the light-emitting element. And controlling the amount of the current supplied by the current supply line, information on the on / off state of each of the switch elements externally written in the switch element array is provided in the light emitting element array. The ON / OFF state information written to the light emitting element array is held for a desired period.

Preferably, in the light emitting device of the present invention, each of the switch element and the light emitting element is formed of an element having the same structure having a semiconductor PNPN structure.

More preferably, the light emitting device of the present invention is configured such that the third electrical means is a diode.

[Action]

The current supply line provided in the light emitting element array is used as a line for controlling the light emission of those light emitting elements. The switch element array (scanning circuit) for scanning and the light emitting element are separated, and the bias light generated by the switch element array is shielded. That is, the light emitting element can be made to emit light for a required time. Therefore, when the light emitting device according to the present invention is applied to an optical printer or the like, deterioration of the quality of image information is prevented.

That is, in the present invention, a conventional self-scanning light-emitting element array is used as a transfer (scanning) switch element array,
The light emitting function is separated into another light emitting element array having substantially the same structure. Therefore, a light shielding layer can be provided above the switch element array that transfers the ON state that causes the bias light. Then, the influence of the bias light on the writing of the image can be eliminated.

Further, since it is only necessary to provide a current source for modulating the emission intensity only in the line of the start pulse supplied to a part of the switch element, the number of current sources can be small,
The drive circuit portion does not become complicated, and thus the light emitting device can be constructed at low cost. That is, the image writing signal can be directly input to the switch element array as a part of the start pulse of the switch element, not to the conventional clock line, which simplifies the configuration of the drive circuit and reduces the cost.

Further, by controlling the amount of current supplied by the current supply line, image information written in the switch element array (information on the on / off state of the switch elements).
Are simultaneously written to the light emitting element array at a predetermined timing via the third electrical means. As a result, the light emitting element emits light, and the light emitting state is maintained as it is. Therefore, the image information remains held in the light emitting element until the light emitting device is reset by the scanning signal in the next period.

Therefore, the duty cycle of light emission is set to almost 1, and the current (peak value) flowing through the light emitting element can be reduced,
The life of the light emitting device can be extended.

Since the switch element and the light emitting element can be formed by elements having the same structure, the manufacturing process does not become complicated, and by changing the photoresist pattern, the conventional element manufacturing process can be used as it is.

〔Example〕

FIG. 1 is an equivalent circuit diagram showing an embodiment of the light emitting device of the present invention. In FIG. 1, the switch element array SDA
And the light emitting element array LMA are described separately above and below.

First, the switch element array SDA having a shift register function will be described. S _{(-2) to} S ₍₂₎ are switch elements (thyristors having a PNPN structure). φ ₁ and φ ₂ are transfer clocks for driving the switch element array SDA, respectively. CL ₁ is a clock line supplied with the transfer clock φ ₁ , and CL ₂ is a clock line supplied with the transfer clock φ ₂ . Each switch element S _(-2)
Between the gates G _{-2 to} G ₂ (first control electrode) of S ~ ₍₂₎ , coupling diodes D _{-2 to} D ₁ (first electrical means), respectively.
Connected by.

Since such a diode coupling system is adopted, the switch element array SDA can perform the information transfer operation with the two-phase transfer clocks φ ₁ and φ ₂ .

In addition, R _A1 and R _A2 are each switch element S _(-2) ~ S
It is an anode load resistance that connects the anode of ₍₂₎ and one of the clock lines CL ₁ and CL ₂ . The anode load resistors R _A1 and R _A2 are for limiting the amount of current in the ON state of each of the switch elements S _{(-2) to} S ₍₂₎ . The cathodes of the switch elements S _{(-2) to} S ₍₂₎ are grounded.

Furthermore, R _L1 and R _L2 are each switch element S _(-2) ~ S
It is a gate load resistance (second electrical means) that connects the gates G _{-2 to} G ₂ of ₍₂₎ and the DC power supply of the power supply voltage V _GK . The gate load resistors R _L1 and R _L2 limit the amount of current flowing from the DC power source of the power source voltage V _GK to the gates G _{-2 to} G ₂ . Each gate G _-2 , G ₀ , G ₂ is connected to the cathode of a diode D _-2 ′, D ₀ ′, D ₂ ′ (third electrical means), respectively.

In the switch element array SDA of FIG. 1, a switch element S ₍ not shown ₎ is provided on the left side of the switch element S _(-2).
(-3) is provided. The gate G _-3 of the switch element S _(-3) is connected to the gate G _-2 of the switch element S _(-2) by the coupling diode D _-3 (not shown) in the same manner as the coupling diode D _-2. It is connected. Also, this switch element S _(-3)
Gate G _-3 is connected to a DC power supply having a power supply voltage V _GK via a gate load resistor R _L-3 (not shown).

Further, the anode of the switch element S _(-3) has a start pulse φ _S via an anode load resistor R _A-3 (not shown).
Is connected to the terminal supplied. The cathode of S _(-3) is grounded. It should be noted that the above-mentioned terminal or line to which the start pulse φ _S is supplied is provided with a current source for modulating the emission intensity.
Illustration is omitted in the figure.

Next, the light emitting element array LMA will be described. φ _R is a clock (scanning signal) that controls permission / prohibition of writing information to the light emitting elements (light emitting thyristors) L _(-2) , L ₍₀₎ , and L ₍₂₎ and resets the written state. Is. Further, CL _R is a current supply line to which the clock φ _R is supplied.

Also, R _A3 each light emitting element _{L (-2), L (0} ), an anode load resistor connects the anode and the current supply line CL _R of L _(2). This anode load resistance R _A3 is applied to each light emitting element L _(-2) ,
This is for limiting the amount of current in the on-state of L ₍₀₎ and L ₍₂₎ . The cathodes of the light emitting elements L _(-2) , L ₍₀₎ and L ₍₂₎ are grounded.

Further, R _L3 is the gate (second control electrode) G ₋₂ ′, G ₀ ′, G ₂ ′ of each light emitting element L ₍₋₂₎ , L ₍₀₎ , and L ₍₂₎ and the power supply voltage V _GK . It is a gate load resistance that connects to a DC power supply. This gate load resistor R _L3 is connected to each gate from the DC power supply of power supply voltage V _GK.
It limits the amount of current flowing through G _-2 ', G ₀ ' and G ₂ '. Each gate G _-2 ', G ₀ ', G ₂ 'is connected to the anode of a diode D _-2 ', D ₀ ', D ₂ ' (third electrical means), respectively.

That is, in FIG. 1, the switch element S _(-2) ,
S _(0), the gate G _-2 to _{S (2), G 0,} G 2 are each diode D _-2 ', D _0', via the D ₂ ', the light emitting element L _(-2), L _{( 0)} ,
It is individually connected to the gates G _-2 ′, G ₀ ′ and G ₂ ′ of L ₍₂₎ .

Next, the operation of the switch element array SDA will be described.

Now, assume that a high-level or low-level voltage as the start pulse φ _S is supplied to the anode (not shown ₎ of the switch element S ₍₋₃₎ . In this case, if the high-level voltage is higher than the voltage obtained by adding the diffusion potential V _dif to the power supply voltage V _GK , the switch element S _(-3) is turned on. Then, then a low level voltage of the start pulse phi _S to be supplied is lower than the ON state maintaining voltage of the switching element S _(-3), switching element S _(-3) is turned off.

In the on state, the gate voltage of the switch element S _(-3) becomes almost 0 volt, and in the off state, the gate voltage is the power supply voltage V
It has the same voltage as _GK . When the gate voltage of the switch element S _(-3) becomes almost 0 volt, the gate voltage of the switch element S _(-2) is lowered by the coupling diode D _-3 (not shown). Then, the turn-on voltage of the switch element S _(-2) also drops. Therefore, the switch element S _(-2) can be turned on by the transfer clock φ ₂ .

This ON state is sequentially transferred to the right in FIG. 1 by the transfer clocks φ ₁ and φ ₂ . That is, the ON state is written in the switch element array SDA by the high level voltage of the start pulse φ _S , and the state is sequentially transferred to the right.

However, when all the bits are in the ON state, it is impossible to transfer this ON state due to the configuration of the present switch element array, and it is necessary to repeat ON and OFF every other bit. Become. That is, the start pulse φ
_{As for} the waveform of _S , it is necessary to alternately send the high level and the low level in synchronization with the transfer clocks φ ₁ and φ ₂ .

Now, assuming that there is valid information in the on and off states of only even bits, the on state is 1 and the off state is 0.
Then, 1 or 0 is written by the start pulse φ _S , and 1 or 0 is written by the transfer clocks φ ₁ , φ ₂ .
0 will be transferred. In this way, the signal (information) of 1 or 0 is written in the switch element array SDA.

Next, the operation of the light emitting elements L _(-2) , (L ₍₀₎ , L ₍₂₎ ) will be described.

If L _(-2) is 0, the light emitting element L _(-2) is not turned on if the voltage of the clock φ _R is 0 volt. That is, the light emitting element L _(-2) is set to the write-protected state. When the voltage of the clock phi _R is set to a voltage between V _GK + V _dif from the ON state maintaining voltage of the light emitting element L _(-2), the light emitting element L _(-2) is set to the state of the write permission. Then, by changing the voltage of the gate G _-2 ', the light emitting element L _(-2) can be set to the ON state.

Now, switch element array SDA to light emitting element array LMA
Writing of information to the memory will be described.

Information of 1 or 0 is written in the switch element array SDA as described above. At the stage where information has been written up to the last bit, the transfer clocks φ ₁ and φ ₂ are maintained at low level and high level, respectively. This completes the information transfer operation, and the switch element array SDA
The information written in is retained (especially in even bits).

In the even-numbered bits of the switch element array, the gate voltage of the switch element S in the ON state is almost zero volt,
The gate voltage of the switch element S in the off state is about twice the V _dif or more. The gate voltage of the switch element S in the off state is about twice the voltage V _dif when the adjacent even bit located in the opposite direction to the transfer direction is in the on state, and V _It is greater than about twice the voltage of _dif . Here, V _dif is the diffusion potential of the PN junction.

Switching element S _(-2), S _(0), S respective gate voltages of ₍₂₎ the diode D _-2 ', D _0', the light emitting element L _(-2) corresponding with D ₂ ', L _{( 0)} , the gate of L ₍₂₎ G _-2 ′, G ₀ ′,
It is transmitted to G ₂ ′. Therefore, the light emitting elements L _(-2) , L ₍₀₎ , L
The gate voltage of ₍₂₎ is V _{dif in} the on state and is 3 times or more of V _{dif in} the off state. The turn-on voltage of the light emitting element is twice V _{dif in} the on state, and is four times V _{dif in} the off state.

On the other hand, the clock φ _R is once set to zero volt so as to eliminate the light emission (that is, reset), and then is raised to the high level voltage V _HR . This voltage V
_{When HR} is set within the range of 2V _dif <V _HR <4V _dif , the switching element S in the ON state is
The light emitting element L corresponding to is turned on, and the light emitting element L corresponding to the switch element S in the off state remains in the off state.

Therefore, 1 written in the switch element array SDA,
The information of 0 is directly written in the light emitting element array LMA.

After that, the voltage V _HR is reset to a value that is equal to or higher than the on-state maintaining voltage of the light emitting element and less than twice the voltage V _dif . As a result, the light emitting element L is not affected by the gate voltage of the switch element S and continues to hold the written information. Then, while the light emitting element array LMA is in the information holding state, the switching element array SDA is performed in the same manner as described above.
Is written with the following information:

Eventually, the clock φ _R is set to a low level voltage, and each light emitting element L is reset. After the reset, the information is written in the light emitting element array LMA again. As described above, a series of operations is repeated.

Next, a case where the light emitting device shown in FIG. 1 is applied to a writing light source for an optical printer will be described.

For example, if the light emitting device has a light emitting element L of 2048 bits, the switch element S requires twice as many as 4096 bits. Since the current amount of the writing light source in the optical printer is about 5 mA, if the light emitting elements L of all the bits are in the light emitting state, a current of about 10 A flows. On the other hand, it is experimentally known that the current for transferring information from the switch element S is 0.5 mA when the gate load resistance R _L3 is 30 kΩ, so that the light emitting elements L of all bits are in the light emitting state. If there is, it is about 1A.

The current amount for this information transfer is 10% compared to the current 10A required for optical printing, which is a value that poses no practical problem.

Further, when the information from the switch element S is moved to the light emitting element L, the voltage of the transfer clocks φ ₁ and φ ₂ is once reduced to 0 volt, so that the switch element array is formed.
The entire SDA is turned off and reset. When this method is used, the amount of current equivalently decreases when the time during which the switch element S is in the ON state is taken into consideration. That is, the current amount is equivalently reduced to about 0.5 A as compared with 1 A described above.

Start pulse φ for 2048 bits of light emitting element L
_With only one data input (not shown) supplied with _S , the transfer rate of information needs to be fairly high. In this regard, the information transfer rate can be reduced by providing a plurality of data input terminals.
For example, a chip of the light emitting element L may be formed with 64 bits or 128 bits as one unit, and information may be input for each chip.

2 when inputting information every 128 bits in parallel
There will be 20 data inputs for 048 bits. Therefore, the transfer rate of information is 1/20. Therefore, the light emitting device can perform a sufficient operation.

Note that the anode load resistance R _A3 can be finely adjusted using a laser or the like in order to prevent variations in the amount of output light in the light emitting element L. As a result, it is possible to obtain a light emitting device in which the amount of output light does not vary.

Further, in FIG. 1, the coupling diodes D _-2 , D connected to the right side of the even-numbered bit in the switch element array SDA.
The characteristic of ₀ is different from the characteristic of the coupling diodes D _-1 and D ₁ connected to the right side of the odd bit. Therefore, it is important to optimize the operating current and the like for the even-numbered bit and the odd-numbered bit. Therefore, it is preferable to set R _L2 <R _L1 and R _A1 <R _A2 . In this case, the light emitting device can perform stable and high-speed operation.

Furthermore, in FIG. 1, a configuration called a diode coupling method is adopted, but the coupling method is not limited to this.
For example, a resistance coupling method using a resistor R ₁ as shown in FIG. 6 or an optical coupling method using the light emitting function and the light receiving function of the switch element S may be used.

In FIG. 1, the number of transfer clocks is two (2
However, the number of phases may be three or more (three phases). However, when the switch element S is driven by three phases, the 1-bit light emitting element L corresponds to the 3-bit switch element S.

Further, normally, a direct transition type semiconductor typified by GaAs is used when manufacturing such a light emitting device, but the invention is not necessarily limited to this.

Next, FIG. 2 is a sectional view showing an example in which the equivalent circuit shown in FIG. 1 is formed on the same semiconductor substrate. In FIG. 2, 71 is an N-type semiconductor substrate, 81 is a P-type semiconductor layer, 82 is an N-type semiconductor layer, and 83 is a P-type semiconductor layer.
The same components as those in FIG. 1 are designated by the same reference numerals.

Important points in the embodiment shown in FIG. 2 are the switch element S and the coupling diodes D _{-2 to} D ₁ and D _-2 'to that shown in FIG.
D ₂ ′, light emitting element L, etc. are semiconductor layers 81, 82, 83, semiconductor substrate
The circuit configuration of FIG. 1 can be integrated and formed without complicating the manufacturing process.

For example, in the switch element S _(-2) , the uppermost P-type semiconductor layer 81 serves as an anode and the N-type semiconductor layer 82 serves as a gate G.
_-2 , and the N-type semiconductor substrate 71 is the cathode.
Then, a P-type semiconductor layer formed on the N-type semiconductor layer 82
The two islands of 81 are coupling diodes D _-2 and D _-2 '. These diodes D _-2 and D _-2 'are the switching elements S
_It has the same structure as _(-2) and is formed by the same manufacturing process as S _(-2) .

Further, for the light emitting element L _(-2) , the switching element S _(-2)
It has exactly the same structure as, and is also formed in the same manufacturing process.

The resistors R _{A1 to} R _A3 and R _{L1 to} R _L3 can be formed by thin film resistors, or can be formed by using the semiconductor layers 81, 82, 83. Further, although a light shielding layer is provided on the upper part of the switch element S, it is omitted in FIG. With such a structure shown in FIG. 2, the light emitting device can perform exactly the same operation as that described with reference to FIG.

Further, in the structure of FIG. 2, a device of a mode using natural light emission is illustrated as a light emitting element, but even a mode by stimulated emission (that is, a laser mode) operates without any problem.

Next, FIG. 3 is a plan view showing an example of the planar structure of FIG. In FIG. 3, the same components as those in FIGS. 1 and 2 are designated by the same reference numerals. As shown in FIG.
The switch element array SDA and the light emitting element array LMA are arranged separately on the upper and lower sides. Then, the resistors R _{A1 to} R _A3 , R _L1
~ R _L3 is formed by a thin film resistor (semiconductor layer 81
It can also be formed using ~ 83).

Although a light shielding layer for shielding bias light is provided above the switch element S, it is omitted in FIG.

In FIG. 3, one light emitting element L is provided for two switch elements S, and the arrangement pitch of the light emitting elements L is twice the arrangement pitch of the switch elements S. For this reason, it seems that the degree of integration does not increase, but this point can be solved by arranging the switch elements S in two rows in a zigzag manner. Further, by providing another switch element array SDA on the opposite side of the light emitting element array LMA, the arrangement pitch of the light emitting elements L can be reduced.

In the above embodiment, the method of stacking the semiconductors was changed from the top.
Although the case of using PNPN has been described, the same operation can be performed even when using NPNP by reversing the polarities of the operating voltage and the transfer clock.

Further, in the above embodiment, the PNPN type thyristor structure has been described as an example of the portion having the shift register function. However, the structure for detecting the voltage and utilizing the fact that the threshold voltage drops to perform the information transfer operation Is not particularly limited as long as it is an element that can configure its function. For example, the completely same shift register function can be achieved not only by the four-layer structure of PNPN but also by the structure of six or more layers.

Furthermore, although the PNPN type thyristor structure has been described as an example in the above embodiment, the same function can be achieved by using an electrostatic induction (SI) thyristor or an electric field control thyristor (FCT).

Although the case where the grounded semiconductor substrate is used has been described in the above embodiment, the present invention is not limited to this, and another substance may be used as the substrate. For example, an N-type GaAs layer may be formed on a semi-insulating GaAs substrate doped with chromium (C _r ) or the like, and the structure described in the above embodiment may be formed on this layer. Further, a semiconductor film may be formed on an insulating substrate such as glass or alumina, and the structure described in the above-mentioned embodiment may be formed using this semiconductor film.

〔The invention's effect〕

As described above, the light emitting device of the present invention uses the conventional self-scanning light emitting device as the transfer switch array and separates the light emitting function into another light emitting element array having substantially the same structure. A light-shielding layer can be provided above the switch element that performs the transfer of the ON state, which is the cause, and the influence of bias light on the writing of image information can be eliminated. Therefore, when the light emitting device is applied to an optical printer or the like, the quality of the optical printer or the like can be improved.

Further, the signal for writing the image information can be directly input to the switch element as a part of the start pulse, instead of being supplied to the clock line as in the conventional technique.
Therefore, the drive circuit is simplified and the cost is reduced.

Further, since the information written in the light emitting element is maintained until it is reset by the scanning signal (clock φ _R ), the duty cycle of light emission is set to approximately 1.
Therefore, the current (peak value) flowing through the light emitting element can be reduced, and the life of the light emitting device can be extended.

By providing the light emitting element array, a light emitting device having a light emission duty cycle of about 1 can be realized by a relatively simple manufacturing process.

In addition, the light emitting device of the present invention can be applied to displays and the like, and can greatly contribute to performance improvement and cost reduction of these devices.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing an embodiment of a light emitting device of the present invention, FIG. 2 is a sectional view showing an example in which the equivalent circuit of FIG. 1 is formed on the same semiconductor substrate, and FIG. 2 is a plan view showing an example of the plane structure of FIG. 2, FIG. 4 is a plan view showing the structure of a conventional light emitting element array, FIG. 5 is a sectional view taken along line XX ′ of FIG. 4, and FIG. 4 and 5 equivalent circuit diagram,
FIGS. 7A and 7B are views for explaining a conventional method for driving a light emitting element array. In the reference numerals used in the drawings, SDA ...... switch element array S _{(-2) to} S ₍₂₎ ...... switch element C _{L1 to} C _L2 ...... clock line G _{-2 to} G ₂ ...... gate (first the control electrode) D _-2 ~D ₁ ...... coupling diode (first electrical means) R _L1 ~R _L2 ...... gate load resistor (second electrical _{means) G -2 ', G 0'} , G ₂ ′ …… Diode (third electrical means) LMA …… Light emitting element array L _(-2) , L ₍₀₎ , L ₍₂₎ …… Light emitting element CL _R …… Current supply line G _-2 ′ , G ₀ ′, G ₂ ′ ... Gate (second control electrode).

Claims (3)

(57) [Claims] 1. A plurality of switch elements each having a first control electrode for externally controlling a threshold voltage or a threshold current for a switching operation are arranged, and each of the first control electrodes is arranged. Are connected to each other by a first electric means, power supply lines are connected to the switch elements by a second electric means, and a clock line for transferring information is provided in each of the switches. A switch element array that is connected to the elements and supplies a signal for writing information to a part of the plurality of switch elements, and a threshold voltage or threshold current for light emission operation is externally controlled. A plurality of light emitting elements each having a second control electrode for arranging, and a current supply line for supplying a current for causing the light emitting elements to emit light is provided in front of each of the plurality of light emitting elements. A light emitting element array connected to the light emitting element, and a third electrical means for individually connecting the first control electrode of the switch element and the second control electrode of the light emitting element. In addition, by controlling the amount of the current supplied by the current supply line, the on / off state information of each of the switch elements, which is externally written to the switch element array, is written to the light emitting element array. In addition, the light emitting device is configured so that the on / off state information written in the light emitting element array is retained for a desired period. 2. The switch element and the light emitting element,
The light emitting device according to claim 1, wherein the light emitting devices are formed of elements having the same structure, each having a semiconductor PNPN structure. 3. The light emitting device according to claim 1, wherein the third electrical means is a diode.