JP5245897B2 - Self-scanning light emitting element array chip, optical writing head, and optical printer - Google Patents

Description

The present invention relates to a self-scanning light emitting element array chip , an optical writing head, and an optical printer .

  A light emitting element array in which a large number of light emitting elements are integrated on the same substrate is used as an optical writing head such as an optical writing head in combination with a driving IC. The inventors have paid attention to a three-terminal light-emitting thyristor having a PNPN structure as a constituent element of the light-emitting element array, and have already applied for a patent (see Patent Documents 1, 2, 3, and 4) that self-scanning of the light-emitting point can be realized. It has been shown that it is easy to mount as an optical printer head, that the light emitting element pitch can be made fine, and that a compact self-scanning light emitting element array (SLED) can be produced.

  Furthermore, the present inventors have proposed a multi-point lighting type self-scanning light-emitting element array separated from a light-emitting element (light-emitting thyristor) array that is a light-emitting part using a switch element (light-emitting thyristor) array as a shift part ( (See Patent Document 5).

JP-A-1-238996 Japanese Patent Laid-Open No. 2-14584 Japanese Patent Laid-Open No. 2-92650 JP-A-2-92651 Japanese Patent No. 2683781

FIG. 1 shows an equivalent circuit diagram of this multi-point lighting type self-scanning light emitting element array chip. This self-scanning light emitting element array includes a shift unit 1 including thyristors T ₁ , T ₂ , T ₃ ,... And a light emitting unit 2 including thyristors L ₁ , L ₂ , L ₃ ,. The configuration of the shift unit uses a diode connection. That is, the gates of the thyristors are coupled by the diodes D ₁ , D ₂ ,. _VGA is a power supply, and is connected to the gate of each shift unit thyristor through a load resistance _RL from a power supply wiring 117. The gates of the odd-numbered shift unit thyristors are also connected to the gates of the corresponding light emitting unit thyristors. The gate of the shift unit thyristor T1 is connected to the image data phi _S input terminal via a resistor R _S for current limiting. The cathode of the shift unit thyristor is connected to two transfer clock pulse φ1, φ2 wirings 210, 211 alternately through current limiting resistors R1, R2, respectively.

The cathode of the light emitting unit thyristor through a resistor R _I current limiting, and is connected to the light emitting signal phi _I wirings 215.

  In FIG. 1, the clock pulse has two phases φ1 and φ2, but may have three or more phases. In general, in a multi-point lighting self-scanning light emitting element array, when the clock pulse is set to M phase, there are only M light emitting unit thyristors for every M, so that M + 1 light emitting unit thyristors are required per pixel and integrated. It was difficult to increase the degree. Further, the shift unit thyristor has a problem that data transfer is slow because data can be written only every M pieces.

Further, when this multi-point lighting type self-scanning light-emitting element array is used as an optical printer head, if the substrate on which the self-scanning light-emitting element array chip is mounted and the driving circuit board are separated, one piece per chip is used. image data phi _S line must be removed from the chip mounting board. For example, M = 4 chips 60 optical printer head (1200 dpi, 256 at 60 chip of the light emitting points, corresponding to the size of the head A3) using the data phi _S wiring 60 present, other drive lines A total of 67 wires are required, including 7 wires (φ1 to φ4, V _GA , GND, φ _I ).

In addition, since this multi-point lighting type self-scanning light emitting element array has a structure in which all the light emitting points can be turned on at the same time, when all the light emitting points of one chip 256 are turned on, a current of 10 mA flows through each light emitting point. , the light emission signal phi _I lines becomes to flow a current of 2.56A, φ _I wiring is required considerable current capacity. Further, even if the head is 150A in 60 chips, a driver for driving the phi _I wiring still require significant drive capability.

  An object of the present invention is to provide a self-scanning light emitting element array chip having a high image data transfer rate.

  Another object of the present invention is to provide a self-scanning light emitting element array chip capable of reducing the number of wirings of an optical writing head.

  Another object of the present invention is to provide a self-scanning light emitting element array chip having a structure in which all of the light emitting points do not light simultaneously.

  Another object of the present invention is to provide an optical writing head using the self-scanning light emitting element array chip as described above.

  Another object of the present invention is to provide a driving method of the self-scanning light emitting element array chip and the optical writing head.

  Another object of the present invention is to provide an optical printer using the above optical writing head.

According to the first aspect of the present invention, P + 1 (P is an integer) first three-terminal light-emitting thyristors are arranged one-dimensionally, the gates of adjacent first thyristors are connected to each other by a diode, and each gate is connected to a gate load. Connect to the power supply wiring via a resistor, and connect the anode / cathode of each first thyristor to M clock pulse wirings that provide M-phase (M is an integer of 2 or more) clock pulses via the resistance. A shift unit in which the image data input terminal is connected to the gate of the first first thyristor and the P second three-terminal light-emitting thyristors are arranged one-dimensionally in a one-dimensional manner. Connecting the gates of the thyristors to the gates of the second to first thyristors corresponding to the shift unit, and dividing the P second thyristors into N groups of P / N consecutive, N luminous signals A self-scanning light-emitting device comprising: a light-emitting unit that connects the anode / cathode of each second thyristor of the n-th group (1 ≦ n ≦ N) to the n-th light-emitting signal wiring through a resistor with respect to the line; It is an element array chip.

The invention according to claim 2 is the self-scanning light-emitting element array chip according to claim 1, wherein the N are two, and the anode / cathode of each second thyristor in one group is connected to a resistor. A self-scanning light-emitting element array chip in which the second light-emitting signal wiring is connected to the first light-emitting signal wiring through the resistor, and the anode / cathode of each second thyristor in the other group is connected to the second light-emitting signal wiring through the resistor. is there.

The invention according to claim 3 is a plurality of self-scanning light emitting element array chips according to claim 2 arranged in a one-dimensional manner, and one common power supply wiring to which the power supply wirings of all the chips are connected. One first common light emission signal wiring to which the first light emission signal wirings of all the chips are connected and one second common light emission signal wiring to which the second light emission signal wirings of all the chips are connected The light emitting signal wiring and the plurality of chips are divided into M consecutive blocks, and M clock pulse wirings of the chips of each block are connected to each other by shifting the phase one by one. An optical writing head including wiring and a plurality of common data wirings to which image data input terminals of all chips in each block are connected.

According to a fourth aspect of the present invention, a plurality of self-scanning light emitting element array chips according to the second aspect arranged in a one-dimensional manner, and one common power source wiring to which the power source wirings of all the chips are connected, The driver circuit for supplying the first and second light emission signals to the first and second light emission signal wirings of each chip, and the plurality of chips are divided into M consecutive blocks. M clock pulse wirings of M chips connected to each other by shifting the phase one by one, and a plurality of common data to which image data input terminals of all the chips of each block are respectively connected. And an optical writing head comprising wiring.

According to a fifth aspect of the present invention, the driver circuit receives a data signal and outputs a signal to a plurality of parallel outputs, OR of each output of the shift register and a data width signal. The optical writing head according to claim 4 , further comprising a gate and a current buffer that outputs a light emission signal based on an output of the OR gate.

According to a sixth aspect of the present invention, a plurality of self-scanning light emitting element array chips according to the second aspect arranged in a one-dimensional manner, and one common power supply wiring to which the power supply wirings of all the chips are connected, The common light emission signal wiring to which the light emission signal wirings of all the chips are connected and the plurality of chips are divided into M consecutive blocks, and M clock pulse wirings of the chips of each block M common clock pulse wirings that are connected with a phase shift by one, a plurality of common data wirings to which image data input terminals of all chips of each block are connected, and light emission permission of each chip And a driver circuit that supplies a light emission permission signal to the signal wiring.

According to a seventh aspect of the present invention, the driver circuit includes a shift register that receives a data signal and outputs signals to a plurality of parallel outputs, and a light emission permission signal based on each signal output from the shift register. The optical write head according to claim 6 , further comprising: a current buffer that outputs a current buffer.

The invention according to claim 8 is an optical printer using the optical writing head according to claim 3, 4 , 5 , 6 or 7 .

  According to the present invention, it is possible to provide a self-scanning light-emitting element array chip that has a high image data transfer speed and that does not emit all the light emitting points simultaneously. A self-scanning light-emitting element array chip that can be reduced can be provided.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an equivalent circuit of the self-scanning light emitting element array chip having 256 light emitting points in this embodiment. In this example, four-phase clock pulses φ1, φ2, φ3, and φ4 are used. As can be seen from the figure, the shift unit thyristor T and the light emitting unit thyristor L have a one-to-one correspondence. In the figure, 1 indicates one unit constituting the shift unit, which is composed of a thyristor 41, resistors 42 and 44, and a diode 43, and 2 indicates one unit constituting a light emitting unit, which is composed of a thyristor 45 and a resistor 46. Also in the figure, the power supply _{V GA} terminal 17, the data phi _S input terminal 14, the clock pulse φ1 terminal 10, a clock pulse φ2 terminals 11, 12 clock pulses φ3 terminal, a clock pulse φ4 pin 13, 18 GND Terminal. 47 is a current limiting resistor connected to the data phi _S input terminal 14.

φ _I wiring is divided into left and right in the middle. The left side of phi _I wiring 215, showing the right side of phi _I wiring 216. These wires are left phi _I L terminals 15 are connected to the right side of phi _I R terminal 16.

  A structure in which the chip of FIG. 1 is realized by a PNPN structure on a p-type substrate is shown in FIGS. FIG. 3 is a plan view of the chip, and FIGS. 4A and 4B are a plan view and a cross-sectional view taken along line XX showing one unit of the shift unit and one unit of the light emitting unit corresponding one-to-one. FIG.

  In this self-scanning light emitting element array chip, a p-type GaAs anode layer 31, an n-type GaAs gate layer 32, a p-type GaAs gate layer 33, and an n-type GaAs cathode layer 34 are sequentially stacked on a p-type GaAs substrate 30. PNPN structure is formed. In the figure, 35 is an n-type ohmic electrode, 36 is a p-type ohmic electrode, and 37 is a back electrode.

  Examples of drive waveforms for driving the self-scanning light emitting element array chip of FIG. 2 are shown in FIGS. The waveforms are continuous in the order of FIG. 5, FIG. 6, FIG. 7, and FIG.

Image data phi _S, when the clock pulse φ1 is an H at the timing at which L, the shift unit thyristor T ₁ is turned on. Further, when the data phi _S L, and the shift unit thyristor T ₁ is not turned on. The on state of the thyristor T ₁ is shifted to the thyristor T ₂ when the clock pulse φ ₂ becomes L, and the on state is shifted from the thyristor T ₃ to the thyristor T ₄ by sequentially setting the clock pulses φ 3 and φ ₄ to L. Then, when the clock pulse φ1 becomes again L, the ON state passes to the thyristor T _5, by giving data phi _S to the data phi _S terminal 14 at this timing, it determines the on / off thyristors T _1. This operation is repeated, where the initial data has moved to the thyristors T _256, as shown in FIG. 5, to fix the voltage of the clock pulse φ4 to L (clock pulse φ1~φ3 is H), a light emission signal phi _{I L} When L, the light emitting unit thyristor L _4n (n = 1 to 32) corresponding to the shift unit thyristor that is turned on is turned on simultaneously. Subsequently, by setting the light emission signal φ _I L to H and then setting the light emission signal φ _I R to L, the thyristor L _4n (n = 33 to 64) is turned on simultaneously.

Then the clock pulse φ1~φ4 and emission signals phi _{I R,} After all the phi _{I L} H, as shown in FIG. 6, moves the first data until thyristor T ₂₅₅ while applying data to the data phi _S terminal 14 The voltage of the clock pulse φ3 is fixed at L (clock pulses φ1, φ2, and φ4 are H), and the thyristor L _4n−1 (n = _{1 to} 32 and 33 to 64) is turned on.

Subsequently, as shown in FIG. 7, when the thyristor T _{254 is} reached, the voltage of the clock pulse φ2 is fixed to L (clock pulses φ1, φ3, and φ4 are H), and the thyristor L _4n−2 (n = 1 to 32). And 33 to 64) are turned on.

Then, as shown in FIG. 8, when the thyristor T _{253 is} reached, the voltage of the clock pulse φ1 is fixed to L (clock pulses φ2, φ3, and φ4 are H), and the thyristor L _4n-3 (n = 1 to 32). And 33 to 64) are turned on.

  With the structure and driving method as described above, 256 light-emitting points can be lit up to 32 times in 8 steps. Therefore, a large current does not flow through the light emitting signal wirings 215 and 216 of the chip.

  FIG. 9 shows a configuration of an optical printer head using the self-scanning light emitting element array chip. FIG. 9A shows an arrangement of terminals (bonding pads) of one chip, and FIG. 9B shows an equivalent circuit of the optical printer head. In FIG. 9A, reference numeral 60 denotes an emission point array.

  When assembling the optical printer head, four chips were connected as one block. Here, the number of chips is determined in accordance with the number of four clock wirings φ1 to φ4. In FIG. 9B, the chips are drawn from # 1 to # 10, but the chips # 1 to 4 are the first block and the chips # 5 to 8 are the second block.

First, the light emission signal phi _I L terminals 15 of all the chips, the light emission signal phi _I R terminal 16, a power supply _{V GA} terminal 17, the backside common electrode terminal 18, respectively phi _I L wiring 115, phi _I R wiring 116, the power supply V _{The GA} wiring 117 and the GND wiring 118 are connected.

The data φ _S terminal 14 of the first block chip is connected to the first data φ _S wiring 114-1, and the data φ _S terminal 14 of the second block chip is connected to the second data input wiring 114-2. 3 blocks of chips of the data phi _S terminal 14 is connected to a third data input lines 114-3.

  The clock pulse φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the first chips # 1 and # 5 of the first and second blocks are respectively connected to the clock pulse wirings 110, 111, 112, and 113, respectively. It is connected.

  The clock pulse φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the second chips # 2 and # 6 of the first and second blocks are respectively connected to the clock pulse wirings 111, 112, 113, and 110, respectively. It is connected.

  The clock pulse φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the third chips # 3 and # 7 of the first and second blocks are respectively connected to the clock pulse wirings 112, 113, 110, and 111, respectively. It is connected.

  The clock pulse φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the fourth chips # 4 and # 8 of the first and second blocks are respectively connected to the clock pulse wirings 113, 110, 111, and 112, respectively. It is connected.

Now, the voltage waveform shown in FIG. 10 in the chip sequence φ (110), φ (111 ), φ (112), φ (113), φ S (114), φ I L (115), φ I R (116 )give. The numerals indicate the wiring numbers in FIG.

Since the connections of the clock pulse wirings 110 to 114 and the clock pulse terminals 10 to 14 are different for each chip, the voltage waveforms received by the chips # 1 to # 4 are as shown in FIGS. That is, by the clock pulse phi (110) is L, the chip # 1 clock pulse φ1 is L, the image data phi _S (114-1) first data _{S 1} is chip # 1 of the shift unit thyristors T of the ₁ is read. Then by a clock pulse φ2 of the chip # 1 is L, the first data S ₁ is transferred to the shift section thyristor T ₂ of the chip # 1, image data phi _S to the shift unit thyristors T ₁ of the chip # 2 at the same time (114-1) second data _{S 2} is read in. Thus, in order data of the image data phi _S (114-1) is read into the shift unit thyristors _{T 1} of the respective chips # 1 to # 4, will be sequentially transferred to the next. As a result, the image data, which is serial data, is developed as an on / off state on the shift unit thyristor of each chip in the last position. When the first data S ₁ is reached to the last bit of the chip # 1 (256 number), stop the transfer, emission signals φ and _{I L} is L, each chip # 1 to # emission point shift section information of the left half of the 4 Outputs with or without. Subsequently, after setting the light emission signal φ _I L to H and then setting the light emission signal φ _I R to L, the shift part information on the right half of the chip is output by light emission / non-light emission of the light emitting point.

  Next, once all clock pulses are set to H and all data is reset, this time, as shown in FIG. 15, L in the order of clock pulses φ (111), (112), (113), (110). While adding the waveform, the image data is developed on the chip and the light emitting unit is turned on.

  Subsequently, as shown in FIG. 16, the image data is developed on the chip while adding the waveforms of L in the order of the clock pulses φ (112), (113), (110), and (111), and the light emitting unit Lights up.

  Finally, as shown in FIG. 17, the image data is developed on the chip while adding the waveforms of L in the order of clock pulses φ (113), (110), (111), (112), and the light emitting unit is By giving a waveform to be lit, all data handled by four chips in one line is developed on the chip and output as light emission.

  FIG. 18 shows how the data is developed at this time. In the figure, vertical columns represent chips # 1 to # 4. The chip # 1 is assigned an address [00], the chip # 2 is [01], the chip # 3 is [02], and the chip # 4 is [03]. The horizontal row indicates the light emitting point number of each chip. The light emitting point numbers are assigned so that the data terminal side has a smaller number. The number of emission points was 256, and the addresses were [00] to [FF]. The notation of each d (xxyy) indicates the image data (0/1) of the light emitting point at the address [yy] of the chip at the address [xx].

  In FIG. 18, data expansion is performed from the light emission point d (00FF) of the upper left block to the light emission point d (0200) of the lower right block as indicated by an arrow.

When the data expansion of FIG.
P number of light emitting points / chips, as Q chips / block, the data to be written to C-th N-th light emitting points of the chip, the D-th data when transmitted serially over a single data phi _S lines Correspondingly,

  It becomes. Note that Q is selected to be equal to the number M of clock pulse phases.

  Actually, this data expansion is not one way, but depending on which chip starts to give data, picks up data in the upper right direction (example in FIG. 18), or picks up data in the upper left direction. There is a deployment method. For this reason, more generally,

  In addition, it is necessary to change how to give the clock pulses φ1 to φ4 depending on the order of data. Further, it is not always necessary to arrange the chips in the order of the chip numbers.

  Further, the data may be sent in two or more times. For example, in FIG. 18, data is written at a rate of 1 for 4 light emitting points, but may be written at a rate of 1 for 8 light emitting points as shown in FIG. By writing the data separately in this way, the number of light emitting points that are turned on at the same time is reduced, so that the light output of the head is reduced. However, the maximum drive current can be reduced, so that the capacity of the drive circuit can be reduced.

Now, when printing at 1200 dpi, A3 horizontal size at 100 sheets per minute (500 mm / s) using the data development method of FIG. 18, the time given to one line is about 61.4 μs. Since one line is drawn by four times of data development / exposure, the time given to one time is 61.4 / 4 = 15.4 μs. Now, one data development requires 50 ns for one transfer and 12.8 μs. Therefore, the time given to the exposure is 15.4-12.8 = 2.6μs, since dividing the emission signal phi _I line to the left and right, the exposure time of t = 1.3 .mu.s. When the light output per light emitting point is p = 50 μW and the pixel area S = (21.15 μm) ² , the exposure amount is pt / S = 0.14 J / m ² . Further, when a rod lens having a transmittance of 4% is used for imaging, the exposure amount is 5.5 mJ / m ² . This is an exposure amount sufficient to expose a standard photosensitive drum.

  In this embodiment, an example of the self-scanning light-emitting element array chip divided into two groups has been described. However, the same effect can be obtained even if there is one or three or more groups.

In Example 1, by using a self-scanning light-emitting element array chip with the M clock pulse wire, the M chips by one block, the number of data phi _S line 114 by one per M chip I finished it. In this embodiment, to avoid a single data phi _S wired to 2M chips.

An equivalent circuit diagram of such a self-scanning light emitting element array chip is shown in FIG. In this circuit, the thyristor T ₀ of the shift portion Tsukekuwawari in the equivalent circuit of FIG. 2, connection of the shift unit thyristors are shifted one by one to the clock pulses φ1~φ4 wiring. The chip connection is a chip # 1 to # 8 as shown in FIG. 21 as a first block, data phi _S input terminal 14 of each chip is connected to the data phi _S line 114-1.

  The φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the chip # 1 are sequentially connected to the clock pulse φ wirings 110, 111, 112, and 113, respectively.

  The φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the chip # 2 are sequentially connected to the clock pulse φ wirings 111, 112, 113, and 110, respectively.

  The φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the chip # 3 are sequentially connected to the clock pulse φ wirings 112, 113, 110, and 111, respectively.

  The φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the chip # 4 are sequentially connected to the clock pulse φ wirings 113, 110, 111, and 112, respectively.

  The φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the chip # 5 are connected to the clock pulse φ wirings 110, 113, 112, and 111, respectively, in order.

  The φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the chip # 6 are connected to the clock pulse φ wirings 113, 112, 111, and 110, respectively, in order.

  The φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the chip # 7 are connected to the clock pulse φ wirings 112, 111, 110, and 113, respectively, in order.

  The φ1 terminal 10, φ2 terminal 11, φ3 terminal 12, and φ4 terminal 13 of the chip # 8 are sequentially connected to clock pulse φ wirings 111, 110, 113, and 112, respectively.

  Other wirings are the same as those in FIG.

  Here, the clock pulse φ wirings 110, 111, 112, and 113 are the chips # 1 to # 4, respectively.

  Are connected to the φ1 to φ4 terminals in this order.

  On the other hand, chips # 5 to # 8 are

  Are connected to the φ1 to φ4 terminals in this order. Compared to Table 1, the direction of the arrow is reversed.

  In the four clock pulse φ wirings 110, 111, 112, 113,

  When L pulses are given in this order, data is transferred in the right direction of the circuit diagram in the chips # 1 to # 4.

  Also,

  When the L pulses are given in this order, data is transferred in the right direction of the circuit diagram in the chips # 5 to # 8.

Thus, given a L pulse of Table 3 or 4 clock pulses φ wiring as shown in Table 4, the chip # 1 to # 4 or, any of the chip # 5 to # 8, the thyristor T ₀ is turned on However, the data cannot be sent to the right side and is eventually invalidated. Accordingly, Table 3, be switched the order to give the L pulses as shown in Table 4, it distributes the data to the 8 chips from one data phi _S line.

FIG. 22 shows an example in which two chip configurations of the second embodiment are incorporated in one chip. As can be seen from the figure, the shift section is divided into two sections between the shift section thyristors _T128 and _T129 . In the figure, on the right side of the shift unit, the data phi _S input terminal 19 is provided. Unlike the FIG. 20, phi _I wiring without divided into right and left, and a one phi _I wiring.

  In this circuit, when pulses are given in the order of φ1 → φ2 → φ3 → φ4 → φ1, the light emitting point is shifted to the right in the left half circuit, and pulses are given in the order of φ1 → φ4 → φ3 → φ2 → φ1. , The light emission point shifts to the left in the right half circuit.

By using this chip, the writing of data 128 bits of the left half, and the 128-bit data of the right half write, since performed separately by order of the clock pulses .phi.1 to .phi.4, the need to separate phi _I wirings Absent. In this configuration, diode coupling is used for coupling between thyristors of the shift unit, but resistance coupling may be used.

As shown in FIG. 23, by providing the data output terminal 20 on the chip, a plurality of chips can be handled as one chip. Incidentally, the chip is obtained by a single light-emitting signal phi _I wiring in the chip 2. FIG. 24 shows an example in which four chips are handled as one chip, and 16 chips constitute one block.

  As can be seen from the figure, the data output terminal 20 is connected to the data input terminal 14 of the adjacent chip between the four chips. Further, the φ 1 terminal 10, the φ 2 terminal 11, the φ 3 terminal 12, and the φ 4 terminal 13 are connected to the clock pulse φ wirings 110, 111, 112, and 113 by changing the connection state in units of four chips.

Consider the case of driving the optical printer head (FIG. 9) of the first embodiment. With the A3 size head, 60 chips per chip, and 256 light emitting points per chip, a maximum of 1/8 of the light emitting points are lit up simultaneously. That is, a maximum of 1920 light emission points are turned on simultaneously. As 10mA of current per light emitting points through the 19A stuff current phi _I driver must drive. For this purpose, a driver circuit having a large current driving capability must be prepared, and the influence of a voltage drop due to wiring resistance or the like must be avoided as much as possible. For example, when driving with a power supply voltage of −3.3 V, the output impedance of the power supply including the wiring resistance must be suppressed to about 2 mΩ in order to suppress the difference in voltage drop between full lighting and non-lighting to 1%. , Costly to realize.

Therefore, as shown in FIG. 25, using a chip in FIG. 20, phi _I L terminals 15 of the right and left of each chip, a phi _I R terminal 16, the terminal of the driver IC200 (201-1) ~ (201-20) Connected to. The number of output terminals is 120, but only 20 are shown for the sake of simplicity. Emission signal thus per chip phi _{I L,} by supplying phi _{I R,} the light emitting point is maximum 32 to light up simultaneously, may be at most driving a current of 320 mA.

  In the case of this embodiment, the number of wirings between the driver IC 200 and the chip is two per chip, and in the case of 60 chips, 120 connections are required. Therefore, the driver IC 200 may be built in the head. desirable. In addition, the driver IC 200 is desirably placed at both ends or one end in the longitudinal direction of the chip mounting substrate.

  A configuration example of the driver IC 200 is shown in FIG. In order to simplify the drawing, it is assumed that the driver has 12 output terminals. The driver IC 200 includes one shift register 210, twelve OR gates 211, and twelve current buffers 212. The shift register 210 is controlled by shift register control terminals 202 (clock input), 203 (clear), and 205 (shift register data input). The output of each bit is ORed with the data width input 204 by the OR gate 211 and output through the current buffer 212.

An example of drive waveforms is shown in FIG. In FIG. 27, after writing data into the shift unit with 8 chips as one block, the light emission signals φ _I L, φ _I R (211-1) are sequentially turned on for each light emission signal φ _I L, φ _I R wiring. ) To (211-12) sequentially become L. These light emission signals are controlled by a clear signal V (203), a clock signal V (202), a data width signal V (204), and a data signal V (205). In this embodiment, the clock signal V (202) and the data width signal V (204) have the same waveform.

When the data development to the shift unit is completed, the clear signal V (203) is set to L and the shift register 210 is cleared. Next, the shift register input data signal V (205) is set to L, and the L data is stored in the first stage of the shift register by the clock signal V (202). The L output and the OR of the data width signal V (204) are output as the light emission signal φ _I L (201-1). Subsequently, the clock signal V (202) becomes H, becomes again L, L data of the shift register is transferred to the second bit, the light-emitting signal φ _I R (201-2) is output. Here, time each phi _I wiring is in order that L is determined by the data width signal V (204), it is possible to adjust the time integration of light quantity of each chip.

  Although a circuit using a shift register is shown in this embodiment, a counter + decoder may be used, or only a decoder may be used.

In the optical printer head of Embodiment 5 (FIG. 25), two drivers capable of driving 320 mA per chip are required. A driver capable of driving a large current increases the chip area in order to reduce the on-resistance. 120 such drivers are required, which increases the cost of the driver IC. Therefore, the chip shown in FIG. 28 is configured to reduce the number of drivers that drive a large current. The configuration of the chip in FIG. 2 is that a resistor 48 is provided between the shift unit thyristor 41 and the light emitting unit thyristor 45, a light emission enabling signal wiring 121 is provided, and the light emitting unit thyristor 45 and the light emission enabling signal wiring 121 are connected. the resistance 49 provided between, the emit signal phi _I wiring is different in that it is constituted by one. In FIG. 28, 21 is a light emission permission signal terminal.

  The circuit of FIG. 28 is realized with the configurations of FIGS. FIG. 29 is a plan view of the chip, and FIGS. 30A and 30B are a plan view and a YY line cross section showing one unit of the shift unit and one unit of the light emitting unit corresponding one-to-one. FIG. 29, the same components as those in FIG. 28 are denoted by the same reference numerals, and in FIGS. 30A and 30B, the same components as those in FIGS. 4A and 4B are shown. Are denoted by the same reference numerals.

The nth bit is extracted and shown in FIG. The resistance value of the resistor 42 is R _g , the resistance value of the resistor 44 is R _kt , the resistance value of the resistor 48 is R _a , the resistance value of the resistor 46 is R _kl , and the resistance value of the resistor 49 is R _b .

Further, the gate voltage of the shift unit thyristor _{T n V GT,} the gate voltage of the light-emitting unit thyristors _{L n} and _{V GL.}

Power supply terminal 17 to -3.3 V, the light emission signal phi _I terminal 15 to 0V. The relationship among on / off of the shift unit thyristor T _n , the level V (21) of the light emission enable signal terminal 21, the gate voltage V _GL of the light emission unit thyristor L _n , and the gate voltage V _GT of the shift unit thyristor T _n Table 5 shows.

Here, R _a , R _b , and R _g are determined so that the light emitting unit thyristor L _n cannot be turned on except for the shift unit thyristor T _n = ON and the light emission permission signal V (21) = 0. It is desirable that the gate voltage V _GL of the light emitting unit thyristor L _n when T _n = ON and V (21) = V _L and T _n = OFF and V (21) = 0 are both close to _VL . For this purpose, R _a , R _b >> R _g may be set. However, if R _a and R _b cannot be increased unnecessarily, the V _GL values under both conditions may be selected to be equal. That is,
R _a / (R _a + R _b ) = R _b / (R _g + R _a + R _b )
Here, since only the ratio becomes a problem, dividing both sides by R _g,
(R _b / R _g ) ² = (R _a / R _g ) + (R _a / R _g ) ²
It becomes the relationship. For example, if R _a / R _g = 3, then R _b / R _g = 12 ^0.5 . Table 6 shows the voltage relationship in this case with V _L = -3.3V.

The light emitting unit thyristor is turned on when a voltage lower than the gate voltage by a threshold _Vth is applied to the cathode. _Assuming that V th = 1.5V, phi case of applying a voltage of -1.5 to-3.03V in _{I lines, T n = ON, V (} 21) = 0 of the chips of phi _I wirings The light emitting point designated by the shift unit can be turned on.

Incidentally, when the pulse of the L level voltage by phi _I wirings difficult to use than differs, as shown in FIG. 32, may be provided a diode D _S of one stage to the gate of the light-emitting portion thyristor L _n. In this case, shifts the ON voltage of the voltage drop by the light emitting unit thyristor diode D _S, like other The clock, L level is operable in a pulsed voltage of -3.3 V.

An optical printer head was constructed using the chip of FIG. 33A and 33B show an equivalent circuit of the output terminal of the chip and the head. The head incorporates a driver IC 220 that drives a light emission permission signal. The configuration of the IC driver 220 is shown in FIG. The driver IC is composed of one shift register 230 and eight current buffers 232. In the figure, reference numerals (2211-1) to (221-8) denote driver IC output terminals, 222 denotes a driver IC clock input, 223 denotes a clear input, and 225 denotes a shift register data signal. Driver IC200 in Figure 25, for driving the phi _I wiring directly, but a large current driving capability were required, driver IC220 is because only drives the light-emission enable signal line driving capability may be small. For example, if R _g + R _a + R _b = 300 kΩ in FIG. 31 is selected, the light emission permission signal terminal 21 can be driven at about 3 mA.

  FIG. 35 shows drive waveforms. V (221-1) to V (221-8) are driver IC output terminal voltages, V (223) is a clear signal voltage, V (222) is a clock signal voltage, and V (225) is a clock signal voltage. The voltage of input data is shown.

In the driver 200 drives the light emission current phi _I in FIG. 25, it is necessary to drive a large current such 320～640MA, driver 220 of this embodiment, one (if necessary 1 head 2-8 The driver IC can be downsized compared to the driver IC 200.

  The anode common type circuit has been described above. However, even the cathode common type circuit can be used in the same manner except that the polarity of the voltage is different. Moreover, although the example with the power supply voltage of -3.3V system was shown, it is the same also with other power supply voltages.

  Next, an optical printer using the optical printer head described above will be described. FIG. 36 shows a configuration of an optical printer including such an optical printer head 140. A photoconductive material (photosensitive member) such as amorphous Si is formed on the surface of the cylindrical photosensitive drum 142. This drum rotates at the speed of printing. The surface of the photosensitive drum of the rotating drum is uniformly charged by the charger 144. Then, the optical printer head 140 irradiates the photosensitive member with light of a dot image to be printed, and neutralizes the charging where the light hits. Subsequently, the developing device 148 applies toner to the photoconductor in accordance with the charged state on the photoconductor. Then, the toner is transferred onto the paper 154 sent from the cassette 152 by the transfer device 150. The paper is heated and fixed by the fixing device 146 and sent to the stacker 158. On the other hand, the drum that has been transferred is neutralized by the erasing lamp 160 over the entire surface, and the remaining toner is removed by the cleaner 62.

It is a figure which shows the equivalent circuit of the conventional multipoint lighting type self-scanning light emitting element array chip. It is a figure which shows the equivalent circuit of the self-scanning light emitting element array chip of 256 light emission points. It is a figure which shows the structure which implement | achieved the chip | tip of FIG. 1 by the PNPN structure on a p-type board | substrate. It is the top view and sectional drawing which show 1 unit of the shift part of FIG. 3, and 1 unit of a light emission part. FIG. 3 is a diagram illustrating an example of a driving waveform for driving the self-scanning light emitting element array chip of FIG. 2. FIG. 3 is a diagram illustrating an example of a driving waveform for driving the self-scanning light emitting element array chip of FIG. 2. FIG. 3 is a diagram illustrating an example of a driving waveform for driving the self-scanning light emitting element array chip of FIG. 2. FIG. 3 is a diagram illustrating an example of a driving waveform for driving the self-scanning light emitting element array chip of FIG. 2. It is a figure which shows the structure of the optical printer head using the self-scanning light emitting element array chip | tip of FIG. It is a figure which shows the waveform of the signal supplied to the optical printer head of FIG. It is a figure which shows the waveform of the signal which chip | tip # 1 receives. It is a figure which shows the waveform of the signal which chip | tip # 2 receives. It is a figure which shows the waveform of the signal which chip | tip # 3 receives. It is a figure which shows the waveform of the signal which chip | tip # 4 receives. It is a figure which shows the waveform of the clock pulse supplied to the optical printer head of FIG. It is a figure which shows the waveform of the clock pulse supplied to the optical printer head of FIG. It is a figure which shows the waveform of the clock pulse supplied to the optical printer head of FIG. It is a figure explaining data expansion | deployment. It is a figure explaining other data expansion | deployment. It is an equivalent circuit diagram of another self-scanning light emitting element array chip. It is a figure which shows the structure of the optical printer head using the chip | tip of FIG. It is an equivalent circuit diagram of another self-scanning light emitting element array chip. It is an equivalent circuit diagram of another self-scanning light emitting element array chip. It is a figure which shows the structure of the optical printer head using the chip | tip of FIG. Emission signal phi _{I L,} is a diagram showing the construction of an optical printer head using a driver IC to the supply of phi _{I R.} FIG. 26 is a diagram illustrating a configuration of a driver IC in FIG. 25. It is a figure which shows the drive waveform of the optical printer head of FIG. It is an equivalent circuit diagram of another self-scanning light emitting element array chip. It is a figure which shows the structure which implement | achieved the chip | tip of FIG. 28 by the PNPN structure on a p-type board | substrate. It is the top view and sectional drawing which show 1 unit of the shift part of FIG. 29, and 1 unit of a light emission part. FIG. 29 is a circuit diagram showing an nth bit extracted from FIG. 28. FIG. 32 is a diagram showing a modification of the circuit in FIG. 31. It is a figure which shows the structure of the optical printer head which used driver IC for supply of the light emission permission signal. It is a figure which shows the structure of the driver IC of FIG. It is a figure which shows the drive waveform of the optical printer head of FIG. It is a figure which shows the structure of an optical printer.

10 ... clock pulse φ1 terminal, 11 ... clock pulse φ2 terminal, 12 ... clock pulses φ3 terminal, 13 ... clock pulse φ4 terminal, 14 ... data phi _S input terminal, 15 ... light-emitting signal phi _I L terminal, 16 ... light-emitting signal phi _IR terminal , 17 ... power supply _VGA terminal , 18 ... GND terminal , 41 , 45 ... thyristor , 42 , 44 , 46 ... resistor , 43 ... diode , 47 ... current limiting resistor , 110 , 111 , 112 , 113 ... clock Pulse wiring , 215 ... Light emission signal φ _I wiring , 216 ... φ _IR wiring , 117 ... Power supply wiring , 118 ... GND wiring

Claims (8)

P + 1 (P is an integer) first three-terminal light-emitting thyristors are arranged one-dimensionally, the gates of adjacent first thyristors are connected to each other with a diode, and each gate is connected to a power supply wiring via a gate load resistor Then, the anode / cathode of each first thyristor is connected to M clock pulse wirings that provide M-phase (M is an integer of 2 or more) clock pulses with a phase shifted one by one through a resistor, A shift unit having an image data input terminal connected to the gate of the first first thyristor;
P second three-terminal light emitting thyristors are arranged one-dimensionally, and the gates of the second thyristors are connected to the gates of the second to first thyristors corresponding to the shift unit, and the P The second thyristor is divided into N groups each having P / N in succession, and the anodes / nodes of the second thyristors in the nth group (1 ≦ n ≦ N) with respect to the N light emitting signal lines. A light emitting unit having a cathode connected to the nth light emitting signal line through a resistor;
A self-scanning light emitting element array chip comprising: The self-scanning light-emitting element array chip according to claim 1,
The N are two, and the anode / cathode of each second thyristor in one group is connected to the first light emitting signal wiring through a resistor, and the anode / cathode of each second thyristor in the other group is connected. A self-scanning light-emitting element array chip in which a cathode is connected to a second light-emitting signal wiring through a resistor. A plurality of self-scanning light-emitting element array chips according to claim 2 arranged in a one-dimensional manner,
One common power supply line to which the power supply lines of all the chips are connected;
One first common light emission signal line to which the first light emission signal lines of all the chips are connected;
One second common light emitting signal wiring to which the second light emitting signal wiring of all the chips is connected;
Dividing the plurality of chips into M consecutive blocks, and M common clock pulse wirings to which M clock pulse wirings of chips of each block are connected with a phase shifted by one;
A plurality of common data wirings to which the image data input terminals of all the chips in each block are respectively connected;
An optical writing head comprising: A plurality of self-scanning light-emitting element array chips according to claim 2 arranged in a one-dimensional manner,
One common power supply line to which the power supply lines of all the chips are connected;
A driver circuit for supplying first and second light emission signals to the first and second light emission signal wirings of each chip;
Dividing the plurality of chips into M consecutive blocks, and M common clock pulse wirings to which M clock pulse wirings of chips of each block are connected with a phase shifted by one;
A plurality of common data wirings to which the image data input terminals of all the chips in each block are respectively connected;
An optical writing head comprising: The driver circuit is
A shift register that receives data signals and outputs signals to a plurality of parallel outputs;
An OR gate that ORs each output of the shift register and a data width signal;
A current buffer for outputting a light emission signal based on the output of the OR gate;
The optical writing head according to claim 4 , comprising: A plurality of self-scanning light-emitting element array chips according to claim 2 arranged in a one-dimensional manner,
One common power supply line to which the power supply lines of all the chips are connected;
One common light emission signal wiring to which the light emission signal wirings of all the chips are connected;
Dividing the plurality of chips into M consecutive blocks, and M common clock pulse wirings to which M clock pulse wirings of chips of each block are connected with a phase shifted by one;
A plurality of common data wirings to which the image data input terminals of all the chips in each block are respectively connected;
A driver circuit for supplying a light emission permission signal to the light emission permission signal wiring of each chip;
An optical writing head comprising: The driver circuit is
A shift register that receives data signals and outputs signals to a plurality of parallel outputs;
A current buffer that outputs a light emission permission signal based on each signal output from the shift register;
The optical writing head according to claim 6 , comprising: An optical printer using the optical write head according to claim 3, 4 , 5 , 6 or 7 .

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