CN100522629C - Self-scanned light-emitting device array chip - Google Patents

Abstract

A self-scanning light-emitting element array is provided in which multiple light-emitting elements may be illuminated simultaneously in one chip. In a self-scanning light-emitting element array including a transfer element array and light-emitting element array, a magnitude of the write signal for illuminating adjacent two light-emitting elements simultaneously is two times that of the write signal for illuminating one light-emitting element. The self-scanning light-emitting element array is composed of a plurality of self-scanning light-emitting element array chips arranged in a linear manner, and the two-phase clock pulses are applied commonly to the plurality of self-scanning light-emitting element array chips.

Description

Self-scanned light-emitting device array chip

The application is that application number is 01802651.6, the applying date is September 4 calendar year 2001, denomination of invention is divided an application for " self-scanning light-emitting element array and driving method thereof and drive circuit " patent application.

Technical field

The present invention relates to self-scanned light-emitting device array chip.

Background technology

The write head of light printing machine (below be called light pen) is the light source that is used to make the photosensitive drums exposure, has light-emitting device array.The schematic diagram that has been equipped with the optical printer of light pen is illustrated in Fig. 1.On the surface of columnar photosensitive drums 2, form material (photoreceptor) with photoconductions such as amorphous Si.This drum rotates with print speed printing speed.By the photosensitive surface uniform charging of charger 4 to the drum that is rotating.With light pen 6 photoreceptor is penetrated in the illumination of print point image then, made the charging neutrality at the illumination place of penetrating and form sub-image.Again by imagescope 8 according to the electriferous state on the photoreceptor, toner is attached on the photoreceptor.Continue and this toner is needed on the paper of sending here from box 12 14 by transfer printing device 10.This paper, is delivered to and is stored up on the device 18 by mode photographic fixing such as heating by fuser 16.On the other hand, the drum of having finished transfer printing neutralizes electric charge by the static lamp 20 that disappears on whole surface, removes remaining toner with sweeper 22 then.

The structural table of light pen 6 is shown among Fig. 2.Light pen by magnification optical systems such as light-emitting device array 24 and erect image for example rod lens array 26 constitute, the focus of lens will be fallen on the photosensitive drums 2.

The inventor etc. are for the structure devices as self-scanning light-emitting element array, focus on the luminous IGCT of three terminals that attention has the pnpn structure, having proposed patent application (spy open flat 1-238962 communique, spy open flat 2-14584 communique, spy are opened flat 2-92650 communique, the spy opens flat 2-92651 communique) and disclosed will be as optical printer with the easy in practice installation of light source, the light-emitting component pitch is reduced, the innovations such as self-scanning light-emitting element that preparation is compact.

In addition, the inventor etc. have proposed with the conveying element array as transport unit, are separated with the light-emitting device array of illuminating part and the self-scanning light-emitting element array (spy opens flat 2-263668 communique) that is configured to.

Represented to have the equivalent circuit of self-scanned light-emitting device array chips transport unit and illuminating part phase separation structure, 1200dpi, 256 light-emitting components among Fig. 3.Transfering department has conveying element T ₁, T ₂, T ₃..., illuminating part has light-emitting component L ₁, L ₂, L ₃....These conveying elements and light-emitting component are made of the luminous IGCT of three terminals.Though the mode that the structure of transport unit can adopt the control with IGCT to be electrically connected has extremely mutually adopted diode D at this ₁, D ₂, D ₃... diode in conjunction with mode.V _GKFor power supply (general 5V), through load resistance R _LControl utmost point G with each transport unit IGCT ₁, G ₂, G ₃... connect.The control utmost point G of transport unit IGCT ₁, G ₂, G ₃... also be connected with the control utmost point of illuminating part IGCT.Transport unit IGCT T ₁Control extremely on be added with start pulse

Alternately be added with on the anode of transport unit IGCT to transmit and use clock pulses On the anode of illuminating part IGCT, then be added with write signal

Have again, represent with 30 among Fig. 3 Circuit, 32 expressions

Circuit, 34 expressions

Circuit, 36 expression power lines, R ₁, R ₂, R _I, respectively the expression be inserted in

Circuit 30, Circuit 32,

Current-limiting resistance in the circuit 34, Rs then are the current-limiting resistances with respect to start pulse.

Summary operation now.At first set to transmit and use clock pulses

Voltage be H level and IGCT T ₂Be in the ON state.At this moment, control utmost point G ₂Current potential from V _GK5V be reduced to and be substantially zero V.The influence of this potential drop can be through diode D ₂Send control utmost point G to ₃, be about 1V (diode D with its potential setting ₂Diffusion potential).But diode D ₁Owing to be anti-state partially, so not to control utmost point G ₁Carry out the connection of current potential, make control utmost point G ₁Current potential still be 5V.The conducting voltage of the luminous IGCT of pnpn structure is similar to the pn knot diffusion potential (about 1V) between control electrode potential+control utmost point and anode, thereby just thinks next one transmission clock pulses

The H level voltage be set to about 2V and (make IGCT T ₃Essential voltage during conducting) above and about 4V (makes IGCT T ₅Essential voltage during conducting) below, just can make IGCT T ₃Conducting, transport unit IGCT in addition then can be still for disconnecting.Therefore by 2 transmission clock pulses

Transmit conducting state.

Start pulse Be the pulse that is used to represent to begin this transmission operation, with start pulse

When being set to L level (about 0V), use clock pulses if will transmit simultaneously

Be made as H level (about 2～about 4V), then can make IGCT T ₁Conducting.After this start pulse

Just return the H level immediately.

Now, establish IGCT T ₂Be in conducting state, control utmost point G ₂Current potential be 0V substantially.Thereby work as write signal

Voltage reach the diffusion potential (about 1V) of pn knot between the control utmost point and anode when above, just can make illuminating part IGCT L ₂Become luminance.

In contrast, control utmost point G ₁About 5V and control utmost point G ₃Become 1V.Thereby IGCT L ₁Write the about 6V of voltage and IGCT L ₃The voltage that writes become 2V.Thus, write IGCT L ₂Write signal Voltage just be 1～2V.As IGCT L ₂After conducting promptly entered luminance, luminous intensity was just by flowing through write signal

Magnitude of current decision, can write image with intensity arbitrarily.In addition, for luminance being sent to next illuminating part IGCT, need write signal

The voltage of circuit once promptly drops to 0V, and allows just luminous IGCT temporarily disconnect.

The self-scanning light-emitting element array of light pen is made a plurality of arrangements of chips of said structure shape that is in line.By aforementioned operation as can be known, each chip can luminous light-emitting component number of while be 1.

In order to improve the print speed printing speed of light printing machine, need to strengthen the exposure energy on the photosensitive drums.Because exposure energy is the light output (dimension with power) of light-emitting component and amassing of time for exposure,, should strengthen light output or prolonging exposure time in order to increase exposure energy.

In order to strengthen light output, if can strengthen electric current though light emitting element structure is identical, increasing electric current can influence component life, can not too increase.On the other hand, prolonging exposure time promptly increases luminous dutycycle, and then needing to increase each chip can simultaneously luminous light-emitting component quantity.

Summary of the invention

One of purpose of the present invention is to provide the driving method that makes each chip can allow the luminous self-scanning light-emitting element array of 2 above light-emitting components simultaneously.

Another object of the present invention is to provide and make the simultaneously luminous light-emitting component quantity of each chip energy at the self-scanning light-emitting element array more than 2.

Diode shown in Figure 3 is to get by the driving of 5V power-supply system with structure that IC drove in conjunction with self-scanning light-emitting element array.But the supply voltage of driving usefulness IC, will further change to low-voltage after the 3.3V system from the 5V system change.This is because the decline of supply voltage can reduce the cause of consumed power.Therefore, preferably can drive self-scanning light-emitting element array by the 3.3V power-supply system.

Still a further object of the present invention be provide by the 3.3V power-supply system drive the diode combination self-scanning light-emitting element array method and the drive circuit of realizing this driving method is provided.

In addition, as shown in Figure 2, light pen is to be made of light-emitting device array and rod lens array.At this moment, when light-emitting component is made by self-scanned light-emitting device array chip shown in Figure 3, in the time of being arranged in a straight line shape to a plurality of chips by the end butt joint, just can not make the arrangement pitches of light-emitting component constant.For avoiding this situation, can the part of die terminals is overlapping and line up so-called stagger mode, and partly locate to make the arrangement pitches of light-emitting component certain in the chip tie point.

When the light pen printing of adopting this light-emitting device array, because the structure of rod lens array and the arrangement of rod lens array and light-emitting component produce the printing striped at the tie point place of chip chamber sometimes.

Another object of the present invention is to provide the light pen that does not produce the printing striped that is caused by above-mentioned reason.

The present invention's another purpose again then is to be provided for to realize above-mentioned light pen, the aligning method of rod lens and light-emitting component.

According to a first aspect of the invention, can not change the circuit of existing self-scanning light-emitting element array, and can make 2 adjacent light-emitting components simultaneously luminous according to clock patterns and write signal.

According to a second aspect of the invention, can pass through additional resistance on the circuit of existing self-scanning light-emitting element, and can make 2 adjacent light-emitting components simultaneously luminous according to clock patterns (pattern) and write signal.

According to a third aspect of the invention we, by on 1 chip, self-scanning light-emitting element array being got the double circuit structure, there are 2 above light-emitting components luminous on each chip simultaneously and can make.

According to a forth aspect of the invention, by before making the conveying element conducting, the clock pulses circuit being pre-charged to than the lower magnitude of voltage of clock pulses voltage that makes the conveying element conducting, just can drive self-scanning light-emitting element array with the 3.3V power-supply system.

According to a fifth aspect of the invention, by rod lens array being constituted when rod lens array is observed the situation equivalence that can form a line with light-emitting component, just can not produce the printing striped.

Description of drawings

Fig. 1 represents to have the principle of the light printing machine of light pen.

Fig. 2 represents the structure of light pen.

Fig. 3 is the equivalent circuit diagram of the self-scanned light-emitting device array chip of transport unit and illuminating part isolating construction.

Fig. 4 illustration is pressed the waveform of 1200dpi resolution drive.

Fig. 5 illustration is pressed the waveform of 600dpi resolution drive.

Fig. 6 represents

First example of line drive circuit.

Fig. 7 represents

Second example of line drive circuit.

The combination of 4 kinds of waveform patterns of Fig. 8 illustration.

Fig. 9 is the key diagram that has made up the example of 4 kinds of waveform patterns.

Figure 10 is the equivalent circuit diagram of second example of self-scanning light-emitting element array of the present invention.

Figure 11 represents I-V (current-voltage) characteristic of illuminating part IGCT.

Figure 12 A, 12B represent resistance is added first example in the luminous IGCT of pnpn structure three terminals.

Figure 13 A, 13B represent resistance is added second example in the luminous IGCT of pnpn structure three terminals.

Figure 14 A, 14B are the oscillograms of expression driving method first example.

Figure 15 is the oscillogram of expression driving method second example.

Figure 16 represents the equivalent circuit of self-scanned light-emitting device array chip first example of the present invention.

Figure 17 is the plane of practical structures of the chip of Figure 16.

Figure 18 is C-C ' the line profile of Figure 17.

Figure 19 represents the equivalent circuit of self-scanned light-emitting device array chip second example of the present invention.

Figure 20 is the plane of practical structures of the chip of Figure 19.

Figure 21 is D-D ' the line profile of Figure 20.

Figure 22 represents the equivalent circuit of self-scanned light-emitting device array chip the 3rd example of the present invention.

Figure 23 is the plane of practical structures of the chip of Figure 22.

Figure 24 is E-E ' the line profile of Figure 23.

Figure 25 represents the equivalent circuit of self-scanned light-emitting device array chip the 4th example of the present invention.

Figure 26 is the plane of practical structures of the chip of Figure 25.

Figure 27 is F-F ' the line profile of Figure 26.

Figure 28 is the I-V performance plot of IGCT.

Figure 29 represents the equivalent circuit of self-scanned light-emitting device array chip the 5th example of the present invention.

Figure 30 is the plane of practical structures of the chip of Figure 29.

Figure 31 represents

The circuit of circuit over time.

Figure 32 represent the value of current-limiting resistance R1 and pre-charge voltage and transmit in required overlapping time t _aThe relation of minimum of a value.

Figure 33 represents the example of diode in conjunction with the drive circuit of self-scanning light-emitting element array.

Figure 34 represents the I/O waveform of the drive circuit of Figure 33.

Figure 35 represents diode another example in conjunction with the drive circuit of self-scanning light-emitting element array.

Figure 36 represents the I/O waveform of the drive circuit of Figure 35.

Figure 37 represents the another example of diode in conjunction with the drive circuit of self-scanning light-emitting element array.

Figure 38 represents the control signal waveform of the drive circuit of Figure 37.

Figure 39 represents voltage (V)-electric current (I) characteristic of IGCT.

Figure 40 represents another example of control signal waveform of the drive circuit of Figure 35.

Figure 41 A, 41B represent the arrangement of light-emitting device array chip.

Figure 42 represents that lamination becomes the rod lens array of 2 row up and down.

Figure 43 A, 43B, 43C are illustrated in the scope of the position A of X-direction shown in Figure 42 and B, calculate the results that the X-direction light quantity changes with regard to 3 kinds of situations of Y direction position 0mm, 0.05mm and 0.10mm respectively.

Figure 44 A, 44B, 44C represent respectively the skew △ TC of TC be 0mm ,-0.1mm ,+during 0.1mm, the calculated example of the MTF at 0mm, 0.05mm, 0.10mm place on Y direction.

Figure 45 represents that rod lens array and light-emitting device array chip arrange unsuitable example.

Figure 46 represents that rod lens array and light-emitting device array arrange unsuitable example.

Figure 47 represents first example of light pen of the present invention.

Figure 48 represents second example of light pen of the present invention.

Figure 49 represents the 3rd example of light pen of the present invention.

Figure 50 represents the 4th example of light pen of the present invention.

Figure 51 represents the 5th example of light pen of the present invention.

Figure 52 represents the 6th example of light pen of the present invention.

The specific embodiment

Below according to the description of drawings embodiments of the invention.

(first embodiment)

Present embodiment is the circuit structure that does not change the self-scanned light-emitting device array chip of Fig. 3, is the driving method of 2 self-scanning light-emitting element array and make the luminous light-emitting component simultaneously of each chip.

First example

The light pen that will possess a plurality of light-emitting components that are arranged in of self-scanned light-emitting device array chip of 1200dpi that Fig. 3 is arranged, 256 light-emitting components, waveform example by the 1200dpi resolution drive is illustrated in Fig. 4, is illustrated in Fig. 5 by the waveform example of 600dpi resolution drive.Present embodiment is by using this 2 kinds of waveforms respectively, when the self-scanning light-emitting element array that uses 1200dpi is pressed the resolution ratio presentation video of 600dpi, 2 adjacent light-emitting components are regarded as 1 cell block and lighted the printing speed that doubles when realizing 1200dpi resolution ratio thus simultaneously.

In addition, in this example, clock pulses Share for a plurality of self-scanning light-emitting element chips that constitute light pen.

At first drive waveforms under the 1200dpi resolution ratio is described referring to Fig. 4.Write signal

Waveform repeat the transport unit clock pulses with period T

Waveform repeat with cycle 2T.Time t among the figure _aBe at transport unit IGCT T _N-1During conducting, for making next IGCT T _nConducting and overlapping time of needing; Time t _bThen be from transport unit IGCT T _nBe conducting to the stand-by time of illuminating part IGCT Ln conducting.At this t _a, t _bDuring this time, the illuminating part IGCT can not be luminous, and can only be during surplus T-(t _a+ t _b) between luminous.The feature of these drive waveforms is " illuminating part IGCT L _nWhen luminous, the IGCT that is in conducting state is T _n".

Referring to Fig. 5 drive waveforms under the 600dpi resolution ratio is described below.This waveform is for write signal

And transport unit clock pulses

Repetition period all be 2T.Establish adjacent transport unit IGCT T now _2n-3, T _2n-2Conducting simultaneously.Initial time t among the figure _eBe to be used to make IGCT T _2n-3Disconnect the necessary time, next time t _aBe to make IGCT T _2n-1The overlapping time that conducting is required, next again time t _eBe to make IGCT T _2n-2Disconnect the required time, next again time t _aBe to make IGCT T _2nThe overlapping time that conducting is required, and the time 2T-2 (t of surplus _a+ t _e) then be adjacent 2 illuminating part IGCT L _2n-1-with L _2nCan the simultaneously luminous time.

The feature of above-mentioned drive waveforms is " illuminating part IGCT L _2n-1With L _2nCan be simultaneously luminous, and this moment transport unit IGCT T _2n-1With T _2nConducting simultaneously ".But because 2 adjacent illuminating part IGCT L _2n-1, L _2nSimultaneously luminous, write signal

Electric current also must divide and flow to 2 IGCTs, therefore The drive circuit of circuit needs to have 1 electric current I when luminous according to resolution ratio _LElectric current 2I with 2 when luminous _LTwo kinds of level.

Fig. 6 represents above-mentioned self-scanning light-emitting element array

The example of the drive circuit of circuit.This drive circuit is by 60,61,3 MOSFET62-63 of 2 phase inverters, 64 and 2 current-limiting resistance R _Ia, R _IbConstitute.V _1a, V _IbBe control terminal, V _IBe lead-out terminal and with Fig. 3 Terminal connects.

Set control terminal V _IaBehind the H level, lead-out terminal V _IThen through resistance R _IaWith positive supply (+V _DD) connect.Set control terminal V again _IbBe the H level, and resistance R _IaWith resistance R _IbIn parallel.If resistance R _IaWith R _IbResistance value identical, so the value of this parallel resistance becomes 1/2 of 1 resistance value, thereby

Electric current becomes 2 times.

So, according to this drive circuit, for making 1 illuminating part IGCT luminous, can be with control terminal V _IaBe made as the H level.And be to make 2 adjacent IGCTs simultaneously luminous, then can be with control terminal V _Ia, V _IbBe set at the H level simultaneously.

Fig. 7 represents by 2 current source J _a, J _b, switch S wa, the SWb that is connected with the output of each current source forms Another example of line drive circuit.Each switch is by control terminal V _Ia, V _IbThe control of breaking/lead to.Promptly when control terminal is the H level, switch connection.

By making control terminal V _IaBe the H level, switch S wa is logical, current source J _aElectric current flow to

Terminal.Have again, establish control terminal V _IbBe the H level, from current source J _aWith J _bHave electric current to flow out, the electric current of establishing each current source is identical, flows to regard to 2 times electric current is arranged

Terminal.

So according to this drive circuit, identical with the drive circuit of Fig. 6, for making 1 IGCT luminous, can be with control terminal V _IaBe made as the H level; And be to make 2 adjacent IGCTs simultaneously luminous, then can make control terminal V _Ia, V _IbBe set to the H level simultaneously.

Now consider to adopt the drive circuit of Fig. 6 or Fig. 7, the resolution ratio of press 1200dpi * 1200dpi (main scanning direction * sub scanning direction) drives the situation that per minute prints 20 A4 paper (vertically) according to the drive waveforms of Fig. 4.Vertical suitable approximately 13800 row of A4 paper.Owing to be to have scanned its (20 of per minute) with 3 seconds, the printing time of every row is 220 μ s, and the period T of each illuminating part IGCT becomes 850ns, establishes t _a=t _b=100ns, but the about 650ns of the fluorescent lifetime of 1 illuminating part IGCT then.

The situation that next consideration is printed with the resolution ratio of 600dpi * 1200dpi (resolution ratio of sub scanning direction is identical).At this moment, the drive waveforms of pressing Fig. 5 drives, and establishes t _a=t _b=100ns, 2T=650ns+400ns then, and the printing time of every row becomes 1050ns * 128=134 μ s.The time of about 1/1.6 when this is 1200dpi * 1200dpi,, then can obtain 1.6 times print speed printing speed if establishing resolution ratio is 600dpi * 1200dpi.

If t _a, t _b, t _eLittle with respect to fluorescent lifetime to negligible degree, then can make print speed printing speed roughly improve 1 times.

As mentioned above, according to this example, because can not change the light-emitting device array of circuit by using 1200dpi can be in the hope of the image of 600dpi,, also can reduce cost by parts generalization with the shaven head of 1200dpi even in the situation of the shaven head of making 600dpi special use.

The 2nd example

Clock pulses has been described in first example

For the shared situation of a plurality of self-scanned light-emitting device array chips that constitutes light pen.Because clock pulses

Be shared, so have the advantage that circuit structure is simplified.

This 2nd example is considered in each self-scanned light-emitting device array chip clock pulses

Give the situation of circuit structure independently.Be adjacent 2 illuminating part IGCT L in example 1 _2n-1With L _2nRegard 1 unit as and make it simultaneously luminous.But in this 1 unit IGCT L _2n-1Or be IGCT L _2nLuminous, utilize to former state the resolution ratio of chip to carry out high speed printing effectively.So, corresponding to each luminance, by making clock pulses Control terminal V _Ia, V _IbWave form varies, with making the modes that 2 illuminating part IGCTs can be luminous simultaneously, can print with the original resolution ratio of chip.

Represented the clock pulses that changes among Fig. 8

Control terminal V _Ia, V _IbFour kinds of waveform patterns 0, I, II, III.Waveform patterns 0 has been represented L _2n-1With L _2nNot luminous, waveform patterns I is IGCT L simultaneously _2n-1Luminous, waveform patterns II is IGCT L _2nLuminous, waveform patterns III is IGCT L _2n-1With L _2nSimultaneously luminous situation.

In the situation of waveform patterns 0, make clock pulses

For the L level,

For the H level, carry out the transmission of conducting state by transport unit, and control terminal V _Ia, V _IbCommon is the L level, allows write signal

Former state ground keeps the L level.At this moment, illuminating part IGCT L _2n-1, L _2nNot luminous.

In the situation of waveform patterns I, be transport unit IGCT T _2n-1Be in conducting state, make control terminal V _IaBe H level control terminal V _IbBe the L level, and make write signal

Be the H level, make illuminating part IGCT L _2n-1Luminous, at illuminating part IGCT L _2n-1After not luminous, the conducting state that is about to transport unit transforms to IGCT T _2n

Waveform patterns II is opposite with the situation of pattern I, at first from transport unit IGCT T _2n-1Transfer to IGCT T _2nConducting state, control terminal V under this state _IaBe H level while write signal

Also become the H level, have only illuminating part IGCT L _2nLuminous.

The situation of waveform patterns III is identical with example 1, transport unit IGCT T _2n-1, T _2nBe in conducting state simultaneously, with control terminal V _IaWith V _IbBe made as the H level and establish write signal

Be the H level, then illuminating part IGCT L _2n-1With L _2nSimultaneously luminous.In this waveform patterns,, flow through 2 times electric current for making 2 illuminating part IGCTs luminous.And allow control terminal V _IaWith V _IbRise to the H level simultaneously.

More than the combination example of four kinds of patterns be illustrated in Fig. 9.Represented according to clock pulses Control terminal V _Ia, V _IbWave form varies, adjacent 2 illuminating part IGCT L _2n-1With L _2nThe situation of flicker.Zero with ● show respectively luminous with not luminous.Anyway make up this four kinds of patterns, transport unit transmits by 2 IGCTs for each piece as can be known.

According to the driving method of present embodiment, in self-scanning light-emitting element array,, under the situation that reduces resolution ratio, can improve print speed printing speed owing to can make 2 IGCTs simultaneously luminous simultaneously to each chip.

(the 2nd embodiment)

The self-scanned light-emitting device array chip that present embodiment relates to is in the circuit structure of the self-scanning light-emitting element array of Fig. 3, by additional resistance can make each chip simultaneously luminous light-emitting component number be 2.

The equivalent circuit of having represented the self-scanned light-emitting device array chip of present embodiment among Figure 10, in essence, the circuit of it and Fig. 3 is roughly the same, thereby for Fig. 3 in identical parts attached with Fig. 3 in identical label represent.

According to present embodiment, in the circuit of Fig. 3 in

Between the anode terminal of circuit 34 and illuminating part IGCT, be respectively equipped with the resistance R of appropriate value _AIn the self-scanning light-emitting element array of this kind structure, existing with transport unit brake tube T _nThis IGCT T during conducting _nThe illuminating part IGCT L that is connected with the control utmost point _nThe example of I-V characteristic be illustrated in the curve map of Figure 11 with solid line 38.Among Figure 11, transverse axis is represented

Electric current, the longitudinal axis is represented

Voltage.Because transport unit IGCT T _nConducting, illuminating part IGCT L _nHas the identical linearity I-V characteristic of I-V characteristic with simple diode.Specifically, the about 1V of the diffusion potential of diode, the slope of straight line is equivalent to R _AResistance value (following R _AThe resistance value of also representing itself), be 50 Ω in this figure.On the other hand, illuminating part IGCT L _nRight adjacent IGCT L _N+1The control utmost point because just in conjunction with diode D _nVoltage drop part (about 1V) relate to high voltage, thereby

The voltage of about 2V just not can conducting on the circuit.If IGCT L _N+1With L _nSimultaneously luminous, then work as When electric current increases,

Voltage if surpass IGCT L _N+1Conducting voltage (starting voltage) get final product.At this moment, the I-V characteristic curve then is converted to characteristic shown in the dotted line 39 with the characteristic shown in the solid line 38 from Figure 11.

At R _A=0 o'clock is the situation of circuit among Fig. 3, if ignore the internal resistance of illuminating part IGCT, then the I-V characteristic curve becomes level, so no matter there are much electric currents to flow through, also can not surpass IGCT L _N+1Starting voltage.Here it is before in the self-scanning light-emitting element array each chip a reason that IGCT is luminous can only be arranged.

In the circuit of Figure 10, can be with resistance value R _ABe chosen to, make and flow through 1 electric current in the illuminating part IGCT and can not make adjacent IGCT luminous, and when the electric current that has 2 times flows through wherein, then can make adjacent IGCT also luminous.Specifically, establish and be used for making IGCT luminous

Electric current is I _LThe time, when with V _{Th (n+1)}Expression IGCT L _N+1Starting voltage and with V _DWhen the pn of table IGCT ties diffusion potential, with respect to

V _D+R _A×I _L<V _th(n+1)<V _D+R _A×2I _L

Separate R _A, obtain

(V _th(n+1)-V _D)/I _L>R _A>(V _th(n+1)-V _D)/2I _L

For example establish V _{Th (n+1)}=2.1V, I _L=15mA and V _D=1V, then

73.3Ω>R _A>36.7Ω

With this resistance R _AAppend to first in the 3 terminal illuminating part IGCTs of pnpn structure for example shown in Figure 12 A, the 12B.Figure 12 A is a plane, and Figure 12 B is the A-A ' profile of Figure 12 A.

3 terminal illuminating part IGCTs are stacked in turn n type semiconductor chip 41, p type semiconductor layer 42, n type semiconductor layer 43, p type semiconductor layer 44 on n type semiconductor chip 40 basically.On diaphragm 45, be provided with

Circuit (A1 distribution) 46, to the A1 distribution 48 of the anode 47 of illuminating part IGCT and to the A1 distribution 50 of the control utmost point 49.Resistance R _AForm by being located at the film resistor 51 that the CrSiO cermet on the diaphragm 45 constitutes between A1 distribution 46 and the A1 distribution 48.Though the resistive element has here adopted the CrSiO cermet, also can adopt other cermet (AuSiO, AgSiO etc.), in addition also can be the metallic film of Ni, Cr, NiCr, W, Pt, Pd etc. as resistive element.Have again, on the inboard of n type semiconductor chip 40 shared medial electrode 52 can be set.

Figure 13 A, 13B represent resistance R _AOther configuration example, Figure 13 A is a plane, Figure 13 B is B-B ' the line profile of Figure 13 A.Resistance R in this example _ABe to constitute by the Ni resistive element 53 that inserts between A1 distribution 48 and the anode 47.Also can adopt and aforementioned electric resistance body identical materials at this.

Resistance R _AAlso can by the impurity concentration of regulating anode layer 44 regulate and anode 47 between contact resistance form, in addition, resistance R _AThe dead resistance of illuminating part IGCT realizes in the time of also can be by conducting.

In the example of Figure 13 A-13B, to note being directly connected on the A1 distribution 46 to the A1 distribution 48 of anode 47.Other structure is then identical with Figure 12 A, 12B.

In the light-emitting device array of Figure 10, write signal

Drive circuit can adopt Fig. 6 or drive circuit shown in Figure 7.

Below with an example of the driving method of the self-scanning light-emitting element array of the drive circuit of Fig. 6 or Fig. 7 explanation Figure 10.It is 1200dpi's that self-scanning light-emitting element array adopts resolution ratio.

This driving method carries out describing of 1200dpi when seeking out high-resolution output, when low the resolution also fully then can be carried out describing of 600dpi when enough, that is be to make adjacent 2 IGCTs side by side luminous in turn.

Figure 14 A and 14B represent respectively with the drive waveforms of the high-resolution of 1200dpi when describing with the low resolution of 600dpi.Make control terminal V among Figure 14 A _IaThe corresponding clock pulses of difference Get the H level.On the other hand, control terminal V _IbThen still keep the L level.Like this, the illuminating part IGCT of Figure 10 is just luminous in turn one by one.If adopt this driving method, then describe with the resolution ratio of 1200dpi.

In Figure 14 B, control terminal V _Ia, V _Ib2 corresponding continuous respectively clock pulses are got the H level in the identical moment, and thus, 2 adjacent IGCTs are simultaneously luminous in turn.If use this driving method, though be to describe with the resolution ratio of 600dpi since with the driving method of Figure 14 A mutually specific energy make the time for exposure prolong 1 times, thereby can make 1 times of print speed printing speed raising.

The following describes another example of driving method of the self-scanning light-emitting element array of Figure 10.This driving method does not reduce resolution ratio and light exposure is doubled.

In the self-scanning light-emitting element array of Figure 10, at the IGCT T of transport unit _nBe under the state of ON control terminal V _IaDuring for the H level, then the IGCT Ln of illuminating part is luminous.Have again as control terminal V _IaBe under the H level state, with control terminal V _IbWhen becoming the H level, IGCT L then _N+1Also simultaneously luminous.Figure 15 has further represented the exposure status of putting on the photosensitive drums.Point range A among the figure is by using control terminal V _IaGet the H level, the light exposure of the point that causes for luminous IGCT Ln is represented with mark Θ.And by making control terminal V _IbGet the H level, for IGCT L _N+1The light exposure of the point of luminous situation is then represented with the mark Θ of point range B simultaneously.

After 1 row was described, the light exposure of each point had several deciding by the vertical row's of point range A, B mark Θ, and the mark zero in the time of 0 shows does not have exposure, and the mark Θ in the time of 1 represents that light exposure is 1 unit, the mark in the time of 2 ● represent that then light exposure is 2 units (point range C).In view of the above, mark ● front side by side must be that light exposure reduces by half and becomes mark Θ.

Above-mentioned driving method can not reduce resolution ratio and light exposure is doubled.But if adopt this driving method, then describe row front point light exposure for other light exposures partly.But the electrofax mode then can make the more faithful to original image of exposure by the light exposure that suppresses the front.In addition, the light exposure of describing row end point is reduced by half.

According to present embodiment, provide to make the simultaneously luminous self-scanning light-emitting element array of adjacent two illuminating part IGCTs on each chip.Thereby can prolong because of the time for exposure, make light exposure increase on the photosensitive drums, its result improves the print speed printing speed of light printing equipment.

(the 3rd embodiment)

Present embodiment is can make 2 self-scanned light-emitting device array chips that above light-emitting component is simultaneously luminous are arranged on per 1 chip.

First example

The equivalent circuit of the self-scanned light-emitting device array chip of first example as shown in figure 16, this is to be provided with two circuit in 1 chip.It respectively has 6 illuminating part IGCTs to left and right sides circuit 70L, 70R among the figure in order to make drawing simplify illustration.

Each circuit 70L, 70R are identical with circuit shown in Figure 3, and circuit 70L can transmit luminous point from left to right, and circuit 70R can transmit luminous point from right to left.Identical in the element that constitutes each circuit and the circuit shown in Figure 3.In the circuit 70L of left side,

Refer to clock pulses, Refer to start pulse,

Refer to write signal, 71L refers to

Circuit, 72L refers to

Circuit, 73L refers to

Circuit.In the circuit 70R of left side,

Refer to clock pulses,

The finger start pulse,

Refer to write signal, 71R refers to

Circuit, 72R refers to

Circuit, 73R refers to

Circuit.In addition, also be provided with current-limiting resistance in each circuit.

About this in each circuit, clock pulses

Start pulse

Write signal

Dividing other system as each, as shown in the figure, is power supply V _GKFor shared.Shared V _GKLine is indicated with 74.

Figure 17 is the plane of Figure 16 chip practical structures, and Figure 18 is C-C ' the line profile of Figure 17, and the identical parts with Figure 16 among Figure 17 and 18 are attached to be represented with identical label.

Among Figure 17,75,76L, 77L, 78L, 79L and 76R, 77R, 78R, 79R represent the land, 80 expression illuminating parts.

Shown in the profile of Figure 18, self-scanned light-emitting device array chip is made by the pnpn structure.The Pnpn structure shown in Figure 12 B, be on n type semiconductor chip 40 in turn lamination n type semiconductor layer 41, p type semiconductor conductor layer 42, n type semiconductor layer 43 and p type semiconductor layer 44 are arranged.On diaphragm 45, then be provided with

Circuit 71R, Circuit 72R, Circuit 73R and V _GKCircuit 74 in addition, also is provided with shared medial electrode 52 in the inboard of n type semiconductor chip.

From Figure 16～18 as can be known, this routine self-scanned light-emitting device array chip is to be taken at the structure of inserting 2 self-scanning light-emitting element arrays on 1 chip.

Under said structure,

2 were about circuit was divided into

Line with

Line, every circuit can allow 1 IGCT luminous.Also be that each chip can make 2 IGCTs luminous simultaneously.Therefore can strengthen luminous power, obtain high light output.Though the light-emitting component number of the left and right sides circuit in the last example is identical, and nonessential like this.

Circuit 70L in this example and 70R be respectively from left to right with transmit luminous point from right to left, but not necessarily need get this combining form, in fact be located in the structure at chip two ends in the land, because the start pulse terminal is at the chip two ends, the structure from the chip two ends to center transmission luminous point is easy to make.

Second example

In first example, just simply 2 self-scanning light-emitting element arrays are set up in 1 chip since about exist respectively

Circuit with

Circuit all increases land number and chip area.

For this reason, this example is to make in the circuit of Figure 16

Circuit 71L with

Circuit 71R is connected in the identical land, simultaneously will

Circuit 72L with

Circuit 72R also is connected on the identical land, and the structure of Xing Chenging has reduced by two lands than first example thus.

Represented the sort circuit structure among Figure 19.

Circuit 71L with Circuit 71R is connected to the right side

On the bonding land, and

Circuit 72L with

Circuit 72R then is connected to the left side In the bonding land.

Figure 20 is the plane of practical structures of the chip of Figure 19, and Figure 21 is D-D ' the line profile of Figure 20.In Figure 20 and 21, for Figure 17 and 18 in identical parts are attached represents with identical label.In addition, 77 expressions

The land, 78 expressions The land.

Compare with first example and can reduce by 2 land numbers, therefore can reduce chip area.

The 3rd example

First and second example possesses the start pulse terminal is arranged, but by adopting diode to make clock pulses be also used as start pulse, then can omit the start pulse terminal.

Figure 22 has represented the sort circuit structure.Diode 82 be inserted in left side circuit 70L left end transport unit IGCT the control utmost point with

Between the circuit 72L, simultaneously IGCT 84 is inserted right side circuit 70R left end transport unit IGCT the control utmost point with

Between the circuit 71R.

Figure 23 is the plane of Figure 22 chips practical structures, and Figure 24 is E-E ' the line profile of Figure 23.In the circuit of Figure 23 left side 86 and 88 represented the negative electrode and the anode of diode 82 respectively.

According to this routine circuit, owing to omitted

The land with The land is so can dwindle chip area.In addition, this routine circuit is jointly luminous point to be transmitted from left to right in left side circuit and right side circuit, but is not having

In this structure of land, the illuminating part IGCT owing to freely selecting to start can constitute direction of transfer structure freely.

The 4th example

In second example,

The land in per 1 chip, can have 1, but as shown in figure 19, on chip surface, need and allow 3 spaces that the clock pulses line passes through.Therefore have and make chip area become big problem.For this reason, this example is by being provided with suitable resistance R between the anode of the IGCT of transport unit and clock pulses circuit _B, can be in two

Circuit with

Allow 2 IGCTs luminous on the circuit simultaneously.

Figure 25 has represented this structure, wherein is provided with two

Circuit 30, Circuit 32, and with transport unit IGCT T ₁L, T ₂L, T ₃L ..., T ₁R, T ₂R, T ₃R ... each anode through resistance R _bBe connected respectively to

Circuit 30 with

On the circuit 32.Other structures are identical with Figure 16.

Figure 26 is the plane of practical structures of the chip of Figure 25, and Figure 27 is F-F ' the line profile of Figure 26, and among Figure 26,91 refer to The land, 92 refer to

The land.

Explanation is by being provided with resistance R now _BCan make the mechanism of adjacent 2 transport unit IGCTs conducting simultaneously.Consider Figure 25's

Terminal with

Terminal is in the situation of L level (earth potential).

At this moment, transport unit IGCT T ₁L, T ₁The starting voltage Vth of R is about V _D(diffusion potential of pn knot).Clock pulses

Become the H level, IGCT T ₁L, T ₁A conducting among the R.The anode of the IGCT of conducting is fixed in about V _DThis moment clock pulses Voltage and anode voltage (=V _D) compare to become and be limited to resistance R _BThe high value of voltage drop part.So, before failed the also conducting fast of IGCT of conducting.In other words, IGCT T ₁L and T ₁R conducting simultaneously.Correspondingly, illuminating part L ₁L and L ₁R is simultaneously luminous.

At this moment, transport unit IGCT T ₂L and T ₂The starting voltage V of R _ThAbout 2V _DClock pulses

After becoming the H level, either side can both ON.At this moment the I-V characteristic of transport unit IGCT as shown in figure 28.Characteristic when the I-V characteristic shown in the solid line 94 is 1 IGCT conducting is with V=V _D+ R _B* I represents.Characteristic when the I-V characteristic shown in the dotted line 95 is 2 IGCT conductings is with V=V _D+ (R _B/ 2) * I represents.Characteristic when the I-V characteristic shown in the chain-dotted line 9G is 3 IGCT conductings is with V=V _D+ (R _B/ 3) * I represents.

For making I=3mA, selected resistance R _B, R ₂Behind clock pulses voltage,

The voltage of circuit becomes the starting voltage (=2V than the IGCT of not conducting _D) low value, can only make 1 IGCT luminous.But along with electric current increases,

The voltage of circuit raises, and surpasses starting voltage at last, and the I-V characteristic is transferred to 95,2 IGCT T of dotted line from solid line 94 ₂L and T ₂R conducting simultaneously.

Under the said circumstances, resistance R _BBe chosen to be with current-limiting resistance R2 and can make the conducting of 2 transport unit IGCTs but do not make 3 IGCTs conductings simultaneously (when the conducting of the 3rd IGCT betides and transmits).

Specifically, for electric current I is flow through

Make 2 IGCT conductings during circuit, need to satisfy

V _th<V _D+R _B×I

And in order not make 3 above IGCT conductings, then need satisfy

V _th>V _D+(R _B/2)×I

Above two formulas are solved I, have

2(V _th-V _D)+R _B>I>(V _th-V _D)/R _B

This I is by the H level voltage V of clock pulses _HDetermine with resistance R 2:

I＝(V _th-V _D)+R2

These relational expressions flow through in electric current I

Situation in the circuit is also set up.

Consider that the relation of these formulas and the condition of work of IGCT determine R _BValue with R1, R2.At the I-V of Figure 28 characteristic situation, R _BDuring=375 Ω, become 411 Ω＜R1, R2＜800 Ω.

Form resistance R _BThe time several different methods is arranged, be to set the impurity concentration of anode layer epitaxial film lowly here, regulate to increase between anode and the anode layer contact resistance and as resistance R _B

Resistance R _BAlso available additive method forms, and resistive layer etc. for example can be set between anode and metal wiring also or make independently with semiconductor and metallic film etc. that resistance is connected.

The 5th example

In the structure of first～the 4th example expression is handle

Circuit is arranged at a side (referring to Figure 17, Figure 20, Figure 23 and Figure 26) of illuminating part IGCT row.But when the bigger light exposure of needs, can with

Circuit is divided into two both sides that are divided into the illuminating part IGCT, can make each chip can make 4 illuminating part IGCTs simultaneously luminous thus.

Figure 29 has represented the sort circuit structure and Figure 30 has represented the practical structures of chip, and this example is will in the structure of first example (Figure 16, Figure 17)

Circuit 73L,

Circuit 73R is divided into 2 example respectively.

Make 2 illuminating part IGCTs corresponding to 1 transport unit IGCT, make illuminating part IGCT and 2 among the circuit 70L of left side Circuit 73L (1) and

Circuit 73L (2) connects respectively alternately; Make illuminating part IGCT and 2 among the circuit 70R of left side

Circuit 73R (1) and Circuit 73R (2) connects respectively alternately.

In addition, in Figure 30,79L (1) and 79L (2) represent left side circuit 70L's respectively The land of circuit; 79R (1), 79R (L) represent right side circuit 70R's respectively

The land of circuit.

Under this structure, 2 IGCTs that can make 2 IGCTs at circuit 70L place, left side and circuit 70R place, right side totally 4 whiles luminous.

Make above-mentioned 4 such IGCTs simultaneously luminous structures also can be applicable to second, third and the 4th example.

(the 4th embodiment)

Present embodiment is with the driving method of the self-scanning light-emitting element array of 3.3V power-supply system driving diode combination and the drive circuit of realizing this driving method.

The operating voltage minimum of a value of the box-like self-scanning light-emitting element array of diode junction shown in Figure 3 is by the conducting voltage V decision of transport unit IGCT.IGCT T _nIGCT T under conducting state _N+1Conducting voltage V _t, be similar to control pole tension V as described above _GPn knot diffusion potential V between the+control utmost point and anode _D

More exactly, the conducting voltage of IGCT can be expressed as

V _t＝V _G+V _D+Rp×I _th

Rp in the formula is control utmost point dead resistance, I _ThBe threshold current.Control pole tension V _GCan be expressed as

$V_G=V_{G_{\mathrm{ON}}}+V_D$

V in the formula _GONBe the IGCT T of conducting _nThe control pole tension.When in IGCT is made, having adopted the material of GaAs system, V is arranged then _D=1.2V, V _GON=0.3V, I _Th=10 μ A, and V _t=2.8V.

For making IGCT T _N+1Conducting needs to make IGCT T in IGCT conduction period _N+1Anode voltage surpass conducting voltage V _tTo this IGCT T _N+1Connect

Or

Line charging is as IGCT T _N+1The time of energy conducting is by clock pulses Reach t overlapping time of H level simultaneously _aDecision.

If

With The electric capacity of circuit is C ₁, C ₂, the current-limiting resistance value is R ₁, R ₂, then T was after second when circuit became the H level

Line voltage distribution V1 becomes

V1＝V _H(1-exp(-t/R1×C1))

In the formula, V _HVoltage for the H level.Also be t overlapping time _aBecome the value that satisfies the following formula scope:

V _t<V _H(1-exp(-t _a/R1×C1))

And for Circuit, identical with following formula, have

V _t<V _H(1-exp(-t _a/R2×C2))

At this overlapping time t _aIn, the illuminating part IGCT can not conducting, thereby works as t _aAfter the increase, may luminous time scale reduce.

When using the power supply of 3.3V system, imagination can produce ± 100% voltage pulsation approximately, then must guarantee minimumly to work with 3.0V.When driving,, must increase t overlapping time in order to be charged to 2.8V with supply voltage 3.0V _a

In order to shorten this overlapping time of t _aThough, can reduce clock pulses Current-limiting resistance R1, R2, but if it is reduced, the electric current of the IGCT of then flowing through after the conducting strengthens, and power consumption is increased.

Even be the value that reduces resistance R 1, R2, but overlapping time t _aCan reduce to the limit because of other reasons, these reasons are as follows.Specifically, for the conducting IGCT, the pn knot between the control utmost point and anode needs by suitable direction biasing.Consider at IGCT T now _2nUnder the conducting state, for making IGCT T _2n+1Conducting and make clock pulses

Situation for the H level.When the clock arteries and veins

During for the L level, IGCT T _2n+1Control pole tension V _GBecome than anode voltage V _GHigh voltage.So the pn between the control utmost point and anode forms for anti-inclined to one side.The capacitor C of certain electric charge can stored _pIn see.This electric capacity is in order to pass through dead resistance R _pCharge/discharge roughly has R _p* C _pTime constant, therefore at R _p* C _pAmong＜R1 * C1, R _p* C _pTime constant determine charge/discharge speed.

According to the driving method of present embodiment, by to be no more than conducting voltage V _tVoltage give the clock pulses line charging in advance, even when using, also can shorten t overlapping time with low supply voltage _aSo with transport unit IGCT T _2nMake IGCT T after the conducting _2n+1During conducting, overlapping time t _aFully increase under the situation

The time variation of line voltage distribution is shown among Figure 31, and curve 101 shows when being precharged to 2V

The time of line voltage distribution changes, when curve 102 shows not precharge

The time of line voltage distribution changes.

To Circuit is pre-charged to the situation of 2V, and the about 25ns conducting of IGCT then needs 55ns just to begin conducting when precharge not.Overlapping time t _aOwing to can overlap onto on this ON time, so can shorten.

For the self-scanning light-emitting element array of the diode junction mould assembly of Fig. 3, studied at supply voltage V _GKDuring for 3V, current-limiting resistance R1, pre-charge voltage (1V, 2V, 2.5V) and transmit in required overlapping time t _aThe relation of minimum of a value, its result is illustrated among Figure 32.When not precharge (0V), even make R1 little to 100 Ω, t _aAlso only can be little to about 40ns.But to the precharge of having carried out 2.5V, even R1 is 500 Ω, also can be little to about 10ns.

Though being chosen as pre-charge voltage than conducting voltage at this is low value, because influences such as noise, for making unlikely conducting mistakenly; Preferably make pre-charge voltage than conducting voltage low value surpass 0.2V.

First example

Figure 33 illustration the drive circuit of Fig. 3 diode in conjunction with self-scanning light-emitting element array.Represented self-scanned light-emitting device array chip 110 and drive circuit 112 among Figure 33, on chip 110, represented

V _GK, The land.

According to this drive circuit 112, two kinds of power supply Vp1 (3.3V) and power supply Vp2 (2.5V) have been prepared.In relevant start pulse

With write signal

Formation in, adopted the inverter buffer 160 of CMOS.Inverter buffer 160 is made up of with N-channel MOS FET162 p channel mosfet 161, and the drain electrode of p channel mosfet 161 connects power supply V _p1, the source ground of N-channel MOS FET162.The control utmost point of these two MOSFET is connected on the control signal terminal 120,140 simultaneously.The tie point of the drain electrode of the source electrode of P channel mosfet 161 and N-channel MOS FET162 is by current-limiting resistance R _sWith chip 110

The land links to each other.

In relevant clock pulses

Formation in, used the circuit 170 that 3 analog switches 171,172 and 173 of band control terminal are combined into.When adopting control terminal to be the H level, analog switch 171,172 and 173 connects the type that disconnects during for the L level.One end of switch 172,173 respectively with power supply V _p2, power supply V _p1 connects, and their other end then jointly is connected to an end and the switch 110 of switch 171 by current-limiting resistance R1

On the land, the other end of switch 171 is ground connection then.Each control terminal of switch 171,172,173 is connected with terminal 130,131,132 and terminal 150,151,152 respectively.

The I/O waveform of this drive circuit as shown in figure 34.The waveform on the top of Figure 34 represents to offer chip 110

Waveform, the waveform V (120) of Figure 34 bottom, V (130) ... be the input waveform of control signal in each terminal 120,130... of drive circuit 112.

Start pulse

As control voltage V (120) when becoming the H level, FET161 disconnects and the FET162 conducting is reduced to 0V from 3.3V, and the transport unit IGCT then will be by clock pulses

Conducting.Start pulse

In clock pulses

Return 3.3V. during decline simultaneously

The level of control voltage V (130), V (131), V (132) at first makes switch 171,173 disconnect and connection switch 172 by illustrated this variation, allows

Circuit is pre-charged to 2.5V from 0V, and cut-off switch 172 then, connects switch 171, makes

Circuit rises to 3.3V.

Time t _aThe clock pulses of expression 3.3V

Clock pulses with 3.3V

The overlapping time, time t _bThe expression clock pulses

Drop to write signal respectively

The time of rising, time t _eDeng the expression clock pulses

Become the time of OV respectively, and T represents write signal

Cycle.Time t _bIt is the required time of influence that is used to eliminate before luminous illuminating part IGCT.

In this example because will

Circuit is pre-charged to 2.5V, and as indicated in Figure 31, it is very short that the voltage of these two circuits rises to the time of 3.3V, thereby can shorten t overlapping time _a

This example has been confirmed t _a=30ns, t _b=10ns, t _e=100ns, the operation of T=250ns.

Second example

Though in first example, prepared two kinds of power supplys of 3.3V and 2.5V, preferably used 3.3V power supply.Here in clock pulses

Driving in be provided with the buffer circuit of the level shifter that diode forms in adopting.This circuit is shown among Figure 35.Figure 35 has represented chip 110 and drive circuit 114, is illustrated in the chip 110

V _GK,

The land.

Be provided with the anti-phase buffer circuit of level shifter among the figure 180 refers to, this circuit comprises the p channel mosfet 183 of level shifter that 2 grades of diodes 181,182 form, series connection with it and N-channel MOS FET184, the level shifter p channel mosfet 185 in parallel with the series circuit of p channel mosfet 183 herewith.The source electrode of the anode of diode 181 and p channel mosfet 185 is with power supply V _p(3.3V) connect.The control utmost point of P channel mosfet 183,185 is connection control signal terminal 133,134 and 153,154 respectively.

Be about 0.6V owing to constitute each level of diode 181,182 voltage drops that caused of level shifter, thereby the 1.2V that in 2 grades, descends approximately.In other words, when power supply was 3.3V, the voltage by the diode level shifter became 2.1V.

The I/O waveform table of drive circuit is shown among Figure 36.Adopting clock pulses

With the situation of anti-phase buffer circuit 180 because control voltage V (134) establishes control voltage V (133) for behind the H level during for the H level, FET183 disconnects and the FET184 conducting.Thereby work as

Circuit becomes OV and establishes control voltage V (133) for behind the L level, FET183 conducting and FET184 disconnects, so

Circuit becomes 2.1V.If make control voltage V (134) get just conducting of L level FET185,

Circuit becomes 3.3V.

Why electing diode progression as 2 grades at this, is to be no more than conducting voltage V for the voltage make level shifter when supply voltage fluctuates in 3.0～3.6V scope after _t(=2.8V)

The 3rd example

In first and second example, be to drive with voltage signal to drive circuit.Then be to drive clock pulses in this example with current signal

With circuit.This drive circuit is illustrated among Figure 37.As clock pulses

With drive circuit adopt in parallel with current source 191 (0.2mA) and the current source 192 (1mA) of being with control terminal.

The control terminal of current source 191 is connected with control signal terminal 133,135 respectively, and the control terminal of current source 192 then is connected with control signal terminal 136,156 respectively.This current source 191,192 is when control terminal is the H level, and the electric current that flows through setting respectively is as 200 μ A, 1mA, if during for the L level then no current flow through.Figure 38 represents the I/O waveform of drive circuit.

According to the I-V characteristic of IGCT shown in Figure 39, the anode voltage of the transport unit IGCT when voltage V (135) and V (155) have the electric current of 200 μ A to flow through for the H level is about 2.5V, under this state, and IGCT not conducting fully.Therefore the illuminating part IGCT that is connected with this transport unit IGCT is not luminous.Then, making voltage V (136) and V (156) is the H level, the made transport unit IGCT conducting of flowing through at the electric current that 1.0mA is arranged, thus can make the illuminating part IGCT luminous.Under this mode, obtain with 2.5V precharge

The result that the situation of circuit is identical.

The 4th example

Under first and second routine drive waveforms,, apply 3.3V usually in order to keep the conducting state of transport unit IGCT.But the conducting state of IGCT is if just can fully keep can have the above electric current of maintenance electric current (being about 400 μ A under the I-V characteristic of Figure 39) to flow through the time.For this reason, in ta after the time, as long as make current value keep just keeping conducting fully on the electric current.So in first and second routine circuit, only need the control signal of change drive circuit, just can make t _aAfter time

Voltage descend and reduce power consumption.

Use the drive circuit of first example, drive with the control signal of the waveform of Figure 40.Waveform by illustrated V (130), V (131), V (132) and V (150), V (151), V (152) can obtain illustrated

Waveform.With Figure 34's

Waveform more as can be known, the duration of 3.3V has shortened.

During the conducting of transport unit IGCT

The about 1.6V of the voltage of circuit.So the electric current when being about the situation transport unit IGCT conducting of 500 Ω for the value of current-limiting resistance R1, R2 is 3.4mA down in 3.3V, is 1.8mA when 2.5V, diminishes owing to flow through the current value of IGCT, the power consumption of transport unit can reduce by half.

Equally, the circuit of using second example can shorten the duration of 3.3V, in this case, the consumed power of transport unit is reduced by half.

According to this method of present embodiment, can realize dwindling t overlapping time with the self-scanning light-emitting element array of 3.3V power-supply system driving diode combination _aDriving method, and then can provide the drive circuit of realizing this driving method.

In addition, in above embodiment, clock pulses is with respect to the explanation of 2 phase situations, but obviously present embodiment can be not limited to 2 phase situations, also can be applicable to the self-scanning light-emitting element array of the clock pulses that adopts m (m is 2 above integers) phase.

(the 5th embodiment)

Present embodiment is when light-emitting device array is lined up stagger mode formation light-emitting device array, to be used for being implemented in the chip junction and not produce the light pen of printing striped and be used to realize the rod lens array of this light pen and the collocation method of light-emitting device array.

Version with a plurality of chip alinement shapes is arranged in self-scanning light-emitting element array.Shown in Figure 41 A, make die terminals dock the shape that is arranged in a straight line a plurality of chips 200.In die terminals, the arrangement pitch of light-emitting component 202 is non-constant.For fear of this situation, shown in Figure 41 B, make the part of cake sheet end overlapping, be arranged in so-called stagger mode, at the tie point of chip, the arrangement pitch of light-emitting component is constant.Here so-called tie point is meant place, the chip end light-emitting component foremost and place, the light-emitting device array chip end light-emitting component foremost of opposite side of the light-emitting device array chip of a side, arranges pitch part arranged side by side by 1.Among Figure 41 B the coupling part is surrounded with dotted line 204.

Light-emitting device array has with light-emitting component itself lines up the light-emitting device array that stagger mode is got two array structures.This light-emitting device array can be in the hope of the resolution multiplied resolution ratio of each row light-emitting component.

When the light pen of forming with this light-emitting device array prints, because the structure of rod lens array and the tie point place that is arranged in chip chamber of rod lens array and light-emitting device array, or light-emitting component longitudinally between the adjacent light-emitting component, produces sometimes and prints striped between row and row when lining up the light-emitting device array of stagger mode by 2 row.

The following describes its reason.Figure 42 represents with rod lens 206 by the above-listed and following line that is stacked into the rod lens arrays 209 of two row, is linked to be along the lens arrangement direction with above-listed and following rod lens tie point 208 in Figure 42 as X-axis, and from following the tie point 210 of 2 adjacent rod lens towards X-axis along line that vertical line drew as Y-axis.

In addition, though expression in Figure 42, this rod lens array is that with rod lens rule and strictly precision is arranged in and forms between two backplates, in the gap of rod lens for removing the filling that glares with black resin.

If the diameter of rod lens is D, length is Z, and conjugate length (distances between object and image planes) is TC, and operating distance (distance from lensed endface to the object image-forming face) is Lo, and the refractive index on the lens axis is N.And 2 index distribution constants are g, and at this moment, each rod lens under wavelength 740nm, is established D=0.563mm, Tc=9.1mm, Z=4.45mm, Lo=2.33mm, No=1.627, g=0.843mm ^-1

For this rod lens array, in the scope of the position of X-direction shown in Figure 42 A and B, the light quantity variation with regard to Y direction position y=0mm, 0.05mm and three kinds of situations calculating of 0.10mm X-direction is illustrated respectively in Figure 43 A, 43B, 43C with accordingly result.Among each figure, A represents the position of X=0, and B represents the position that equates with the radius of rod lens on the X-direction.A, B position generally are the above-listed and following contacted positions of rod lens among each at rod lens array.Can see that from these figure along with departing from the y direction of principal axis, the light quantity difference of A, B position increases, when y=0.10mm, have an appointment 10% poor.

With respect to this rod lens array 209, light-emitting device array chip is lined up 2 row by stagger mode, the light-emitting component of one side's chip is arranged corresponding to the y axle of Figure 42, the y place, position that the opposing party's chip light emitting arrangements of components is departed from out 0.10mm on the y direction of principal axis, when the tie point of chip arrived A or B position, light quantity was done discontinuous variation by 10% part.

Calculate according to same viewpoint, under wavelength 780nm, with respect to D=0.88mm, TC=15.3mm, Z=6.93mm, Lo=4.20mm, NO=1.625, g=0.531mm ^-1, h ₄=0.8, h ₆=-3.112, h ₈The result that the MTF of=9.205 rod lens array (spatial frequency 24Lp/mm) carries out is illustrated respectively in Figure 44 A, Figure 44 B and Figure 44 C.

Figure 44 A, 44B, 44C represented the skew (△ TC) of TC be respectively △ TC=0mm ,-0.1mm ,+during 0.1mm, in the value of y direction of principal axis position y=0mm, 0.05mm, 0.10mm.

h ₄, h ₆, h ₈Be high order index distribution constant.MTF (modulation transfer function) is the image quality evaluation index of the image transmission characteristic of expression rod lens array, can be obtained by following formula

$\mathrm{MTF}\left(W\right)=\frac{i\left(w\right)\max -i\left(w\right)\min }{i\left(w\right)\max +i\left(w\right)\min }\&times;100(\%)$

I in the formula (W) max and i (W) min are respectively the maximum and the minimum of the response of spatial frequency W (Lp/mm).MTF is more near 100%, and resolution ratio is just bigger, has also promptly formed real in the picture of former figure.

From Figure 44 A, 44B, 44C as can be known, when rod type lens array is used for best TC position (MTF becomes maximum TC), basically be unquestioned, but in actual applications, even the TC skew for it is believed that about 0.1mm that can not avoid also can have a significant impact with respect to " MTF changes due to the y direction of principal axis position ", in the situation of y=0.10mm, MTF in A, B position is poor, also can be near 20%.As hereinbefore, when the tie point that is arranged in zigzag light-emitting device array chip is in the position of A or B, discontinuous variation takes place.

Figure 45 represents that diameter D is the rod lens array 212 of the rod lens 206 of 0.75mm by two row stacked arrangement one-tenth, with with light-emitting component (light emitting diode for example, luminous IGCT) presses 1200dpi, the self-scanned light-emitting device array chip 214 that 256 light-emitting components (effective length 5.4mm) assortment becomes is arranged into the relation of the light-emitting device array of stagger mode, in Figure 45,216 and 218 expression backplates, 220 expression black resins, the tie point of self-scanned light-emitting device array chip partly is in the contact position place of the above-listed middle rod lens of the rod lens array shown in the arrow C.Like this, when the tie point of light-emitting device array chip was partly come the C position of rod lens array, in the tie point part, the discontinuous variation by light quantity and MTF can produce striped during printing.

Figure 46 represents that diameter D is that the rod lens 206 of 0.6mm is by 2 row stacked arrangement rod lens 212 that becomes and the configuration relation of light-emitting component 222 being got the light-emitting device array 224 of stagger mode arrangement by two row.Rod lens array above-listed or following in the contacted position D of adjacent rod lens, E, F place, in the local time that neighbouring light-emitting component arrives these, identically with Figure 45 can produce the printing striped.

In order not produce this printing striped, key is which type of structure rod lens array gets.Claim now rod lens array perpendicular to its longitudinally direction be its thickness direction, then need make rod lens array get geometric line symmetrical structure along thickness direction; Or get a plurality of rod lens stacked arrangement are become two groups, and allow this first and second group lens arra become overlapping close contacting structure.

For above-mentioned preceding a kind of rod lens array, light-emitting device array chip or light-emitting component can be arranged with respect to get stagger mode by antimeric 2 lines of the line of rod lens array.By means of this arrangement form, because the line symmetry on the geometry of this rod lens array, even light-emitting element chip or light-emitting component are arranged to stagger mode, the situation equivalence that can form a line with light-emitting component when rod lens is observed.Thereby between the tie point of light-emitting device array chip part or the adjacent light-emitting component wherein, discontinuous variation can not take place in light quantity and MTF yet.

To a kind of rod lens array in last aforesaid back, can be with light-emitting device array chip or light-emitting component along first lens arra, second center line of first center line and second lens arra longitudinally, or the interval of former state ground maintenance first center line and second center line, by thickness direction translation, be arranged to stagger mode with respect to formed 2 lines along rod lens array.Compare the two parts that disposed, for the situation that does not have degree of overlapping from the opposing party's light basically, can be regarded as equal position mutually, even thereby light-emitting device array chip or light-emitting component are arranged to stagger mode, when rod lens array is observed, with the light-emitting component situation equivalence that forms a line.In addition, above-mentioned degree of overlapping is arranged the ratio Xo/Do definition of cycle Do with respect to rod lens by the radius of view Xo of rod lens imaging.

First example

Figure 47 represents to dispose with respect to the rod lens array 226 that rod lens 206 becomes with odd column (illustration 3 row among the figure) lamination the example of self-scanned light-emitting device array chips 214.Rod lens array 226 becomes how much line symmetry with respect to the axle 230 of the longitudinal centre line that is equivalent to central array.With respect to symmetry axis 230, subtend is made chiasmus by becoming antimeric 2 lines 242,234 of line with self-scanned light-emitting device array chip 214 then.

According to the structure of above-mentioned this rod lens array and with respect to the layout of the light-emitting device array chip of rod lens array, just can partly avoid discontinuous big light quantity and the variation of MTF at the tie point of light-emitting device array chip.

Second example

Figure 48 is identical with Figure 47, illustration with respect to the stacked rod lens array 226 of 3 row, the light-emitting device array 240 that the light-emitting component chiasmus is constituted.In this example, by antimeric 2 lines 232,234 of line, light-emitting component 242a, 242b are pressed stagger mode arrange with respect to symmetry axis 230, subtend.

Arrange according to the structure of this rod lens array and with respect to the light-emitting component of rod lens array, just can between adjacent 2 light-emitting component 242a, 242b, avoid discontinuous big light quantity and variation MTF.

The 3rd example

Figure 49 illustration the rod lens array 244 (being 2 row in the illustrated example) that becomes by the square arrangement lamination with rod lens 206, and disposed self-scanned light-emitting device array chip 214 therewith relatively.The pros here arrange and pile up, and as shown in figure 49, can be described as the overlapping method that respectively is centered close to foursquare each summit by 4 adjacent up and down rod lens 206.According to this kind overlapping method, rod lens array becomes how much line symmetry with respect to symmetry axis.Then, with respect to symmetry axis 230, subtend is pressed stagger mode with self-scanned light-emitting device array chip 214 and is arranged by 2 lines 232,234 of the part of line symmetry.

According to the structure of above-mentioned rod lens and with respect to the layout of the self-scanned light-emitting device array chip of rod lens, can avoid in the discontinuous big light quantity at the tie point place of chip and the variation of MTF.

The 4th example

Figure 50 is identical with Figure 48, illustration the array 244 of the rod lens that becomes with respect to 2 row square arrangement laminations, the light-emitting device array 240 that light-emitting component is staggered and becomes 2 row and constitute.One with respect to symmetry axle 230 not in this example, and subtend is arranged in stagger mode with light-emitting component 242a, 242b by antimeric 2 lines 232,234 of line.

According to above-mentioned rod lens array structure and with respect to the layout of the light-emitting component of rod lens array, can avoid that discontinuous big light quantity and the variation of MTF are arranged between adjacent 2 light-emitting component 242a, 242b.

The 5th example

In above 4 examples, all adopted the rod lens array that becomes the geometrical line symmetry along thickness direction.Even yet adopt along how much asymmetric rod lens arrays as described below of thickness direction, also can obtain same effect.

Figure 51 represents to get the rod lens array 254 of overlapping close contact structures by rod lens 206 by stacked 2 lens arras 250,252 that constitute of 2 row.The longitudinal centre line of each lens arra 250,252 is with 256,258 expressions, and the longitudinal centre line of rod lens array 254 is with 260 expressions.

This rod lens array 254 of subtend is staggered the center line 256,258 of self-scanned light-emitting device array chip 214 relative each lens arra 250,252.Arranged light-emitting device array chip in this wise, just can with press linearity with respect to rod lens 254 and arrange the situation equivalence of chip.Thereby,, can avoid the variation of discontinuous big light quantity and MTF for the end of a square chip and the end of the opposing party's chip at the tie point place of chip.

In addition, the interval of center line 256 and 258 is remained unchanged light-emitting element chip is staggered, also can try to achieve identical effect with respect to 2 lines that form by thickness direction translation along rod lens array 254.

The 6th example

Figure 52 is routine identical with Figure 51's, has represented with respect to the stacked rod lens array 254 of 4 row, and subtend center line 256,258 is arranged in stagger mode with light-emitting component 242a, 242b and the light-emitting device array 240 that constitutes.According to the structure of this rod lens array and light-emitting component layout, can avoid between 2 light-emitting component 242a, 242b of adjacency, having discontinuous big light quantity and variation MTF with respect to rod lens array.

In addition, keep the interval of center line 256 and 258 constant, light-emitting component is staggered, also can obtain identical effect with respect to 2 lines that form by thickness direction translation along rod lens array 254.

According to present embodiment, light-emitting device array is lined up the light pen of stagger mode, or 2 row light-emitting components are arranged to the light pen of stagger mode with the structure that obtains resolution ratio and double for each column split rate, wherein because tie point/longitudinally adjacent luminous element position place between light-emitting device array chip does not have the variation of discontinuous light quantity and resolution ratio, thereby can provide the tie point/longitudinally adjacent luminous element position place between light-emitting device array chip to be difficult for taking place to print the light pen of striped.

The driving method of self-scanning light-emitting element array of the present invention, self-scanning light-emitting element array and drive circuit can be applied in the light pen of light printing and can realize high-precision light pen.

Claims (6)

1. self-scanned light-emitting device array chip is characterized in that comprising:

First circuit, comprising a plurality of conveying element arrays of arranging by one dimension of 3 terminal conveying elements of control electrode with control starting voltage or threshold current, and the control electrode of adjacent above-mentioned conveying element interconnects by having the unidirectional electric device of voltage or electric current, to the mutual supply of the side in 2 terminals of above-mentioned each conveying element surplus 2 phase clock pulses, by certain conveying element of phase clock pulse conducting of a side time, the starting voltage or the threshold current of near the conveying element of this conveying element are changed by above-mentioned electric device, by the opposing party's the phase clock pulse conducting and the conveying element of above-mentioned certain conveying element adjacency, the a plurality of light-emitting device arrays that are arranged in by one dimension of 3 terminal light-emitting components comprising control electrode with control starting voltage or threshold current, and each control electrode of above-mentioned conveying element is connected on the control electrode of corresponding above-mentioned light-emitting component, then has a side of 2 terminals of the surplus of above-mentioned each light-emitting component to apply 1 the write signal circuit that is used for luminous write signal;

Second circuit, the a plurality of conveying element arrays of arranging by one dimension of 3 terminal conveying elements that wherein have the control electrode of control starting voltage or threshold current, and the control electrode of the above-mentioned conveying element of adjacent second circuit interconnects by having the unidirectional electric device of voltage or electric current, supply with 2 phase clock pulses to the side in 2 terminals of above-mentioned each conveying element surplus of second circuit is mutual from the outside, by certain conveying element of a side phase clock pulse conducting second circuit the time, the starting voltage or the threshold current of near the conveying element of this conveying element are changed by above-mentioned electric device, conveying element by above-mentioned certain conveying element adjacency of the opposing party's phase clock pulse conducting and second circuit, the a plurality of light-emitting device arrays that are arranged in by one dimension of 3 terminal light-emitting components comprising control electrode with control starting voltage or threshold current, and each control electrode of the above-mentioned conveying element of second circuit is connected on the control electrode of above-mentioned light-emitting component of corresponding second circuit, then has a side of 2 terminals of the surplus of above-mentioned each light-emitting component of second circuit to apply 1 the write signal circuit that is used for luminous write signal;

One side's phase clock pulse is supplied with interconnective 2 clock pulses circuits of above-mentioned first and second circuit respectively;

The opposing party's phase clock pulse is supplied with interconnective 2 clock pulses circuits of above-mentioned first and second circuit respectively; And

1 power circuit that is connected with each control electrode of the conveying element of above-mentioned first and second circuit by load resistance.

2. self-scanned light-emitting device array chip is characterized in that comprising:

First circuit, comprising a plurality of conveying element arrays of arranging by one dimension of 3 terminal conveying elements of control electrode with control starting voltage or threshold current, and the control electrode of adjacent above-mentioned conveying element interconnects by having the unidirectional electric device of voltage or electric current, to mutual 2 the clock pulses circuits supplying with 2 phase clock pulses of the side in 2 terminals of above-mentioned each conveying element surplus, by certain conveying element of phase clock pulse conducting of a side time, the starting voltage or the threshold current of near the conveying element of this conveying element are changed by above-mentioned electric device, by the opposing party's the phase clock pulse conducting and the conveying element of above-mentioned certain conveying element adjacency, comprising a plurality of light-emitting device arrays of arranging by one dimension of 3 terminal light-emitting components of control electrode with control starting voltage or threshold current, and each control electrode of above-mentioned conveying element is connected on the control electrode of corresponding above-mentioned light-emitting component, and the side in 2 terminals of the surplus of above-mentioned each light-emitting component then has and applies 1 the write signal circuit that is used for luminous write signal;

Second circuit, the a plurality of conveying element arrays that are arranged in by one dimension of 3 terminal conveying elements comprising control electrode with control starting voltage or threshold current, the control electrode of the above-mentioned conveying element of adjacent second circuit then interconnects by having the unidirectional electric device of voltage or electric current, to mutual 2 the clock pulses circuits supplying with 2 phase clock pulses of the side in 2 terminals of above-mentioned each conveying element surplus of second circuit, by certain conveying element of a side phase clock pulse conducting second circuit the time, the starting voltage or the threshold current of near the conveying element of this conveying element are changed by above-mentioned electric device, conveying element by above-mentioned certain conveying element adjacency of the opposing party's phase clock pulse conducting and second circuit, the a plurality of light-emitting device arrays that are arranged in by one dimension of 3 terminal light-emitting components comprising control electrode with control starting voltage or threshold current, each control electrode of the above-mentioned conveying element of second circuit then is connected on the control electrode of above-mentioned light-emitting component of corresponding second circuit, and the side in 2 terminals of the surplus of above-mentioned each light-emitting component of second circuit then has and applies 1 the write signal circuit that is used for luminous write signal; And

1 power circuit that is connected with each control electrode of the conveying element of above-mentioned first and second circuit by corresponding load resistance,

In above-mentioned first circuit, make a square tube of above-mentioned 2 phase clock pulses cross diode and be connected with the control electrode of the conveying element of conducting at first;

In above-mentioned second circuit, make a square tube of above-mentioned 2 phase clock pulses cross diode and be connected with the control electrode of the conveying element of conducting at first.

3. self-scanned light-emitting device array chip is characterized in that comprising:

First circuit, the a plurality of conveying element arrays that are arranged in by one dimension of 3 terminal conveying elements comprising control electrode with control starting voltage or threshold current, the control electrode of adjacent above-mentioned conveying element then interconnects by having the unidirectional electric device of voltage or electric current, to the mutual supply of the side in 2 terminals of above-mentioned each conveying element surplus 2 phase clock pulses, by certain conveying element of phase clock pulse conducting of a side time, the starting voltage or the threshold current of near the conveying element of this conveying element are changed by above-mentioned electric device, by the opposing party's the phase clock pulse conducting and the conveying element of above-mentioned certain conveying element adjacency, the a plurality of light-emitting device arrays that are arranged in by one dimension of 3 terminal light-emitting components comprising control electrode with control starting voltage or threshold current, each control electrode of above-mentioned conveying element then is connected on the control electrode of corresponding above-mentioned light-emitting component, and the side in 2 terminals of the surplus of above-mentioned each light-emitting component then has and applies 1 the write signal circuit that is used for luminous write signal;

Second circuit, the a plurality of conveying element arrays that are arranged in by one dimension of 3 terminal conveying elements comprising control electrode with control starting voltage or threshold current, the control electrode of the above-mentioned conveying element of adjacent second circuit then interconnects by having the unidirectional electric device of voltage or electric current, supply with 2 phase clock pulses to the side in 2 terminals of above-mentioned each conveying element surplus of second circuit is mutual from the outside, by certain conveying element of a side phase clock pulse conducting second circuit the time, the starting voltage or the threshold current of near the conveying element of this conveying element are changed by above-mentioned electric device, conveying element by above-mentioned certain conveying element adjacency of the opposing party's phase clock pulse conducting and second circuit, the a plurality of light-emitting device arrays that are arranged in by one dimension of 3 terminal light-emitting components comprising control electrode with control starting voltage or threshold current, each control electrode of the above-mentioned conveying element of second circuit then is connected on the control electrode of above-mentioned light-emitting component of corresponding second circuit, and the side in 2 terminals of the surplus of above-mentioned each light-emitting component of second circuit has and applies 1 the write signal circuit that is used for luminous write signal;

One side's phase clock pulse is supplied with 1 first clock pulses circuit of above-mentioned first and second circuit respectively;

Be inserted in 1 first current-limiting resistance in the above-mentioned first clock pulses circuit;

The opposing party's phase clock pulse is supplied with 1 second clock impulse circuit of above-mentioned first and second circuit;

Insert 1 second current-limiting resistance in this second clock impulse circuit;

Be inserted in above-mentioned first and second circuit each conveying element terminal and above-mentioned first or the second clock impulse circuit between the 3rd resistance; And

1 power circuit that is connected with each control electrode of the conveying element of above-mentioned first and second circuit via load resistance.

4. the self-scanned light-emitting device array chip above-mentioned according to claim 3, it is characterized in that, determine above-mentioned first and second current-limiting resistance value and the 3rd resistance value, so that 1 conveying element conducting simultaneously of 1 conveying element of above-mentioned first circuit and second circuit.

5. according to each above-mentioned self-scanned light-emitting device array chip in the claim 1～4, it is characterized in that, each write signal circuits of above-mentioned first and second circuit be divided into 2,

The light-emitting component of above-mentioned first circuit alternately is connected on 2 write signal circuits being cut apart of above-mentioned first circuit via its terminal,

The light-emitting component of above-mentioned second circuit alternately is connected on 2 write signal circuits being cut apart of above-mentioned second circuit via its terminal.

6. according to each above-mentioned self-scanned light-emitting device array chip in the claim 1～4, it is characterized in that the conveying element of above-mentioned first and second circuit and light-emitting component are that the luminous IGCT of 3 terminals by the pnpn structure constitutes.

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